mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-27 13:31:53 +01:00
84 lines
2.9 KiB
ArmAsm
84 lines
2.9 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# mulhsu.S
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#-----------------------------------------------------------------------------
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#
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# Test mulhsu instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
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TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
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TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
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TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
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TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
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TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
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TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
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TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
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TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
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TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
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TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
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TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
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TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
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TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
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TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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