mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-27 13:31:53 +01:00
93 lines
2.5 KiB
ArmAsm
93 lines
2.5 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# sw.S
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#-----------------------------------------------------------------------------
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#
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# Test sw instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Basic tests
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#-------------------------------------------------------------
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TEST_ST_OP( 2, lw, sw, 0x00aa00aa, 0, tdat );
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TEST_ST_OP( 3, lw, sw, 0xaa00aa00, 4, tdat );
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TEST_ST_OP( 4, lw, sw, 0x0aa00aa0, 8, tdat );
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TEST_ST_OP( 5, lw, sw, 0xa00aa00a, 12, tdat );
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# Test with negative offset
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TEST_ST_OP( 6, lw, sw, 0x00aa00aa, -12, tdat8 );
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TEST_ST_OP( 7, lw, sw, 0xaa00aa00, -8, tdat8 );
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TEST_ST_OP( 8, lw, sw, 0x0aa00aa0, -4, tdat8 );
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TEST_ST_OP( 9, lw, sw, 0xa00aa00a, 0, tdat8 );
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# Test with a negative base
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TEST_CASE( 10, x3, 0x12345678, \
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la x1, tdat9; \
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li x2, 0x12345678; \
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addi x4, x1, -32; \
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sw x2, 32(x4); \
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lw x3, 0(x1); \
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)
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# Test with unaligned base
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TEST_CASE( 11, x3, 0x58213098, \
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la x1, tdat9; \
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li x2, 0x58213098; \
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addi x1, x1, -3; \
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sw x2, 7(x1); \
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la x4, tdat10; \
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lw x3, 0(x4); \
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)
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xaabbccdd, 0, tdat );
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TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xdaabbccd, 4, tdat );
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TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xddaabbcc, 8, tdat );
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TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xcddaabbc, 12, tdat );
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TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xccddaabb, 16, tdat );
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TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xbccddaab, 20, tdat );
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TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat );
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TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat );
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TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat );
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TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
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TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
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TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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tdat:
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tdat1: .word 0xdeadbeef
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tdat2: .word 0xdeadbeef
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tdat3: .word 0xdeadbeef
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tdat4: .word 0xdeadbeef
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tdat5: .word 0xdeadbeef
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tdat6: .word 0xdeadbeef
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tdat7: .word 0xdeadbeef
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tdat8: .word 0xdeadbeef
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tdat9: .word 0xdeadbeef
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tdat10: .word 0xdeadbeef
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RVTEST_DATA_END
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