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16 lines
198 B
Systemverilog
16 lines
198 B
Systemverilog
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module sd_cmd (
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input clk,
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input reset,
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sd_scb.cmd sd_scb,
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input sd_clk_rising,
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input sd_clk_falling,
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inout sd_cmd
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);
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assign sd_cmd = 1'bZ;
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endmodule
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