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27 lines
899 B
Systemverilog
27 lines
899 B
Systemverilog
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module fifo_junction (
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fifo_bus.controller dev_bus,
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fifo_bus.fifo cfg_bus,
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fifo_bus.fifo dma_bus
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);
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always_comb begin
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dev_bus.rx_read = cfg_bus.rx_read || dma_bus.rx_read;
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dev_bus.tx_write = cfg_bus.tx_write || dma_bus.tx_write;
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dev_bus.tx_wdata = cfg_bus.tx_write ? cfg_bus.tx_wdata : dma_bus.tx_wdata;
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cfg_bus.rx_empty = dev_bus.rx_empty;
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cfg_bus.rx_almost_empty = dev_bus.rx_almost_empty;
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cfg_bus.rx_rdata = dev_bus.rx_rdata;
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cfg_bus.tx_full = dev_bus.tx_full;
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cfg_bus.tx_almost_full = dev_bus.tx_almost_full;
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dma_bus.rx_empty = dev_bus.rx_empty;
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dma_bus.rx_almost_empty = dev_bus.rx_almost_empty;
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dma_bus.rx_rdata = dev_bus.rx_rdata;
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dma_bus.tx_full = dev_bus.tx_full;
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dma_bus.tx_almost_full = dev_bus.tx_almost_full;
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end
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endmodule
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