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https://github.com/Polprzewodnikowy/SummerCart64.git
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38 lines
816 B
Systemverilog
38 lines
816 B
Systemverilog
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interface usb_scb ();
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logic fifo_flush;
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logic fifo_flush_busy;
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logic write_buffer_flush;
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logic [10:0] rx_count;
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logic [10:0] tx_count;
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logic pwrsav;
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logic reset_state;
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logic reset_on_ack;
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logic reset_off_ack;
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modport controller (
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output fifo_flush,
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input fifo_flush_busy,
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output write_buffer_flush,
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input rx_count,
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input tx_count,
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input pwrsav,
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input reset_state,
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output reset_on_ack,
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output reset_off_ack
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);
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modport usb (
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input fifo_flush,
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output fifo_flush_busy,
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input write_buffer_flush,
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output rx_count,
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output tx_count,
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output pwrsav,
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output reset_state,
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input reset_on_ack,
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input reset_off_ack
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);
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endinterface
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