mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-02 01:54:14 +01:00
39 lines
1.1 KiB
Makefile
39 lines
1.1 KiB
Makefile
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RISCV_TOOLS_PREFIX = /opt/riscv32ic/bin/riscv32-unknown-elf-
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CXX = $(RISCV_TOOLS_PREFIX)g++
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CC = $(RISCV_TOOLS_PREFIX)gcc
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AS = $(RISCV_TOOLS_PREFIX)gcc
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CXXFLAGS = -MD -Os -Wall -std=c++11
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CCFLAGS = -MD -Os -Wall -std=c++11
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LDFLAGS = -Wl,--gc-sections
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LDLIBS = -lstdc++
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test: testbench.vvp firmware32.hex
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vvp -N testbench.vvp
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testbench.vvp: testbench.v ../../picorv32.v
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iverilog -o testbench.vvp testbench.v ../../picorv32.v
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chmod -x testbench.vvp
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firmware32.hex: firmware.elf start.elf hex8tohex32.py
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$(RISCV_TOOLS_PREFIX)objcopy -O verilog start.elf start.tmp
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$(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp
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cat start.tmp firmware.tmp > firmware.hex
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python3 hex8tohex32.py firmware.hex > firmware32.hex
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rm -f start.tmp firmware.tmp
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firmware.elf: firmware.o syscalls.o
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$(CC) $(LDFLAGS) -o $@ $^ -T ../../firmware/riscv.ld $(LDLIBS)
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chmod -x firmware.elf
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start.elf: start.S start.ld
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$(CC) -nostdlib -o start.elf start.S -T start.ld $(LDLIBS)
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chmod -x start.elf
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clean:
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rm -f *.o *.d *.tmp start.elf
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rm -f firmware.elf firmware.hex firmware32.hex
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rm -f testbench.vvp testbench.vcd
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-include *.d
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.PHONY: test clean
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