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https://github.com/Polprzewodnikowy/SummerCart64.git
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18 lines
318 B
Tcl
18 lines
318 B
Tcl
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read_verilog system.v
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read_verilog ../../picorv32.v
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read_xdc synth_system.xdc
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synth_design -part xc7a35t-cpg236-1 -top system
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opt_design
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place_design
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route_design
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report_utilization
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report_timing
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write_verilog -force synth_system.v
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write_bitstream -force synth_system.bit
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# write_mem_info -force synth_system.mmi
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