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34 lines
476 B
Systemverilog
34 lines
476 B
Systemverilog
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module fifo_8kb (
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input clk,
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input reset,
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output empty,
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input read,
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output [7:0] rdata,
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output full,
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input write,
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input [7:0] wdata,
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output logic [10:0] count
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);
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fifo_mock #(
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.DEPTH(1024)
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) fifo_8kb (
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.clk(clk),
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.reset(reset),
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.empty(empty),
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.read(read),
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.rdata(rdata),
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.full(full),
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.write(write),
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.wdata(wdata),
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.count(count)
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);
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endmodule
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