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https://github.com/Polprzewodnikowy/SummerCart64.git
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74 lines
2.0 KiB
ArmAsm
74 lines
2.0 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# beq.S
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#-----------------------------------------------------------------------------
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#
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# Test beq instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Branch tests
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#-------------------------------------------------------------
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# Each test checks both forward and backward branches
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TEST_BR2_OP_TAKEN( 2, beq, 0, 0 );
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TEST_BR2_OP_TAKEN( 3, beq, 1, 1 );
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TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
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TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 );
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TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 );
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TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 );
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TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
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TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
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#-------------------------------------------------------------
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# Test delay slot instructions not executed nor bypassed
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#-------------------------------------------------------------
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TEST_CASE( 21, x1, 3, \
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li x1, 1; \
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beq x0, x0, 1f; \
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addi x1, x1, 1; \
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addi x1, x1, 1; \
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addi x1, x1, 1; \
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addi x1, x1, 1; \
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1: addi x1, x1, 1; \
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addi x1, x1, 1; \
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)
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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