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16 lines
230 B
Systemverilog
16 lines
230 B
Systemverilog
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interface if_cpu_bus_out ();
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logic req;
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logic [3:0] wstrb;
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logic [31:0] address;
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logic [31:0] wdata;
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endinterface
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interface if_cpu_bus_in ();
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logic ack;
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logic [31:0] rdata;
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endinterface
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