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https://github.com/Polprzewodnikowy/SummerCart64.git
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46 lines
1.7 KiB
Systemverilog
46 lines
1.7 KiB
Systemverilog
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module cpu_ram (
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if_system.sys system_if,
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if_cpu_bus_out cpu_bus_if,
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if_cpu_bus_in cpu_ram_if
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);
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wire request;
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wire bank;
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reg ack;
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reg [3:0][7:0] ram1 [0:4095];
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reg [3:0][7:0] ram2 [0:2047];
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reg [31:0] q1;
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reg [31:0] q2;
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wire [31:0] q;
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assign request = (cpu_bus_if.address[31:24] == 8'h00) && cpu_bus_if.req;
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assign bank = cpu_bus_if.address[14];
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assign q = bank ? q2 : q1;
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assign cpu_ram_if.ack = ack & request;
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assign cpu_ram_if.rdata = cpu_ram_if.ack ? q : 32'd0;
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always_ff @(posedge system_if.clk) begin
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ack <= 1'b0;
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if (request) begin
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ack <= 1'b1;
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end
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q1 <= ram1[cpu_bus_if.address[14:2]];
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if (request & !bank) begin
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if (cpu_bus_if.wstrb[0]) ram1[cpu_bus_if.address[13:2]][0] <= cpu_bus_if.wdata[7:0];
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if (cpu_bus_if.wstrb[1]) ram1[cpu_bus_if.address[13:2]][1] <= cpu_bus_if.wdata[15:8];
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if (cpu_bus_if.wstrb[2]) ram1[cpu_bus_if.address[13:2]][2] <= cpu_bus_if.wdata[23:16];
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if (cpu_bus_if.wstrb[3]) ram1[cpu_bus_if.address[13:2]][3] <= cpu_bus_if.wdata[31:24];
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end
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q2 <= ram2[cpu_bus_if.address[12:2]];
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if (request & bank) begin
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if (cpu_bus_if.wstrb[0]) ram2[cpu_bus_if.address[12:2]][0] <= cpu_bus_if.wdata[7:0];
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if (cpu_bus_if.wstrb[1]) ram2[cpu_bus_if.address[12:2]][1] <= cpu_bus_if.wdata[15:8];
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if (cpu_bus_if.wstrb[2]) ram2[cpu_bus_if.address[12:2]][2] <= cpu_bus_if.wdata[23:16];
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if (cpu_bus_if.wstrb[3]) ram2[cpu_bus_if.address[12:2]][3] <= cpu_bus_if.wdata[31:24];
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end
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end
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endmodule
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