mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-23 14:29:14 +01:00
102 lines
2.3 KiB
Systemverilog
102 lines
2.3 KiB
Systemverilog
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interface if_cpu_soc ();
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logic led;
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logic scl;
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logic sda;
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modport peripherals (
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input led,
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inout scl,
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inout sda
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);
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modport cpu (
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output led,
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inout scl,
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inout sda
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);
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endinterface
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module cpu_soc (
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if_system.sys system_if,
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if_cpu_soc.cpu cpu_soc_if
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);
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if_cpu_bus_out cpu_bus_if ();
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wire cpu_ack;
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wire [31:0] cpu_rdata;
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.ENABLE_COUNTERS64(0),
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.ENABLE_REGS_16_31(1),
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.ENABLE_REGS_DUALPORT(1),
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.LATCHED_MEM_RDATA(0),
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.TWO_STAGE_SHIFT(0),
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.BARREL_SHIFTER(0),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(0),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(0),
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.ENABLE_PCPI(0),
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.ENABLE_MUL(0),
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.ENABLE_FAST_MUL(0),
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.ENABLE_DIV(0),
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.ENABLE_IRQ(0),
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.ENABLE_IRQ_QREGS(0),
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.ENABLE_IRQ_TIMER(0),
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.ENABLE_TRACE(0),
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.REGS_INIT_ZERO(0),
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.MASKED_IRQ(32'h0000_0000),
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.LATCHED_IRQ(32'hFFFF_FFFF),
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.PROGADDR_RESET(32'h0100_0000),
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.PROGADDR_IRQ(32'h0000_0010),
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.STACKADDR(32'hFFFF_FFFF)
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) cpu_inst (
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.clk(system_if.clk),
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.resetn(~system_if.reset),
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.mem_valid(cpu_bus_if.req),
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.mem_ready(cpu_ack),
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.mem_addr(cpu_bus_if.address),
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.mem_wdata(cpu_bus_if.wdata),
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.mem_wstrb(cpu_bus_if.wstrb),
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.mem_rdata(cpu_rdata)
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);
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wire scl;
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wire sda;
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assign cpu_soc_if.scl = scl;
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assign cpu_soc_if.sda = sda;
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if_cpu_bus_in cpu_ram_if ();
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cpu_ram cpu_ram_inst (.*);
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if_cpu_bus_in cpu_bootloader_if ();
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cpu_bootloader cpu_bootloader_inst (.*);
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if_cpu_bus_in cpu_led_if ();
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cpu_led cpu_led_inst (.*, .led(cpu_soc_if.led));
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if_cpu_bus_in cpu_i2c_if ();
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cpu_i2c cpu_i2c_inst (.*, .scl(scl), .sda(sda));
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assign cpu_ack = (
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cpu_ram_if.ack |
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cpu_bootloader_if.ack |
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cpu_led_if.ack |
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cpu_i2c_if.ack
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);
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assign cpu_rdata = (
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cpu_ram_if.rdata |
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cpu_bootloader_if.rdata |
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cpu_led_if.rdata |
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cpu_i2c_if.rdata
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);
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endmodule
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