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2021-08-05 19:50:29 +02:00
<session jtag_chain="Arrow-USB-Blaster [AR5GOOMN]" jtag_device="@1: 10M08SA(.|ES)/10M08SC (0x031820DD)" sof_file="output_files/SummerCart64.sof">
<display_tree gui_logging_enabled="0">
<display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
</display_tree>
<instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
<node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
<position_info>
<single attribute="active tab" value="0"/>
<single attribute="data horizontal scroll position" value="0"/>
<single attribute="data vertical scroll position" value="0"/>
<single attribute="setup horizontal scroll position" value="0"/>
<single attribute="setup vertical scroll position" value="0"/>
<single attribute="zoom level denominator" value="1"/>
<single attribute="zoom level numerator" value="4096"/>
<single attribute="zoom offset denominator" value="1"/>
<single attribute="zoom offset numerator" value="11"/>
</position_info>
<signal_set global_temp="1" name="signal_set: 2021/08/05 16:09:12 #0">
<clock name="system:system_inst|system_if.clk" polarity="posedge" tap_mode="classic"/>
<config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" tap_mode="classic"/>
</trigger_input_vec>
<data_input_vec>
<wire name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" tap_mode="classic"/>
</data_input_vec>
<storage_qualifier_input_vec>
<wire name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" tap_mode="classic"/>
<wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" tap_mode="classic"/>
</storage_qualifier_input_vec>
</signal_vec>
<presentation>
<unified_setup_data_view>
<node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
<node data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="66" type="unknown"/>
<node data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="65" type="unknown"/>
<node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="25" type="unknown"/>
<node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="24" type="unknown"/>
<node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="22" type="unknown"/>
<node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="21" type="unknown"/>
<node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="20" type="unknown"/>
<node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="19" type="unknown"/>
<node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="18" type="unknown"/>
<node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="17" type="unknown"/>
<node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="16" type="unknown"/>
<node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="15" type="unknown"/>
<node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="14" type="unknown"/>
<node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="13" type="unknown"/>
<node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="11" type="unknown"/>
<node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="10" type="unknown"/>
<node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="9" type="unknown"/>
<node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="8" type="unknown"/>
<node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="7" type="unknown"/>
<node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="6" type="unknown"/>
<node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="5" type="unknown"/>
<node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="4" type="unknown"/>
<node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="3" type="unknown"/>
<node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="2" type="unknown"/>
<node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="32" type="unknown"/>
<node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="31" type="unknown"/>
<node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="30" type="unknown"/>
<node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="29" type="unknown"/>
<node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="28" type="unknown"/>
<node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="27" type="unknown"/>
<node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="26" type="unknown"/>
<node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="23" type="unknown"/>
<node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="12" type="unknown"/>
<node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="1" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<node data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="57" type="unknown"/>
<node data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="56" type="unknown"/>
<node data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="54" type="unknown"/>
<node data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="53" type="unknown"/>
<node data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="52" type="unknown"/>
<node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="51" type="unknown"/>
<node data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="50" type="unknown"/>
<node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="49" type="unknown"/>
<node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="48" type="unknown"/>
<node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="47" type="unknown"/>
<node data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="46" type="unknown"/>
<node data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="45" type="unknown"/>
<node data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="43" type="unknown"/>
<node data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="42" type="unknown"/>
<node data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="41" type="unknown"/>
<node data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="40" type="unknown"/>
<node data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="39" type="unknown"/>
<node data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="38" type="unknown"/>
<node data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="37" type="unknown"/>
<node data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="36" type="unknown"/>
<node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="35" type="unknown"/>
<node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="34" type="unknown"/>
<node data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="64" type="unknown"/>
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<node data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="55" type="unknown"/>
<node data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="44" type="unknown"/>
<node data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="33" type="unknown"/>
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<node data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="101" type="unknown"/>
<node data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="100" type="unknown"/>
<node data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="99" type="unknown"/>
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<node data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="90" type="unknown"/>
<node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="88" type="unknown"/>
<node data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="87" type="unknown"/>
<node data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="86" type="unknown"/>
<node data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="85" type="unknown"/>
<node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="84" type="unknown"/>
<node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="83" type="unknown"/>
<node data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="82" type="unknown"/>
<node data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="81" type="unknown"/>
<node data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="80" type="unknown"/>
<node data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="79" type="unknown"/>
<node data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="77" type="unknown"/>
<node data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="76" type="unknown"/>
<node data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="75" type="unknown"/>
<node data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="74" type="unknown"/>
<node data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="73" type="unknown"/>
<node data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="72" type="unknown"/>
<node data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="71" type="unknown"/>
<node data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="70" type="unknown"/>
<node data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="69" type="unknown"/>
<node data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="68" type="unknown"/>
<node data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="98" type="unknown"/>
<node data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="97" type="unknown"/>
<node data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="96" type="unknown"/>
<node data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="95" type="unknown"/>
<node data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="94" type="unknown"/>
<node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="93" type="unknown"/>
<node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="92" type="unknown"/>
<node data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="89" type="unknown"/>
<node data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="78" type="unknown"/>
<node data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="67" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<node data_index="1" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
</node>
<node data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="103" type="unknown"/>
</unified_setup_data_view>
<data_view>
<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
<net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="66" type="unknown"/>
<net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="65" type="unknown"/>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="25" type="unknown"/>
<net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="24" type="unknown"/>
<net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="22" type="unknown"/>
<net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="21" type="unknown"/>
<net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="20" type="unknown"/>
<net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="19" type="unknown"/>
<net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="18" type="unknown"/>
<net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="17" type="unknown"/>
<net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="16" type="unknown"/>
<net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="15" type="unknown"/>
<net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="14" type="unknown"/>
<net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="13" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="11" type="unknown"/>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="10" type="unknown"/>
<net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="9" type="unknown"/>
<net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="8" type="unknown"/>
<net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="7" type="unknown"/>
<net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="6" type="unknown"/>
<net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="5" type="unknown"/>
<net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="4" type="unknown"/>
<net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="3" type="unknown"/>
<net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="2" type="unknown"/>
<net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="32" type="unknown"/>
<net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="31" type="unknown"/>
<net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="30" type="unknown"/>
<net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="29" type="unknown"/>
<net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="28" type="unknown"/>
<net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="27" type="unknown"/>
<net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="26" type="unknown"/>
<net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="23" type="unknown"/>
<net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="12" type="unknown"/>
<net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="1" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="57" type="unknown"/>
<net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="56" type="unknown"/>
<net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="54" type="unknown"/>
<net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="53" type="unknown"/>
<net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="52" type="unknown"/>
<net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="51" type="unknown"/>
<net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="50" type="unknown"/>
<net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="49" type="unknown"/>
<net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="48" type="unknown"/>
<net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="47" type="unknown"/>
<net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="46" type="unknown"/>
<net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="45" type="unknown"/>
<net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="43" type="unknown"/>
<net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="42" type="unknown"/>
<net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="41" type="unknown"/>
<net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="40" type="unknown"/>
<net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="39" type="unknown"/>
<net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="38" type="unknown"/>
<net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="37" type="unknown"/>
<net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="36" type="unknown"/>
<net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="35" type="unknown"/>
<net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="34" type="unknown"/>
<net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="64" type="unknown"/>
<net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="63" type="unknown"/>
<net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="62" type="unknown"/>
<net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="61" type="unknown"/>
<net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="60" type="unknown"/>
<net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="59" type="unknown"/>
<net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="58" type="unknown"/>
<net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="55" type="unknown"/>
<net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="44" type="unknown"/>
<net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="33" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="102" type="unknown"/>
<net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="101" type="unknown"/>
<net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="100" type="unknown"/>
<net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="99" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="91" type="unknown"/>
<net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="90" type="unknown"/>
<net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="88" type="unknown"/>
<net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="87" type="unknown"/>
<net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="86" type="unknown"/>
<net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="85" type="unknown"/>
<net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="84" type="unknown"/>
<net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="83" type="unknown"/>
<net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="82" type="unknown"/>
<net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="81" type="unknown"/>
<net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="80" type="unknown"/>
<net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="79" type="unknown"/>
<net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="77" type="unknown"/>
<net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="76" type="unknown"/>
<net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="75" type="unknown"/>
<net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="74" type="unknown"/>
<net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="73" type="unknown"/>
<net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="72" type="unknown"/>
<net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="71" type="unknown"/>
<net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="70" type="unknown"/>
<net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="69" type="unknown"/>
<net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="68" type="unknown"/>
<net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="98" type="unknown"/>
<net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="97" type="unknown"/>
<net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="96" type="unknown"/>
<net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="95" type="unknown"/>
<net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="94" type="unknown"/>
<net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="93" type="unknown"/>
<net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="92" type="unknown"/>
<net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="89" type="unknown"/>
<net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="78" type="unknown"/>
<net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="67" type="unknown"/>
</bus>
<net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="103" type="unknown"/>
</data_view>
<setup_view>
<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
<net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="66" type="unknown"/>
<net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="65" type="unknown"/>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="25" type="unknown"/>
<net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="24" type="unknown"/>
<net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="22" type="unknown"/>
<net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="21" type="unknown"/>
<net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="20" type="unknown"/>
<net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="19" type="unknown"/>
<net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="18" type="unknown"/>
<net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="17" type="unknown"/>
<net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="16" type="unknown"/>
<net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="15" type="unknown"/>
<net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="14" type="unknown"/>
<net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="13" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="11" type="unknown"/>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="10" type="unknown"/>
<net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="9" type="unknown"/>
<net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="8" type="unknown"/>
<net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="7" type="unknown"/>
<net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="6" type="unknown"/>
<net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="5" type="unknown"/>
<net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="4" type="unknown"/>
<net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="3" type="unknown"/>
<net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="2" type="unknown"/>
<net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="32" type="unknown"/>
<net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="31" type="unknown"/>
<net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="30" type="unknown"/>
<net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="29" type="unknown"/>
<net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="28" type="unknown"/>
<net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="27" type="unknown"/>
<net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="26" type="unknown"/>
<net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="23" type="unknown"/>
<net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="12" type="unknown"/>
<net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="1" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="57" type="unknown"/>
<net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="56" type="unknown"/>
<net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="54" type="unknown"/>
<net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="53" type="unknown"/>
<net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="52" type="unknown"/>
<net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="51" type="unknown"/>
<net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="50" type="unknown"/>
<net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="49" type="unknown"/>
<net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="48" type="unknown"/>
<net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="47" type="unknown"/>
<net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="46" type="unknown"/>
<net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="45" type="unknown"/>
<net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="43" type="unknown"/>
<net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="42" type="unknown"/>
<net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="41" type="unknown"/>
<net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="40" type="unknown"/>
<net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="39" type="unknown"/>
<net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="38" type="unknown"/>
<net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="37" type="unknown"/>
<net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="36" type="unknown"/>
<net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="35" type="unknown"/>
<net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="34" type="unknown"/>
<net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="64" type="unknown"/>
<net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="63" type="unknown"/>
<net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="62" type="unknown"/>
<net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="61" type="unknown"/>
<net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="60" type="unknown"/>
<net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="59" type="unknown"/>
<net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="58" type="unknown"/>
<net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="55" type="unknown"/>
<net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="44" type="unknown"/>
<net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="33" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="102" type="unknown"/>
<net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="101" type="unknown"/>
<net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="100" type="unknown"/>
<net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="99" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="91" type="unknown"/>
<net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="90" type="unknown"/>
<net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="88" type="unknown"/>
<net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="87" type="unknown"/>
<net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="86" type="unknown"/>
<net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="85" type="unknown"/>
<net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="84" type="unknown"/>
<net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="83" type="unknown"/>
<net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="82" type="unknown"/>
<net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="81" type="unknown"/>
<net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="80" type="unknown"/>
<net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="79" type="unknown"/>
<net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="77" type="unknown"/>
<net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="76" type="unknown"/>
<net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="75" type="unknown"/>
<net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="74" type="unknown"/>
<net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="73" type="unknown"/>
<net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="72" type="unknown"/>
<net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="71" type="unknown"/>
<net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="70" type="unknown"/>
<net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="69" type="unknown"/>
<net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="68" type="unknown"/>
<net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="98" type="unknown"/>
<net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="97" type="unknown"/>
<net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="96" type="unknown"/>
<net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="95" type="unknown"/>
<net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="94" type="unknown"/>
<net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="93" type="unknown"/>
<net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="92" type="unknown"/>
<net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="89" type="unknown"/>
<net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="78" type="unknown"/>
<net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="67" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
<net data_index="1" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
</bus>
<net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="103" type="unknown"/>
</setup_view>
<trigger_in_editor/>
<trigger_out_editor/>
</presentation>
<trigger CRC="8B574246" attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2021/08/05 17:55:26 #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1024" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no"/>
<events use_custom_flow_control="no">
<level enabled="yes" name="condition1" type="basic">'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]' == high &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid' == rising edge
<power_up enabled="yes">
</power_up>
<op_node/>
</level>
</events>
<storage_qualifier_events>
<transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
<pwr_up_transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
</storage_qualifier_events>
<log>
<data global_temp="1" name="log: Trig @ 2021/08/05 18:09:40 (0:0:1.3 elapsed)" power_up_mode="false" sample_depth="1023" trigger_position="-1">000000000000000001000000000111100000000000000000000000000000000000001110011110100000000001001000110000010000000000000000010000000001111000000000000000000000000000000000000011100111101000000000010010001100000100000000000000000100000100011110000000000000000000000000000000000010111001111010000000000100100011000001000000000000000001000001000111100110000111101100000000000001001011101110011110100000000001001000110000010000000000000000010000010001111000000000000000000000000000000000000011100111101000000000010010001100000100000000000000000000000000000000000000000000000000000000000000000010111001111010000000000100100011000001000000000000000000000000000000000011100111101000000000010010001101101110011110100000000001001000110000010000000000000000000000000000000000000000000000000000000000000000000011100111101000000000010010001100000100000000000000000000000000000000000000000000000000000000000000000000111001111010000000000100100011000001000000000000000001000000001111100000000000000000000000000000000000101110011110100000000001001000110000010000000000000000010000000011111001000100000011011000000000001000011011100111101000000000010010001100000100000000000000000100000000111110000000000000000000000000000000000000111001111010000000000100100011000001000000000000000001000000001111100000000000000000000000000000000000001110011110100000000001001000110000010000000000000000010000010011111000000000000000000000000000000000001011100111101000000000010010001100000100000000000000000100000100111110011000000000110000000001000110011110111001111010000000000100100011000001000000000000000001000001001111100000000000000000000000000000000000001110011110100000000001001000110000010000000000000000000000000000000000000000000000000000000000000000001111100111101000000000010010001101111100000000000000000000000000000000001110011110100000000001001000110111111001111010000000000100100011011111000000000000000000000000000000000000000000000000000000000000000000011110011110100000000001001000110111110000000000000000000000000000000000000000000000000000000000000000000111100111101000000000010010001101111100000000000000000100000000000001000000000000000000000000000000000011111001111010000000000100100011000001000000000000000001000000000000010110000011101111111111101101000111111110011110100000000001001000110000010000000000000000010000000000000100000000000000000000000000000000000111100111101000000000010010001100000100000000000000000100000000000001000000000000000000000000000000000001111001111010000000000100100011000001000000000000000001000001000000010000000000000000000000000000000000111110011110100000000001001000110000010000000000000000010000010000000101101001111010111011111011001110111111100111101000000000010010001100000100000000000000000100000100000001000000000000000000000000000000000001111001111010000000000100100011000001000000000000000001000001000000010000000000000000000000000000000000011110011110100000000001001000110000010000000000000000010000000010000100000000000000000000000000000000001111100111101000000000010010001100000100000000000000000100000000100001011000000000100000000001010110111111111001111010000000000100100011000001000000000000000001000000001000010000000000000000000000000000000000011110011110100000000001001000110000010000000000000000010000000001111000000000000000000000000000000000001111100111101000000000010010001100000100000000000000000100000000011110011001000000100000000000000000111111111001111010000000000100100011000001000000000000000001000000000111100000000000000000000000000000000000011110011110100000000001001000110000010000000000000000010000000001111000000000000000000000000000000000000111100111101000000000010010001100000100000000000000000100000100011110000000000000000000000000000000000011111001111010000000000100100011000001000000000000000001000001000111100110000111101100000000000001001011111110011110100000000001001000110000010000000000000000010000010001111000000000000000000000000000000000000111100111101000000000010010
<extradata>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>
</log>
</trigger>
</signal_set>
</instance>
<mnemonics/>
<static_plugin_mnemonics/>
<global_info>
<single attribute="active instance" value="0"/>
<single attribute="config widget visible" value="1"/>
<single attribute="data log widget visible" value="0"/>
<single attribute="hierarchy widget visible" value="0"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="jtag widget visible" value="1"/>
<single attribute="lock mode" value="0"/>
<multi attribute="frame size" size="2" value="1675,673"/>
<multi attribute="jtag widget size" size="2" value="348,135"/>
</global_info>
</session>
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