[SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19)
* isv support + usb/dd improvements
* make room for saves
* update offset
* fixed debug address
* idk
* exception
* ironed out all broken stuff
* cleanup
* return epc fix
* better
* more cleanup
* even more cleanup
* mooore cleanup
* fixed printf
* no assert
* improved docker build, pyft232 instead of pyserial
* fixed displaying long message strings
description test
* just straight cleanup
* smallest cleanup
* PAL
* cpu buffer
* n64 bootloader done
* super slow usb storage reading implemented
* reduced buffer size
* usb gets fast
* little cleanup
* double buffered reads
* removed separate event id
* ISV in hardware finally
* small exception changes
* mac testing
* py spacing
* fsd write, rtc, isv and reset fixes
* fixxx
* good stopping point
* usb fixed?
* pretend we have 128 MB sdram
* backup
* chmod
* test
* test done
* more tests
* user rm
* help
* final fix
* updated component values
* nice asset names
* cic 64dd support
* ddipl enable separation
* pre DMA rewrite, created dedicated buffer memory space, simplified code
* dma rewrite, needs testing
* moved xml
* dd basics
* timing
* 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite
* added usb read functionality, general cleanup
* changed mem addressing
* added fpga flash update access
* added mcu update
* chmod
* little cleanup
* update format and stuff
* fixes
* uninitialized fix
* small fixes
* update fixes
* update stuff done
* fpga update tested
* build time fix
* boot fix
* test timing
* readme test
* test 2
* reports
* testseet
* final
* build test
* forgot
* button and naming
* General cleanup
And multiline commit message test
* Exception screen UI touch ups
* display separation and tests beginning
* pc software update
* pc software done
* timing test
* delete launch.json
* sw fixes
* fixed button hole diameter in shell
* small cleanup, rpi testing
* shell fillet fix, pc rtc printing
* added cfg lock mechanism
* moved lock to cfg address space
* extended ROM and ISV fixes
* preliminary sd card support
* little sd card cleanup
* sd menu fixes
* 5 second limit
* reduced shell thickness
* basic led act blinking
* faster sd menu loading
* inst cache invalidate
* sd card writing is working
* SD card CSD and CID registers
* wait for previous command
* led error codes
* fixed cfg_translate_address use
* 64dd from sd card working
* 64dd speedup and button handling
* delayed address latching cycle - might break other builds, needs testing
* bootloader improvements
* small fixes
* return previous cfg when setting new
* cache stuff
* unfloader debug protocol support
* UNFLoader style debug command line support
* requirements.txt
* shell groove fillet
* reset state inside controller
* fixed fast PI read, added PI R/W fifo debug info
* PI access prioritize
* SD clock stop when RX FIFO is more than half full
* flash erase method change
* CFG error handling, TLOZ MM debug ISV support
* CIC5167 support
* general fixes
* USB unplugged cable handling
* turn off led when changing between error/act modes
* rtc 2 bit clock stop support
* line endings
* Revert "line endings"
This reverts commit d0ddfe5ec716d2db7c72561703f51a94bf34e6bb.
* PI address debug
* readme test
* diagram update
* diagram background
* diagram background
* diagram background
* updated readme
2022-11-10 11:46:54 +01:00
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#include <stdint.h>
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#include "fpga.h"
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#define FLASHRAM_SIZE (128 * 1024)
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#define FLASHRAM_SECTOR_SIZE (16 * 1024)
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#define FLASHRAM_PAGE_SIZE (128)
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#define FLASHRAM_ADDRESS (0x03FE0000UL)
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#define FLASHRAM_BUFFER_ADDRESS (0x05002900UL)
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enum operation {
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OP_NONE,
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OP_ERASE_ALL,
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OP_ERASE_SECTOR,
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OP_WRITE_PAGE
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};
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static enum operation flashram_operation_type (uint32_t scr) {
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if (!(scr & FLASHRAM_SCR_PENDING)) {
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return OP_NONE;
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}
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if (scr & FLASHRAM_SCR_WRITE_OR_ERASE) {
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if (scr & FLASHRAM_SCR_SECTOR_OR_ALL) {
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return OP_ERASE_ALL;
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} else {
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return OP_ERASE_SECTOR;
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}
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} else {
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return OP_WRITE_PAGE;
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}
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}
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void flashram_init (void) {
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2022-11-24 22:55:05 +01:00
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if (fpga_reg_get(REG_FLASHRAM_SCR) & FLASHRAM_SCR_PENDING) {
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fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE);
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}
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[SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19)
* isv support + usb/dd improvements
* make room for saves
* update offset
* fixed debug address
* idk
* exception
* ironed out all broken stuff
* cleanup
* return epc fix
* better
* more cleanup
* even more cleanup
* mooore cleanup
* fixed printf
* no assert
* improved docker build, pyft232 instead of pyserial
* fixed displaying long message strings
description test
* just straight cleanup
* smallest cleanup
* PAL
* cpu buffer
* n64 bootloader done
* super slow usb storage reading implemented
* reduced buffer size
* usb gets fast
* little cleanup
* double buffered reads
* removed separate event id
* ISV in hardware finally
* small exception changes
* mac testing
* py spacing
* fsd write, rtc, isv and reset fixes
* fixxx
* good stopping point
* usb fixed?
* pretend we have 128 MB sdram
* backup
* chmod
* test
* test done
* more tests
* user rm
* help
* final fix
* updated component values
* nice asset names
* cic 64dd support
* ddipl enable separation
* pre DMA rewrite, created dedicated buffer memory space, simplified code
* dma rewrite, needs testing
* moved xml
* dd basics
* timing
* 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite
* added usb read functionality, general cleanup
* changed mem addressing
* added fpga flash update access
* added mcu update
* chmod
* little cleanup
* update format and stuff
* fixes
* uninitialized fix
* small fixes
* update fixes
* update stuff done
* fpga update tested
* build time fix
* boot fix
* test timing
* readme test
* test 2
* reports
* testseet
* final
* build test
* forgot
* button and naming
* General cleanup
And multiline commit message test
* Exception screen UI touch ups
* display separation and tests beginning
* pc software update
* pc software done
* timing test
* delete launch.json
* sw fixes
* fixed button hole diameter in shell
* small cleanup, rpi testing
* shell fillet fix, pc rtc printing
* added cfg lock mechanism
* moved lock to cfg address space
* extended ROM and ISV fixes
* preliminary sd card support
* little sd card cleanup
* sd menu fixes
* 5 second limit
* reduced shell thickness
* basic led act blinking
* faster sd menu loading
* inst cache invalidate
* sd card writing is working
* SD card CSD and CID registers
* wait for previous command
* led error codes
* fixed cfg_translate_address use
* 64dd from sd card working
* 64dd speedup and button handling
* delayed address latching cycle - might break other builds, needs testing
* bootloader improvements
* small fixes
* return previous cfg when setting new
* cache stuff
* unfloader debug protocol support
* UNFLoader style debug command line support
* requirements.txt
* shell groove fillet
* reset state inside controller
* fixed fast PI read, added PI R/W fifo debug info
* PI access prioritize
* SD clock stop when RX FIFO is more than half full
* flash erase method change
* CFG error handling, TLOZ MM debug ISV support
* CIC5167 support
* general fixes
* USB unplugged cable handling
* turn off led when changing between error/act modes
* rtc 2 bit clock stop support
* line endings
* Revert "line endings"
This reverts commit d0ddfe5ec716d2db7c72561703f51a94bf34e6bb.
* PI address debug
* readme test
* diagram update
* diagram background
* diagram background
* diagram background
* updated readme
2022-11-10 11:46:54 +01:00
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}
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void flashram_process (void) {
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uint32_t scr = fpga_reg_get(REG_FLASHRAM_SCR);
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enum operation op = flashram_operation_type(scr);
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uint8_t buffer[FLASHRAM_PAGE_SIZE];
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uint32_t address = FLASHRAM_ADDRESS;
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uint32_t erase_size = (op == OP_ERASE_SECTOR) ? FLASHRAM_SECTOR_SIZE : FLASHRAM_SIZE;
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uint32_t page = (op != OP_ERASE_ALL) ? ((scr & FLASHRAM_SCR_PAGE_MASK) >> FLASHRAM_SCR_PAGE_BIT) : 0;
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address += page * FLASHRAM_PAGE_SIZE;
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switch (op) {
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case OP_ERASE_ALL:
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case OP_ERASE_SECTOR:
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for (int i = 0; i < FLASHRAM_PAGE_SIZE; i++) {
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buffer[i] = 0xFF;
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}
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for (int i = 0; i < erase_size; i += FLASHRAM_PAGE_SIZE) {
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fpga_mem_write(address + i, FLASHRAM_PAGE_SIZE, buffer);
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}
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fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE);
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break;
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case OP_WRITE_PAGE:
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fpga_mem_copy(FLASHRAM_BUFFER_ADDRESS, address, FLASHRAM_PAGE_SIZE);
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fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE);
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break;
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case OP_NONE:
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default:
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break;
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}
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}
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