diff --git a/build.sh b/build.sh
index d5b0ef2..65306fb 100755
--- a/build.sh
+++ b/build.sh
@@ -75,12 +75,13 @@ build_update () {
     if [ "$FORCE_CLEAN" = true ]; then
         rm -f ./sc64.upd
     fi
-    INFO=""
-    if [ ! -z "${GIT_BRANCH+x}" ]; then INFO+=" $GIT_BRANCH"; fi
-    if [ ! -z "${GIT_TAG+x}" ]; then INFO+=" $GIT_TAG"; fi
-    if [ ! -z "${GIT_SHA+x}" ]; then INFO+=" $GIT_SHA"; fi
+    GIT_INFO=""
+    if [ ! -z "${GIT_BRANCH+x}" ]; then GIT_INFO+="branch: $GIT_BRANCH "; fi
+    if [ ! -z "${GIT_TAG+x}" ]; then GIT_INFO+="tag: $GIT_TAG "; fi
+    if [ ! -z "${GIT_SHA+x}" ]; then GIT_INFO+="sha: $GIT_SHA "; fi
+    GIT_INFO=$(echo "$GIT_INFO" | xargs)
     python3 update.py \
-        --info "$INFO" \
+        --git "$GIT_INFO" \
         --mcu ../controller/build/app/app.bin \
         --fpga ../../fw/project/lcmxo2/impl1/sc64_impl1.jed \
         --boot ../bootloader/build/bootloader.bin \
diff --git a/docker_build.sh b/docker_build.sh
index b3e3912..bdcb5cf 100755
--- a/docker_build.sh
+++ b/docker_build.sh
@@ -19,6 +19,7 @@ docker run \
     --mac-address ${MAC_ADDRESS:-F8:12:34:56:78:90} \
     --mount type=bind,src="$(pwd)/flexlm",target="/flexlm" \
     --mount type=bind,src="$(pwd)",target="/workdir" \
+    -h=`hostname` \
     -e GIT_BRANCH="$GIT_BRANCH" \
     -e GIT_TAG="$GIT_TAG" \
     -e GIT_SHA="$GIT_SHA" \
diff --git a/fw/project/lcmxo2/sc64.ldf b/fw/project/lcmxo2/sc64.ldf
index 9bdab48..d00a47e 100644
--- a/fw/project/lcmxo2/sc64.ldf
+++ b/fw/project/lcmxo2/sc64.ldf
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <BaliProject version="3.2" title="sc64" device="LCMXO2-7000HC-6TG144C" default_implementation="impl1">
     <Options/>
-    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="release">
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="debug">
         <Options VerilogStandard="System Verilog" def_top="top" top="top"/>
         <Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>