From 06aa5c9de20ee21264e7b4ac0c762b835a284226 Mon Sep 17 00:00:00 2001
From: Polprzewodnikowy <sc@mateuszfaderewski.pl>
Date: Tue, 16 Nov 2021 22:13:56 +0100
Subject: [PATCH] reset vector update

---
 fw/rtl/cpu/cpu_wrapper.sv |  2 +-
 fw/rtl/system/sc64.sv     | 12 +++++-------
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/fw/rtl/cpu/cpu_wrapper.sv b/fw/rtl/cpu/cpu_wrapper.sv
index 7c1bd8e..aaededc 100644
--- a/fw/rtl/cpu/cpu_wrapper.sv
+++ b/fw/rtl/cpu/cpu_wrapper.sv
@@ -33,7 +33,7 @@ module cpu_wrapper (
         .ENABLE_COUNTERS64(0),
         .CATCH_MISALIGN(0),
         .CATCH_ILLINSN(0),
-        .PROGADDR_RESET({4'(sc64::ID_CPU_FLASH), 28'h003_5800})
+        .PROGADDR_RESET(sc64::CPU_RESET_VECTOR)
     ) cpu_inst (
         .clk(sys.clk),
         .resetn(~sys.reset),
diff --git a/fw/rtl/system/sc64.sv b/fw/rtl/system/sc64.sv
index 56f5aae..b14c128 100644
--- a/fw/rtl/system/sc64.sv
+++ b/fw/rtl/system/sc64.sv
@@ -30,12 +30,10 @@ package sc64;
         __ID_DMA_END
     } e_dma_id;
 
-    parameter bit [31:0] SC64_VER   = 32'h53437632;
-
-    parameter int CLOCK_FREQUENCY   = 32'd100_000_000;
-
-    parameter bit CPU_HAS_UART      = 1'b0;
-
-    parameter int UART_BAUD_RATE    = 32'd1_000_000;
+    parameter bit [31:0] SC64_VER           = 32'h53437632;
+    parameter int CLOCK_FREQUENCY           = 32'd100_000_000;
+    parameter bit [31:0] CPU_RESET_VECTOR   = {4'(ID_CPU_FLASH), 28'h0035800};
+    parameter bit CPU_HAS_UART              = 1'b0;
+    parameter int UART_BAUD_RATE            = 32'd1_000_000;
 
 endpackage