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dd write works
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Polprzewodnikowy
parent
0bb73dac1c
commit
099d0bc91c
@ -29,7 +29,12 @@ module cpu_dd (
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bus.rdata = 32'd0;
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if (bus.ack) begin
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if (bus.address[8] == M_SECTOR_BUFFER[8]) begin
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bus.rdata = dd.sector_rdata;
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bus.rdata = {
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dd.sector_rdata[7:0],
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dd.sector_rdata[15:8],
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dd.sector_rdata[23:16],
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dd.sector_rdata[31:24]
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};
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end else begin
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case (bus.address[5:2])
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R_SCR: bus.rdata = {
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@ -48,6 +48,8 @@ class SC64:
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__DEBUG_ID_FSD_SECTOR = 0xF3
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__DEBUG_ID_DD_BLOCK = 0xF5
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__DD_USER_SECTORS_IN_BLOCK = 85
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def __init__(self) -> None:
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self.__serial = None
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@ -381,7 +383,8 @@ class SC64:
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self.__fsd_file.write(data)
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def __dd_track_offset(self, head_track: int) -> int:
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def __dd_track_offset(self, head_track: int, sector_size: int) -> int:
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# shamelessly stolen from MAME implementation, to be rewritten
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head = (head_track & 0x1000) >> 9
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track = head_track & 0xFFF
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dd_zone = 0
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@ -412,43 +415,52 @@ class SC64:
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dd_zone = 0 + head
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tr_off = track
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ddStartOffset = [0x0,0x5F15E0,0xB79D00,0x10801A0,0x1523720,0x1963D80,0x1D414C0,0x20BBCE0,
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0x23196E0,0x28A1E00,0x2DF5DC0,0x3299340,0x36D99A0,0x3AB70E0,0x3E31900,0x4149200]
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ddZoneSecSize = [232,216,208,192,176,160,144,128,
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216,208,192,176,160,144,128,112]
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ddStartOffset = [
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0x0000000,
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0x05F15E0,
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0x0B79D00,
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0x10801A0,
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0x1523720,
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0x1963D80,
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0x1D414C0,
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0x20BBCE0,
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0x23196E0,
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0x28A1E00,
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0x2DF5DC0,
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0x3299340,
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0x36D99A0,
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0x3AB70E0,
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0x3E31900,
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0x4149200
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]
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return (dd_zone, ddStartOffset[dd_zone] + tr_off * ddZoneSecSize[dd_zone] * 85 * 2)
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return ddStartOffset[dd_zone] + tr_off * sector_size * self.__DD_USER_SECTORS_IN_BLOCK * 2
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# def __dd_zone_track_size(self, i) -> int:
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# # ddZoneTrackSize = [158,158,149,149,149,149,149,114,158,158,149,149,149,149,149,114]
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# ddZoneSecSize = [232,216,208,192,176,160,144,128,
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# 216,208,192,176,160,144,128,112]
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# return ddZoneSecSize[i]
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def __dd_calculate_file_offset(self, head_track: int, starting_block: int, sector_size: int) -> int:
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offset = self.__dd_track_offset(head_track, sector_size)
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offset += starting_block * self.__DD_USER_SECTORS_IN_BLOCK * sector_size
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return offset
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def __debug_process_dd_block(self, data: bytes) -> None:
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# scr = int.from_bytes(data[0:4], byteorder='big')
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current_sector = int.from_bytes(data[4:8], byteorder='little')
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head_track = int.from_bytes(data[8:12], byteorder='little')
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sector_num = int.from_bytes(data[12:16], byteorder='little')
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sector_size = int.from_bytes(data[16:20], byteorder='little')
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# sector_size_full = int.from_bytes(data[20:24], byteorder='little')
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# sectors_in_block = int.from_bytes(data[24:28], byteorder='little')
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# print(f"info: {hex(scr)}, {current_sector}, {head_track}, {sector_num}, {sector_size}, {sector_size_full}, {sectors_in_block}")
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transfer_mode = int.from_bytes(data[0:4], byteorder='little')
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head_track = int.from_bytes(data[4:6], byteorder='little')
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starting_block = int.from_bytes(data[6:7], byteorder='little')
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sector_size = int.from_bytes(data[7:8], byteorder='little')
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if (self.__disk_file):
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(zone, track_offset) = self.__dd_track_offset(head_track)
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sector = 0
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sector += track_offset
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sector += (int(sector_num / 90) * 85 * (sector_size + 1)) # self.__dd_zone_track_size(zone)
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sector += ((current_sector) * (sector_size + 1))
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self.__disk_file.seek(sector)
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data_dd = self.__disk_file.read(0x100 * 85)
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if (current_sector == 0x00 or current_sector == 0x5A):
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print(f"getting sect {hex(sector)}, {hex(int.from_bytes(data_dd[0:4], byteorder='big'))}")
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self.__debug_write(self.__DEBUG_ID_DD_BLOCK, data_dd)
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file_offset = self.__dd_calculate_file_offset(head_track, starting_block, sector_size)
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self.__disk_file.seek(file_offset)
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if (transfer_mode):
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block_data = self.__disk_file.read(sector_size * self.__DD_USER_SECTORS_IN_BLOCK)
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self.__debug_write(self.__DEBUG_ID_DD_BLOCK, block_data)
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else:
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self.__debug_write(self.__DEBUG_ID_DD_BLOCK, bytes(0x100))
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block_data = self.__read_long(sector_size * self.__DD_USER_SECTORS_IN_BLOCK)
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self.__disk_file.write(block_data)
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else:
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if (transfer_mode):
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self.__debug_write(self.__DEBUG_ID_DD_BLOCK, bytes(4))
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def debug_loop(self, file: str = None, disk_file: str = None) -> None:
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@ -1,5 +1,4 @@
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#include "dd.h"
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#include "uart.h"
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#include "rtc.h"
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#include "usb.h"
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@ -7,7 +6,10 @@
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#define DD_DRIVE_ID_RETAIL (0x0003)
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#define DD_DRIVE_ID_DEVELOPMENT (0x0004)
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#define DD_VERSION_RETAIL (0x0114)
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#define DD_TRACK_SEEK_TIME_TICKS (10000)
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#define DD_POWER_UP_DELAY_TICKS (320000000UL) // 3.2 s
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#define DD_TRACK_SEEK_TIME_TICKS (10000) // 0.1 ms
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#define DEFAULT_DD_BUFFER_OFFSET (0x03BD8000UL)
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#define USB_DEBUG_ID_DD_BLOCK (0xF5)
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typedef enum {
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DD_CMD_SEEK_READ = 0x01,
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@ -44,6 +46,7 @@ struct process {
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enum state state;
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uint32_t track_seek_time;
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uint32_t next_seek_time;
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bool power_up_delay;
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bool deffered_cmd_ready;
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bool bm_running;
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bool transfer_mode;
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@ -52,37 +55,32 @@ struct process {
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uint8_t current_sector;
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bool is_dev_disk;
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rtc_time_t time;
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io32_t *buffer;
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};
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static struct process p;
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enum {
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READ_PHASE_IDLE,
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READ_PHASE_STARTED,
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READ_PHASE_WAIT,
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} read_phase = READ_PHASE_IDLE;
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io32_t *sdram = (io32_t *) (SDRAM_BASE + (32 * 1024 * 1024));
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static void dd_block_read (void) {
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read_phase = READ_PHASE_STARTED;
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io32_t *dst = sdram;
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io32_t *dst = p.buffer;
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const char *dma = "DMA@";
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const char *cmp = "CMPH";
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if (usb_debug_tx_ready()) {
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*dst++ = *((uint32_t *) (dma));
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*dst++ = 0xF5 | (7 * 4) << 24;
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*dst++ = (uint32_t) DD->SCR;
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*dst++ = (uint32_t) p.current_sector;
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*dst++ = (uint32_t) DD->HEAD_TRACK;
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*dst++ = p.starting_block ? (DD->SECTORS_IN_BLOCK + 1) : 0;
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*dst++ = (uint32_t) DD->SECTOR_SIZE;
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*dst++ = (uint32_t) DD->SECTOR_SIZE_FULL;
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*dst++ = (uint32_t) DD->SECTORS_IN_BLOCK;
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*dst++ = (((2 * 4) << 24) | USB_DEBUG_ID_DD_BLOCK);
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*dst++ = p.transfer_mode;
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*dst++ = (((DD->SECTOR_SIZE + 1) << 24) | (p.starting_block << 16) | DD->HEAD_TRACK);
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*dst++ = *((uint32_t *) (cmp));
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usb_debug_tx_data((uint32_t) (sdram), 10 * 4);
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}
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usb_debug_tx_data((uint32_t) (p.buffer), (5 * 4));
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}
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static bool dd_block_read_done (void) {
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@ -91,7 +89,7 @@ static bool dd_block_read_done (void) {
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if (read_phase == READ_PHASE_STARTED) {
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if (usb_debug_rx_ready(&type, &length)) {
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usb_debug_rx_data((uint32_t) (sdram), length);
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usb_debug_rx_data((uint32_t) (p.buffer), length);
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read_phase = READ_PHASE_WAIT;
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}
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return false;
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@ -107,39 +105,64 @@ static bool dd_block_read_done (void) {
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}
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static void dd_sector_read (void) {
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io32_t *buf = DD->SEC_BUF;
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io32_t *dst = sdram;
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uint8_t sector_size = DD->SECTOR_SIZE + 1;
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io32_t *src = p.buffer;
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io32_t *dst = DD->SECTOR_BUFFER;
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dst += ((sector_size * p.current_sector) / sizeof(io32_t));
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for (int i = 0; i < 0x100; i += 4) {
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*buf++ = *dst++;
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uint8_t sector_size = ((DD->SECTOR_SIZE + 1) / sizeof(io32_t));
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src += (sector_size * p.current_sector);
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for (int i = 0; i < sector_size; i++) {
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*dst++ = *src++;
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}
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}
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static void dd_sector_write (void) {
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io32_t *src = DD->SECTOR_BUFFER;
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io32_t *dst = p.buffer + 4;
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uint8_t sector_size = ((DD->SECTOR_SIZE + 1) / sizeof(io32_t));
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dst += (sector_size * p.current_sector);
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for (int i = 0; i < sector_size; i++) {
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*dst++ = *src++;
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}
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}
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static void dd_block_write (void) {
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uart_print("Requesting block write 0x");
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uart_print_08hex(DD->HEAD_TRACK & DD_HEAD_TRACK_MASK);
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uart_print("\r\n");
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io32_t *dst = p.buffer;
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const char *dma = "DMA@";
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const char *cmp = "CMPH";
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uint32_t block_length = ((DD->SECTOR_SIZE + 1) * 85);
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*dst++ = *((uint32_t *) (dma));
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*dst++ = (((2 * 4) << 24) | USB_DEBUG_ID_DD_BLOCK);
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*dst++ = p.transfer_mode;
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*dst++ = (((DD->SECTOR_SIZE + 1) << 24) | (p.starting_block << 16) | DD->HEAD_TRACK);
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dst += block_length / 4;
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*dst++ = *((uint32_t *) (cmp));
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usb_debug_tx_data((uint32_t) (p.buffer), ((5 * 4) + block_length));
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}
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static bool dd_block_write_done (void) {
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return true;
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}
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static void dd_sector_write (void) {
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return usb_debug_tx_ready();
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}
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void dd_init (void) {
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DD->SCR = 0;
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DD->SCR = DD_SCR_DISK_INSERTED;
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DD->HEAD_TRACK = 0;
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DD->DRIVE_ID = DD_DRIVE_ID_RETAIL;
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p.state = STATE_IDLE;
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p.track_seek_time = DD_TRACK_SEEK_TIME_TICKS;
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p.power_up_delay = true;
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p.deffered_cmd_ready = false;
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p.bm_running = false;
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p.is_dev_disk = false;
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p.buffer = (io32_t *) (SDRAM_BASE + DEFAULT_DD_BUFFER_OFFSET);
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}
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@ -148,7 +171,9 @@ void process_dd (void) {
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if (scr & DD_SCR_HARD_RESET) {
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DD->SCR &= ~(DD_SCR_DISK_CHANGED);
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DD->HEAD_TRACK = 0;
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p.state = STATE_IDLE;
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p.power_up_delay = true;
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p.deffered_cmd_ready = false;
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p.bm_running = false;
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}
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@ -167,7 +192,12 @@ void process_dd (void) {
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}
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} else if ((cmd == DD_CMD_SEEK_READ) || (cmd == DD_CMD_SEEK_WRITE)) {
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int track_distance = abs((DD->HEAD_TRACK & DD_TRACK_MASK) - (data & DD_TRACK_MASK));
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p.next_seek_time = track_distance * p.track_seek_time;
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if (p.power_up_delay) {
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p.power_up_delay = false;
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p.next_seek_time += DD_POWER_UP_DELAY_TICKS;
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} else {
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p.next_seek_time = (track_distance * p.track_seek_time);
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}
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p.deffered_cmd_ready = true;
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DD->HEAD_TRACK &= ~(DD_HEAD_TRACK_INDEX_LOCK);
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DD->SCR |= DD_SCR_SEEK_TIMER_RESET;
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@ -8,9 +8,6 @@
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#include <stdbool.h>
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#define CPU_FREQ (100000000UL)
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typedef volatile uint8_t io8_t;
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typedef volatile uint16_t io16_t;
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typedef volatile uint32_t io32_t;
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@ -209,7 +206,7 @@ typedef volatile struct dd_regs {
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io16_t __padding_3;
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io32_t SEEK_TIMER;
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io32_t __padding_4[58];
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io32_t SEC_BUF[64];
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io32_t SECTOR_BUFFER[64];
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} dd_regs_t;
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#define DD_BASE (0xB0000000UL)
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