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changed mem addressing

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Polprzewodnikowy 2022-07-30 19:39:49 +02:00
parent ea4470eaaa
commit 0b18c55d1c
18 changed files with 161 additions and 96 deletions
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2
fw/project/lcmxo2/sc64.ldf
View File

@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="sc64" device="LCMXO2-7000HC-6TG144C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Timing">
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy">
<Options VerilogStandard="System Verilog" def_top="top" top="top"/>
<Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>

2
fw/project/lcmxo2/sc64.sty
View File

@ -92,7 +92,7 @@
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>

14
fw/rtl/mcu/mcu_top.sv
View File

@ -586,8 +586,6 @@ module mcu_top (
// Register write logic
logic [31:0] reg_buffer;
always_ff @(posedge clk) begin
mem_start <= 1'b0;
mem_stop <= 1'b0;
@ -644,6 +642,7 @@ module mcu_top (
n64_scb.bootloader_enabled <= 1'b1;
flash_scb.erase_pending <= 1'b0;
dd_bm_ack <= 1'b0;
n64_scb.rtc_wdata_valid <= 1'b0;
end else if (reg_write) begin
case (address)
REG_STATUS: begin end
@ -731,17 +730,18 @@ module mcu_top (
end
REG_RTC_TIME_0: begin
reg_buffer <= reg_wdata;
n64_scb.rtc_wdata_valid <= 1'b0;
n64_scb.rtc_wdata[28:26] <= reg_wdata[26:24];
n64_scb.rtc_wdata[19:14] <= reg_wdata[21:16];
n64_scb.rtc_wdata[13:7] <= reg_wdata[14:8];
n64_scb.rtc_wdata[6:0] <= reg_wdata[6:0];
end
REG_RTC_TIME_1: begin
n64_scb.rtc_wdata_valid <= 1'b1;
n64_scb.rtc_wdata[41:34] <= reg_wdata[23:16];
n64_scb.rtc_wdata[33:29] <= reg_wdata[12:8];
n64_scb.rtc_wdata[25:20] <= reg_wdata[5:0];
n64_scb.rtc_wdata[28:26] <= reg_buffer[26:24];
n64_scb.rtc_wdata[19:14] <= reg_buffer[21:16];
n64_scb.rtc_wdata[13:7] <= reg_buffer[14:8];
n64_scb.rtc_wdata[6:0] <= reg_buffer[6:0];
end
REG_SD_SCR: begin

16
fw/rtl/memory/memory_arbiter.sv
View File

@ -39,15 +39,15 @@ module memory_arbiter (
assign usb_dma_sdram_request = usb_dma_bus.request && !usb_dma_bus.address[26];
assign sd_dma_sdram_request = sd_dma_bus.request && !sd_dma_bus.address[26];
assign n64_flash_request = n64_bus.request && (n64_bus.address[26:25] == 2'b10);
assign cfg_flash_request = cfg_bus.request && (cfg_bus.address[26:25] == 2'b10);
assign usb_dma_flash_request = usb_dma_bus.request && (usb_dma_bus.address[26:25] == 2'b10);
assign sd_dma_flash_request = sd_dma_bus.request && (sd_dma_bus.address[26:25] == 2'b10);
assign n64_flash_request = n64_bus.request && (n64_bus.address[26:24] == 3'b100);
assign cfg_flash_request = cfg_bus.request && (cfg_bus.address[26:24] == 3'b100);
assign usb_dma_flash_request = usb_dma_bus.request && (usb_dma_bus.address[26:24] == 3'b100);
assign sd_dma_flash_request = sd_dma_bus.request && (sd_dma_bus.address[26:24] == 3'b100);
assign n64_bram_request = n64_bus.request && (n64_bus.address[26:25] == 2'b11);
assign cfg_bram_request = cfg_bus.request && (cfg_bus.address[26:25] == 2'b11);
assign usb_dma_bram_request = usb_dma_bus.request && (usb_dma_bus.address[26:25] == 2'b11);
assign sd_dma_bram_request = sd_dma_bus.request && (sd_dma_bus.address[26:25] == 2'b11);
assign n64_bram_request = n64_bus.request && (n64_bus.address[26:24] >= 3'b101);
assign cfg_bram_request = cfg_bus.request && (cfg_bus.address[26:24] >= 3'b101);
assign usb_dma_bram_request = usb_dma_bus.request && (usb_dma_bus.address[26:24] >= 3'b101);
assign sd_dma_bram_request = sd_dma_bus.request && (sd_dma_bus.address[26:24] >= 3'b101);
e_source_request sdram_source_request;

71
fw/rtl/memory/memory_bram.sv
View File

@ -28,14 +28,20 @@ module memory_bram (
logic buffer_selected;
logic eeprom_selected;
logic flashram_selected;
logic dd_selected;
logic flashram_selected;
always_comb begin
buffer_selected = mem_bus.address[14:13] == 2'b00;
eeprom_selected = mem_bus.address[14:13] == 2'b01;
flashram_selected = mem_bus.address[14:13] == 2'b10;
dd_selected = mem_bus.address[14:13] == 2'b11;
buffer_selected = 1'b0;
eeprom_selected = 1'b0;
dd_selected = 1'b0;
flashram_selected = 1'b0;
if (mem_bus.address[25:24] == 2'b01 && mem_bus.address[23:14] == 10'd0) begin
buffer_selected = mem_bus.address[13] == 1'b0;
eeprom_selected = mem_bus.address[13:11] == 3'b100;
dd_selected = mem_bus.address[13:8] == 6'b101000;
flashram_selected = mem_bus.address[13:7] == 7'b1010010;
end
end
@ -46,7 +52,8 @@ module memory_bram (
always_ff @(posedge clk) begin
if (write && buffer_selected) begin
buffer_bram[mem_bus.address[12:1]] <= mem_bus.wdata;
if (mem_bus.wmask[1]) buffer_bram[mem_bus.address[12:1]][15:8] <= mem_bus.wdata[15:8];
if (mem_bus.wmask[0]) buffer_bram[mem_bus.address[12:1]][7:0] <= mem_bus.wdata[7:0];
end
end
@ -66,7 +73,7 @@ module memory_bram (
logic [15:0] eeprom_bram_rdata;
always_ff @(posedge clk) begin
if (write && eeprom_selected) begin
if (write && mem_bus.wmask[1] && eeprom_selected) begin
eeprom_bram_high[mem_bus.address[10:1]] <= mem_bus.wdata[15:8];
end
if (n64_scb.eeprom_write && !n64_scb.eeprom_address[0]) begin
@ -75,7 +82,7 @@ module memory_bram (
end
always_ff @(posedge clk) begin
if (write && eeprom_selected) begin
if (write && mem_bus.wmask[0] && eeprom_selected) begin
eeprom_bram_low[mem_bus.address[10:1]] <= mem_bus.wdata[7:0];
end
if (n64_scb.eeprom_write && n64_scb.eeprom_address[0]) begin
@ -105,6 +112,29 @@ module memory_bram (
end
// DD memory
logic [15:0] dd_bram [0:127];
logic [15:0] dd_bram_rdata;
always_ff @(posedge clk) begin
if (write && dd_selected) begin
dd_bram[mem_bus.address[7:1]] <= mem_bus.wdata;
end
if (n64_scb.dd_write) begin
dd_bram[n64_scb.dd_address] <= n64_scb.dd_wdata;
end
end
always_ff @(posedge clk) begin
dd_bram_rdata <= dd_bram[mem_bus.address[7:1]];
end
always_ff @(posedge clk) begin
n64_scb.dd_rdata <= dd_bram[n64_scb.dd_address];
end
// FlashRAM memory
logic [15:0] flashram_bram [0:63];
@ -121,37 +151,14 @@ module memory_bram (
end
// DD memory
logic [15:0] dd_bram [0:1023];
logic [15:0] dd_bram_rdata;
always_ff @(posedge clk) begin
if (write && dd_selected) begin
dd_bram[mem_bus.address[9:1]] <= mem_bus.wdata;
end
if (n64_scb.dd_write) begin
dd_bram[n64_scb.dd_address] <= n64_scb.dd_wdata;
end
end
always_ff @(posedge clk) begin
dd_bram_rdata <= dd_bram[mem_bus.address[9:1]];
end
always_ff @(posedge clk) begin
n64_scb.dd_rdata <= dd_bram[n64_scb.dd_address];
end
// Output data mux
always_ff @(posedge clk) begin
mem_bus.rdata <= 16'd0;
if (buffer_selected) mem_bus.rdata <= buffer_bram_rdata;
if (eeprom_selected) mem_bus.rdata <= eeprom_bram_rdata;
if (flashram_selected) mem_bus.rdata <= flashram_bram_rdata;
if (dd_selected) mem_bus.rdata <= dd_bram_rdata;
if (flashram_selected) mem_bus.rdata <= flashram_bram_rdata;
end
endmodule

1
fw/rtl/n64/n64_cfg.sv
View File

@ -40,6 +40,7 @@ module n64_cfg (
always_ff @(posedge clk) begin
if (reset) begin
n64_scb.cfg_pending <= 1'b0;
n64_scb.cfg_cmd <= 8'h00;
irq <= 1'b0;
end else begin
if (n64_scb.cfg_done) begin

2
fw/rtl/n64/n64_dd.sv
View File

@ -279,7 +279,7 @@ module n64_dd (
always_comb begin
n64_scb.dd_write = reg_bus.write && reg_bus.address[10:8] == MEM_SECTOR_BUFFER[10:8];
n64_scb.dd_address = {2'b00, reg_bus.address[7:1]};
n64_scb.dd_address = reg_bus.address[7:1];
n64_scb.dd_wdata = reg_bus.wdata;
end

2
fw/rtl/n64/n64_pi.sv
View File

@ -129,7 +129,7 @@ module n64_pi (
const bit [31:0] FLASH_OFFSET = 32'h0400_0000;
const bit [31:0] BOOTLOADER_OFFSET = 32'h04E0_0000;
const bit [31:0] SHADOW_OFFSET = 32'h04FE_0000;
const bit [31:0] BUFFER_OFFSET = 32'h0600_0000;
const bit [31:0] BUFFER_OFFSET = 32'h0500_0000;
logic [31:0] mem_offset;

5
fw/rtl/n64/n64_scb.sv
View File

@ -15,7 +15,7 @@ interface n64_scb ();
logic eeprom_16k_mode;
logic dd_write;
logic [8:0] dd_address;
logic [6:0] dd_address;
logic [15:0] dd_rdata;
logic [15:0] dd_wdata;
@ -36,6 +36,7 @@ interface n64_scb ();
logic rtc_pending;
logic rtc_done;
logic rtc_wdata_valid;
logic [41:0] rtc_rdata;
logic [41:0] rtc_wdata;
@ -71,6 +72,7 @@ interface n64_scb ();
input rtc_pending,
output rtc_done,
output rtc_wdata_valid,
input rtc_rdata,
output rtc_wdata,
@ -125,6 +127,7 @@ interface n64_scb ();
output rtc_pending,
input rtc_done,
input rtc_wdata_valid,
output rtc_rdata,
input rtc_wdata
);

2
fw/rtl/n64/n64_si.sv
View File

@ -364,7 +364,7 @@ module n64_si (
n64_scb.rtc_pending <= 1'b0;
end
if (!rtc_stopped && !n64_scb.rtc_pending && (tx_state != TX_STATE_DATA)) begin
if (!rtc_stopped && !n64_scb.rtc_pending && n64_scb.rtc_wdata_valid && (tx_state != TX_STATE_DATA)) begin
{
rtc_time_year,
rtc_time_month,

5
sw/bootloader/src/io.h
View File

@ -228,11 +228,8 @@ typedef struct {
typedef struct {
io8_t BUFFER[8192];
io8_t EEPROM[2048];
io8_t __unused_1[8192 - 2048];
io8_t DD_SECTOR[256];
io8_t FLASHRAM[128];
io8_t __unused_2[8192 - 128];
io8_t DD_SECTOR[2048];
io8_t __unused_3[8192 - 2048];
} sc64_buffers_t;
#define SC64_BUFFERS_BASE (0x1FFE0000UL)

9
sw/bootloader/src/sc64.c
View File

@ -96,7 +96,7 @@ bool sc64_usb_write_ready (void) {
void sc64_usb_write (uint32_t *address, uint32_t length) {
while (!sc64_usb_write_ready());
uint32_t args[2] = { (uint32_t) (address), length };
sc64_execute_cmd(SC64_CMD_USB_WRITE, args, NULL);
return sc64_execute_cmd(SC64_CMD_USB_WRITE, args, NULL);
}
bool sc64_usb_read_ready (uint8_t *type, uint32_t *length) {
@ -111,11 +111,14 @@ bool sc64_usb_read_ready (uint8_t *type, uint32_t *length) {
return result[1] > 0;
}
void sc64_usb_read (uint32_t *address, uint32_t length) {
bool sc64_usb_read (uint32_t *address, uint32_t length) {
uint32_t args[2] = { (uint32_t) (address), length };
uint32_t result[2];
sc64_execute_cmd(SC64_CMD_USB_READ, args, NULL);
if (sc64_execute_cmd(SC64_CMD_USB_READ, args, NULL)) {
return true;
}
do {
sc64_execute_cmd(SC64_CMD_USB_READ_STATUS, NULL, result);
} while(result[0] & (1 << 24));
return false;
}

4
sw/bootloader/src/sc64.h
View File

@ -82,9 +82,9 @@ void sc64_get_boot_info (sc64_boot_info_t *info);
void sc64_get_time (rtc_time_t *t);
void sc64_set_time (rtc_time_t *t);
bool sc64_write_usb_ready (void);
void sc64_write_usb (uint32_t *address, uint32_t length);
bool sc64_write_usb (uint32_t *address, uint32_t length);
bool sc64_usb_read_ready (uint8_t *type, uint32_t *length);
void sc64_usb_read (uint32_t *address, uint32_t length);
bool sc64_usb_read (uint32_t *address, uint32_t length);
#endif

104
sw/controller/src/cfg.c
View File

@ -58,6 +58,14 @@ typedef enum {
TV_TYPE_UNKNOWN = 3
} tv_type_t;
typedef enum {
CFG_ERROR_OK = 0,
CFG_ERROR_BAD_ADDRESS = 1,
CFG_ERROR_BAD_CONFIG_ID = 2,
CFG_ERROR_TIMEOUT = 3,
CFG_ERROR_UNKNOWN_CMD = -1,
} cfg_error_t;
struct process {
boot_mode_t boot_mode;
@ -75,7 +83,31 @@ static void cfg_set_usb_output_ready (void) {
p.usb_output_ready = true;
}
static void change_scr_bits (uint32_t mask, bool value) {
static bool cfg_translate_address (uint32_t *args) {
uint32_t address = args[0];
uint32_t length = args[1];
if (address >= 0x10000000 && address < 0x14000000) {
if ((address + length) <= 0x14000000) {
args[0] = address - 0x10000000 + 0x00000000;
return false;
}
}
if (address >= 0x1FFE0000 && address < 0x1FFE2000) {
if ((address + length) <= 0x1FFE2000) {
args[0] = address - 0x1FFE0000 + 0x05000000;
return false;
}
}
return true;
}
static void cfg_set_error (cfg_error_t error) {
fpga_reg_set(REG_CFG_DATA_0, error);
fpga_reg_set(REG_CFG_DATA_1, 0);
fpga_reg_set(REG_CFG_CMD, CFG_CMD_ERROR | CFG_CMD_DONE);
}
static void cfg_change_scr_bits (uint32_t mask, bool value) {
if (value) {
fpga_reg_set(REG_CFG_SCR, fpga_reg_get(REG_CFG_SCR) | mask);
} else {
@ -83,7 +115,7 @@ static void change_scr_bits (uint32_t mask, bool value) {
}
}
static void set_save_type (save_type_t save_type) {
static void cfg_set_save_type (save_type_t save_type) {
uint32_t save_reset_mask = (
CFG_SCR_EEPROM_16K |
CFG_SCR_EEPROM_ENABLED |
@ -92,25 +124,25 @@ static void set_save_type (save_type_t save_type) {
CFG_SCR_SRAM_ENABLED
);
change_scr_bits(save_reset_mask, false);
cfg_change_scr_bits(save_reset_mask, false);
switch (save_type) {
case SAVE_TYPE_NONE:
break;
case SAVE_TYPE_EEPROM_4K:
change_scr_bits(CFG_SCR_EEPROM_ENABLED, true);
cfg_change_scr_bits(CFG_SCR_EEPROM_ENABLED, true);
break;
case SAVE_TYPE_EEPROM_16K:
change_scr_bits(CFG_SCR_EEPROM_16K | CFG_SCR_EEPROM_ENABLED, true);
cfg_change_scr_bits(CFG_SCR_EEPROM_16K | CFG_SCR_EEPROM_ENABLED, true);
break;
case SAVE_TYPE_SRAM:
change_scr_bits(CFG_SCR_SRAM_ENABLED, true);
cfg_change_scr_bits(CFG_SCR_SRAM_ENABLED, true);
break;
case SAVE_TYPE_FLASHRAM:
change_scr_bits(CFG_SCR_FLASHRAM_ENABLED, true);
cfg_change_scr_bits(CFG_SCR_FLASHRAM_ENABLED, true);
break;
case SAVE_TYPE_SRAM_BANKED:
change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_ENABLED, true);
cfg_change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_ENABLED, true);
break;
default:
save_type = SAVE_TYPE_NONE;
@ -125,7 +157,7 @@ uint32_t cfg_get_version (void) {
return fpga_reg_get(REG_CFG_VERSION);
}
void cfg_query (uint32_t *args) {
bool cfg_query (uint32_t *args) {
uint32_t scr = fpga_reg_get(REG_CFG_SCR);
switch (args[0]) {
@ -171,31 +203,35 @@ void cfg_query (uint32_t *args) {
case CFG_ID_DD_DISK_STATE:
args[1] = dd_get_disk_state();
break;
default:
return true;
}
return false;
}
void cfg_update (uint32_t *args) {
bool cfg_update (uint32_t *args) {
switch (args[0]) {
case CFG_ID_BOOTLOADER_SWITCH:
change_scr_bits(CFG_SCR_BOOTLOADER_ENABLED, args[1]);
cfg_change_scr_bits(CFG_SCR_BOOTLOADER_ENABLED, args[1]);
break;
case CFG_ID_ROM_WRITE_ENABLE:
change_scr_bits(CFG_SCR_ROM_WRITE_ENABLED, args[1]);
cfg_change_scr_bits(CFG_SCR_ROM_WRITE_ENABLED, args[1]);
break;
case CFG_ID_ROM_SHADOW_ENABLE:
change_scr_bits(CFG_SCR_ROM_SHADOW_ENABLED, args[1]);
cfg_change_scr_bits(CFG_SCR_ROM_SHADOW_ENABLED, args[1]);
break;
case CFG_ID_DD_MODE:
if (args[1] == DD_MODE_DISABLED) {
change_scr_bits(CFG_SCR_DD_ENABLED | CFG_SCR_DDIPL_ENABLED, false);
cfg_change_scr_bits(CFG_SCR_DD_ENABLED | CFG_SCR_DDIPL_ENABLED, false);
} else if (args[1] == DD_MODE_REGS) {
change_scr_bits(CFG_SCR_DD_ENABLED, true);
change_scr_bits(CFG_SCR_DDIPL_ENABLED, false);
cfg_change_scr_bits(CFG_SCR_DD_ENABLED, true);
cfg_change_scr_bits(CFG_SCR_DDIPL_ENABLED, false);
} else if (args[1] == DD_MODE_IPL) {
change_scr_bits(CFG_SCR_DD_ENABLED, false);
change_scr_bits(CFG_SCR_DDIPL_ENABLED, true);
cfg_change_scr_bits(CFG_SCR_DD_ENABLED, false);
cfg_change_scr_bits(CFG_SCR_DDIPL_ENABLED, true);
} else {
change_scr_bits(CFG_SCR_DD_ENABLED | CFG_SCR_DDIPL_ENABLED, true);
cfg_change_scr_bits(CFG_SCR_DD_ENABLED | CFG_SCR_DDIPL_ENABLED, true);
}
break;
case CFG_ID_ISV_ENABLE:
@ -203,10 +239,10 @@ void cfg_update (uint32_t *args) {
break;
case CFG_ID_BOOT_MODE:
p.boot_mode = args[1];
change_scr_bits(CFG_SCR_BOOTLOADER_SKIP, (args[1] == BOOT_MODE_DIRECT));
cfg_change_scr_bits(CFG_SCR_BOOTLOADER_SKIP, (args[1] == BOOT_MODE_DIRECT));
break;
case CFG_ID_SAVE_TYPE:
set_save_type((save_type_t) (args[1]));
cfg_set_save_type((save_type_t) (args[1]));
break;
case CFG_ID_CIC_SEED:
p.cic_seed = (cic_seed_t) (args[1] & 0xFFFF);
@ -223,7 +259,11 @@ void cfg_update (uint32_t *args) {
case CFG_ID_DD_DISK_STATE:
dd_set_disk_state(args[1]);
break;
default:
return true;
}
return false;
}
void cfg_get_time (uint32_t *args) {
@ -247,7 +287,7 @@ void cfg_set_time (uint32_t *args) {
void cfg_init (void) {
fpga_reg_set(REG_CFG_SCR, 0);
set_save_type(SAVE_TYPE_NONE);
cfg_set_save_type(SAVE_TYPE_NONE);
p.cic_seed = CIC_SEED_UNKNOWN;
p.tv_type = TV_TYPE_UNKNOWN;
@ -270,11 +310,17 @@ void cfg_process (void) {
break;
case 'c':
cfg_query(args);
if (cfg_query(args)) {
cfg_set_error(CFG_ERROR_BAD_CONFIG_ID);
return;
}
break;
case 'C':
cfg_update(args);
if (cfg_update(args)) {
cfg_set_error(CFG_ERROR_BAD_CONFIG_ID);
return;
}
break;
case 't':
@ -286,12 +332,20 @@ void cfg_process (void) {
break;
case 'm':
if (cfg_translate_address(args)) {
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
return;
}
if (!usb_prepare_read(args)) {
return;
}
break;
case 'M':
if (cfg_translate_address(args)) {
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
return;
}
usb_create_packet(&packet_info, PACKET_CMD_USB_OUTPUT);
packet_info.dma_length = args[1];
packet_info.dma_address = args[0];
@ -312,7 +366,7 @@ void cfg_process (void) {
break;
default:
fpga_reg_set(REG_CFG_CMD, CFG_CMD_ERROR | CFG_CMD_DONE);
cfg_set_error(CFG_ERROR_UNKNOWN_CMD);
return;
}

4
sw/controller/src/cfg.h
View File

@ -6,8 +6,8 @@
uint32_t cfg_get_version (void);
void cfg_query (uint32_t *args);
void cfg_update (uint32_t *args);
bool cfg_query (uint32_t *args);
bool cfg_update (uint32_t *args);
void cfg_get_time (uint32_t *args);
void cfg_set_time (uint32_t *args);
void cfg_init (void);

2
sw/controller/src/dd.c
View File

@ -11,7 +11,7 @@
#define DD_SECTOR_MAX_SIZE (232)
#define DD_BLOCK_DATA_SECTORS_NUM (85)
#define DD_BLOCK_BUFFER_ADDRESS (0x03BC0000UL - (DD_SECTOR_MAX_SIZE * DD_BLOCK_DATA_SECTORS_NUM))
#define DD_SECTOR_BUFFER_ADDRESS (0x06006000UL)
#define DD_SECTOR_BUFFER_ADDRESS (0x05002800UL)
#define DD_DRIVE_ID_RETAIL (0x0003)
#define DD_DRIVE_ID_DEVELOPMENT (0x0004)

8
sw/controller/src/flashram.c
View File

@ -6,8 +6,8 @@
#define FLASHRAM_SIZE (128 * 1024)
#define FLASHRAM_SECTOR_SIZE (16 * 1024)
#define FLASHRAM_PAGE_SIZE (128)
#define FLASHRAM_OFFSET (0x03FE0000UL)
#define FLASHRAM_BUFFER_OFFSET (0x06004000UL)
#define FLASHRAM_ADDRESS (0x03FE0000UL)
#define FLASHRAM_BUFFER_ADDRESS (0x05002900UL)
enum operation {
@ -43,7 +43,7 @@ void flashram_process (void) {
uint32_t scr = fpga_reg_get(REG_FLASHRAM_SCR);
enum operation op = flashram_operation_type(scr);
uint8_t buffer[FLASHRAM_PAGE_SIZE];
uint32_t address = FLASHRAM_OFFSET;
uint32_t address = FLASHRAM_ADDRESS;
uint32_t erase_size = (op == OP_ERASE_SECTOR) ? FLASHRAM_SECTOR_SIZE : FLASHRAM_SIZE;
uint32_t sector = (op != OP_ERASE_ALL) ? ((scr & FLASHRAM_SCR_PAGE_MASK) >> FLASHRAM_SCR_PAGE_BIT) : 0;
address += sector * FLASHRAM_PAGE_SIZE;
@ -61,7 +61,7 @@ void flashram_process (void) {
break;
case OP_WRITE_PAGE:
fpga_mem_copy(FLASHRAM_BUFFER_OFFSET, address, FLASHRAM_PAGE_SIZE);
fpga_mem_copy(FLASHRAM_BUFFER_ADDRESS, address, FLASHRAM_PAGE_SIZE);
fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE);
break;

4
sw/controller/src/usb.c
View File

@ -169,7 +169,7 @@ static void usb_rx_process (void) {
break;
case 'c':
cfg_query(p.rx_args);
p.response_error = cfg_query(p.rx_args);
p.rx_state = RX_STATE_IDLE;
p.response_pending = true;
p.response_info.data_length = 4;
@ -177,7 +177,7 @@ static void usb_rx_process (void) {
break;
case 'C':
cfg_update(p.rx_args);
p.response_error = cfg_update(p.rx_args);
p.rx_state = RX_STATE_IDLE;
p.response_pending = true;
break;