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[SC64][FW] Added placeholder test point outputs in the FPGA project

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This commit is contained in:
Mateusz Faderewski 2024-05-03 17:55:40 +02:00
parent 8a49e954ce
commit 0e868b5ad5
2 changed files with 9 additions and 1 deletions
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3
fw/project/lcmxo2/sc64.lpf
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@ -194,6 +194,9 @@ LOCATE COMP "sdram_dqm[0]" SITE "97" ;
LOCATE COMP "sdram_dqm[1]" SITE "73" ; LOCATE COMP "sdram_dqm[1]" SITE "73" ;
LOCATE COMP "sdram_ras" SITE "94" ; LOCATE COMP "sdram_ras" SITE "94" ;
LOCATE COMP "sdram_we" SITE "96" ; LOCATE COMP "sdram_we" SITE "96" ;
LOCATE COMP "test_point[0]" SITE "23" ;
LOCATE COMP "test_point[1]" SITE "24" ;
LOCATE COMP "test_point[2]" SITE "25" ;
LOCATE COMP "usb_clk" SITE "12" ; LOCATE COMP "usb_clk" SITE "12" ;
LOCATE COMP "usb_cs" SITE "11" ; LOCATE COMP "usb_cs" SITE "11" ;
LOCATE COMP "usb_miosi[0]" SITE "22" ; LOCATE COMP "usb_miosi[0]" SITE "22" ;

7
fw/rtl/top.sv
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@ -51,7 +51,10 @@ module top (
output mcu_miso, output mcu_miso,
// Unused I/O // Unused I/O
output n64_video_sync
output n64_video_sync,
output [2:0] test_point
); );
logic clk; logic clk;
@ -278,4 +281,6 @@ module top (
assign n64_video_sync = 1'bZ; assign n64_video_sync = 1'bZ;
assign test_point = 3'b000;
endmodule endmodule