From 11372e09108039b1e49150c3fc6053c339423328 Mon Sep 17 00:00:00 2001 From: Mateusz Faderewski Date: Sun, 7 Jul 2024 18:06:05 +0200 Subject: [PATCH] revert1 --- fw/rtl/memory/memory_dma.sv | 222 ------------------------------------ 1 file changed, 222 deletions(-) diff --git a/fw/rtl/memory/memory_dma.sv b/fw/rtl/memory/memory_dma.sv index 6c17173..61915f3 100644 --- a/fw/rtl/memory/memory_dma.sv +++ b/fw/rtl/memory/memory_dma.sv @@ -8,228 +8,6 @@ module memory_dma ( mem_bus.controller mem_bus ); - // logic stop_requested; - // logic dma_done; - - // always_ff @(posedge clk) begin - // if (reset) begin - // dma_scb.busy <= 1'b0; - // stop_requested <= 1'b0; - // end else begin - // if (dma_scb.start) begin - // dma_scb.busy <= 1'b1; - // end - - // if (dma_scb.busy && dma_scb.stop) begin - // stop_requested <= 1'b1; - // end - - // if (dma_done) begin - // dma_scb.busy <= 1'b0; - // stop_requested <= 1'b0; - // end - // end - // end - - // logic unaligned_start; - // logic unaligned_end; - - // always_ff @(posedge clk) begin - // if (dma_scb.start) begin - // unaligned_start <= dma_scb.starting_address[0]; - // // unaligned_end <= ; - // end - // end - - // logic [26:0] bytes_remaining; - - // always_ff @(posedge clk) begin - // bytes_remaining <= bytes_remaining - 27'd1; - // if (dma_scb.start) begin - // bytes_remaining <= dma_scb.transfer_length; - // end - // end - - - - - // logic mem_transfer_request; - // logic mem_wdata_buffer_ready; - // logic mem_rdata_buffer_ready; - // logic [15:0] mem_wdata_buffer; - // logic [15:0] mem_rdata_buffer; - // logic [1:0] mem_wdata_buffer_valid_bytes; - // logic mem_rdata_buffer_valid; - - // always_comb begin - // mem_transfer_request = ( - // !mem_bus.request || mem_bus.ack - // ) && ( - // mem_wdata_buffer_ready || mem_rdata_buffer_ready - // ); - // end - - // always_ff @(posedge clk) begin - // if (dma_scb.start) begin - // mem_bus.write <= dma_scb.direction; - // mem_bus.address <= {dma_scb.starting_address[26:1], 1'b0}; - // mem_rdata_buffer_valid <= 1'b0; - // end - - // if (mem_bus.ack) begin - // mem_bus.request <= 1'b0; - // mem_bus.address <= mem_bus.address + 27'd2; - // mem_rdata_buffer <= mem_bus.rdata; - // mem_rdata_buffer_valid <= 1'b1; - // end - - // if (reset) begin - // mem_bus.request <= 1'b0; - // end else if (mem_transfer_request) begin - // mem_bus.request <= 1'b1; - // mem_bus.wmask <= mem_wdata_buffer_valid_bytes; - // end - - // if (!mem_bus.request || mem_bus.ack) begin - // if (mem_wdata_buffer_ready) begin - // if (dma_scb.byte_swap) begin - // mem_bus.wdata[15:8] <= mem_wdata_buffer[7:0]; - // mem_bus.wdata[7:0] <= mem_wdata_buffer[15:8]; - // end else begin - // mem_bus.wdata <= mem_wdata_buffer; - // end - // end - // end - // end - - - - - - - - - // // always_ff @(posedge clk) begin - // // mem_wdata_buffer_ready <= dma_scb.busy; - // // mem_wdata_buffer_valid_bytes <= 2'b10; - // // end - - - - - - - // logic [1:0] rx_fifo_bytes_available; - // logic [1:0] tx_fifo_bytes_available; - - // always_comb begin - // rx_fifo_bytes_available = 2'd2; - // if (fifo_bus.rx_almost_empty) begin - // rx_fifo_bytes_available = 2'd1; - // end - // if (fifo_bus.rx_empty) begin - // rx_fifo_bytes_available = 2'd0; - // end - - // tx_fifo_bytes_available = 2'd2; - // if (fifo_bus.tx_almost_full) begin - // tx_fifo_bytes_available = 2'd1; - // end - // if (fifo_bus.tx_full) begin - // tx_fifo_bytes_available = 2'd0; - // end - // end - - // always_ff @(posedge clk) begin - // if (dma_scb.busy) begin - // if (!dma_scb.direction) begin - // // RX FIFO handling - // end - // end - // end - - // always_ff @(posedge clk) begin - // if (dma_scb.busy) begin - // if (dma_scb.direction) begin - // // TX FIFO handling - // end - // end - // end - - - -//XDDDAWDWD - - - - - - - - - - - - - - - // always_ff @(posedge clk) begin - // dma_done <= 1'b0; - - // if (dma_scb.busy && bytes_remaining == 27'd0) begin - // // dma_done <= 1'b1; - // end - // end - - - - - - // typedef enum bit [1:0] { - - // } e_rx_fifo_state; - - // typedef enum bit [1:0] { - - // } e_tx_fifo_state; - - // typedef enum bit [1:0] { - // MEM_BUS_IDLE = 2'b00, - // MEM_BUS_WAIT = 2'b01, - // MEM_BUS_TRANSFERRING = 2'b10, - // } e_mem_bus_state; - - // e_mem_bus_state mem_bus_state; - // e_mem_bus_state next_mem_bus_state; - - // always_ff @(posedge clk) begin - // mem_bus_state <= next_mem_bus_state; - // if (reset) begin - // mem_bus_state <= MEM_BUS_IDLE; - // end - // end - - // always_comb begin - // next_mem_bus_state = mem_bus_state; - - // case (mem_bus_state) - // MEM_BUS_IDLE: begin - // if (dma_scb.start) begin - // next_mem_bus_state = MEM_BUS_WAIT; - // end - // end - - // MEM_BUS_WAIT: begin - // i - // end - - // MEM_BUS_TRANSFERRING: begin - - // end - // endcase - // end - - // DMA start/stop control logic dma_start;