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cleanup

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Polprzewodnikowy 2021-09-25 12:23:10 +02:00
parent 281137f9f1
commit 1e98c669bd
11 changed files with 57 additions and 49 deletions
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4
fw/SummerCart64.qsf
View File

@ -19,7 +19,7 @@
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 00:28:50 September 07, 2021
# Date created = 21:23:28 September 18, 2021
#
# -------------------------------------------------------------------------- #
#
@ -191,7 +191,7 @@ set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
# Compiler Assignments
# ====================
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name OPTIMIZATION_MODE BALANCED
# Analysis & Synthesis Assignments
# ================================

17
sw/riscv/Makefile
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@ -3,7 +3,7 @@ CC = $(TOOLCHAIN)gcc
OBJCOPY = $(TOOLCHAIN)objcopy
SIZE = $(TOOLCHAIN)size
FLAGS = -mabi=ilp32 -march=rv32i
FLAGS = -mabi=ilp32 -march=rv32i $(USER_FLAGS)
CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP
LDFLAGS = -nostartfiles -Wl,--gc-sections
@ -17,7 +17,9 @@ DEPS = $(OBJS:.o=.d)
VPATH = $(SRC_DIR)
all: make_output_dir $(BOOTLOADER_DIR)/cpu_bootloader.sv $(BUILD_DIR)/controller.rom
$(@info $(shell mkdir -p ./$(BUILD_DIR) &> /dev/null))
all: $(BOOTLOADER_DIR)/cpu_bootloader.sv $(BUILD_DIR)/controller.rom
$(BUILD_DIR)/%.o: %.c
$(CC) $(FLAGS) $(CFLAGS) -c $< -o $@
@ -32,21 +34,18 @@ $(BUILD_DIR)/controller.rom: $(BUILD_DIR)/uc.elf
@echo 'Size of controller modules:'
@$(SIZE) -B -t --common $(OBJS)
@echo 'Size of controller:'
@$(SIZE) -B build/controller.elf
@$(SIZE) -B $(BUILD_DIR)/controller.elf
$(BOOTLOADER_DIR)/cpu_bootloader.sv: $(BUILD_DIR)/uc.elf
$(OBJCOPY) -j .bootloader $(BUILD_DIR)/uc.elf $(BUILD_DIR)/bootloader.elf
$(OBJCOPY) -O binary $(BUILD_DIR)/bootloader.elf $(BUILD_DIR)/bootloader.bin
python3 tools/bin2sv.py tools/cpu_bootloader_template.sv $@ < $(BUILD_DIR)/bootloader.bin
@echo 'Size of bootloader:'
@$(SIZE) -B build/bootloader.elf
make_output_dir:
@$(shell mkdir ./$(BUILD_DIR) 2> /dev/null)
@$(SIZE) -B $(BUILD_DIR)/bootloader.elf
clean:
rm -rf build
rm -rf ./$(BUILD_DIR)/*
.PHONY: all make_output_dir clean
.PHONY: all clean
-include $(DEPS)

3
sw/riscv/src/cfg.c
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@ -89,6 +89,7 @@ static void set_save_type (enum save_type save_type) {
change_scr_bits(CFG_SCR_FLASHRAM_EN, true);
break;
default:
save_type = SAVE_TYPE_NONE;
break;
}
@ -171,8 +172,10 @@ void cfg_query (uint32_t *args) {
void cfg_init (void) {
set_save_type(SAVE_TYPE_NONE);
CFG->DD_OFFSET = DEFAULT_DD_OFFSET;
CFG->SCR = CFG_SCR_CPU_READY | CFG_SCR_SDRAM_SWITCH;
p.cic_seed = 0xFFFF;
p.tv_type = 0x03;
}

19
sw/riscv/src/joybus.c
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@ -31,15 +31,15 @@
static void joybus_rx (uint8_t *data) {
uint32_t rx_length = (JOYBUS->SCR & JOYBUS_SCR_RX_LENGTH_MASK) >> JOYBUS_SCR_RX_LENGTH_BIT;
size_t rx_length = (JOYBUS->SCR & JOYBUS_SCR_RX_LENGTH_MASK) >> JOYBUS_SCR_RX_LENGTH_BIT;
for (size_t i = 0; i < rx_length; i++) {
data[i] = ((uint8_t *) JOYBUS->DATA)[(10 - rx_length) + i];
data[i] = ((uint8_t *) (JOYBUS->DATA))[(10 - rx_length) + i];
}
}
static void joybus_tx (uint8_t *data, size_t length) {
for (size_t i = 0; i < ((length + 3) / 4); i++) {
JOYBUS->DATA[i] = ((uint32_t *) data)[i];
JOYBUS->DATA[i] = ((uint32_t *) (data))[i];
}
JOYBUS->SCR = ((length * 8) << JOYBUS_SCR_TX_LENGTH_BIT) | JOYBUS_SCR_TX_START;
}
@ -61,6 +61,7 @@ void joybus_set_eeprom (enum eeprom_type eeprom_type) {
void joybus_init (void) {
JOYBUS->SCR = JOYBUS_SCR_TX_RESET | JOYBUS_SCR_RX_RESET;
p.eeprom_type = EEPROM_NONE;
p.rtc_running = true;
p.rtc_write_protect = RTC_WP_MASK;
@ -120,9 +121,9 @@ void process_joybus (void) {
}
} else if (rx_data[1] == RTC_BLOCK_TIME) {
rtc_time_t *rtc_time = rtc_get_time();
tx_data[0] = rtc_time->seconds;
tx_data[1] = rtc_time->minutes;
tx_data[2] = rtc_time->hours | 0x80;
tx_data[0] = rtc_time->second;
tx_data[1] = rtc_time->minute;
tx_data[2] = rtc_time->hour | 0x80;
tx_data[4] = rtc_time->weekday - 1;
tx_data[3] = rtc_time->day;
tx_data[5] = rtc_time->month;
@ -139,9 +140,9 @@ void process_joybus (void) {
p.rtc_running = (!(rx_data[3] & RTC_ST));
} else if (rx_data[1] == RTC_BLOCK_TIME && (!(p.rtc_write_protect & RTC_WP_TIME))) {
rtc_time_t rtc_time;
rtc_time.seconds = rx_data[2];
rtc_time.minutes = rx_data[3];
rtc_time.hours = rx_data[4] & 0x7F;
rtc_time.second = rx_data[2];
rtc_time.minute = rx_data[3];
rtc_time.hour = rx_data[4] & 0x7F;
rtc_time.weekday = rx_data[6] + 1;
rtc_time.day = rx_data[5];
rtc_time.month = rx_data[7];

12
sw/riscv/src/rtc.c
View File

@ -121,9 +121,9 @@ void process_rtc (void) {
} else if (p.time_valid) {
p.running = p.data[RTCSEC] & RTCSEC_ST;
sanitize_time(p.data);
p.time.seconds = p.data[RTCSEC];
p.time.minutes = p.data[RTCMIN];
p.time.hours = p.data[RTCHOUR];
p.time.second = p.data[RTCSEC];
p.time.minute = p.data[RTCMIN];
p.time.hour = p.data[RTCHOUR];
p.time.weekday = p.data[RTCWKDAY];
p.time.day = p.data[RTCDATE];
p.time.month = p.data[RTCMTH];
@ -162,8 +162,8 @@ void process_rtc (void) {
p.i2c_write = true;
p.i2c_length = 7;
p.data[0] = RTCMIN;
p.data[1] = p.time.minutes;
p.data[2] = p.time.hours;
p.data[1] = p.time.minute;
p.data[2] = p.time.hour;
p.data[3] = p.time.weekday | RTCWKDAY_VBAT;
p.data[4] = p.time.day;
p.data[5] = p.time.month;
@ -177,7 +177,7 @@ void process_rtc (void) {
p.i2c_length = 2;
p.i2c_first_read_done = false;
p.data[0] = RTCSEC;
p.data[1] = p.time.seconds | RTCSEC_ST;
p.data[1] = p.time.second | RTCSEC_ST;
p.rtc_phase = RTC_PHASE_WAIT_START;
break;

6
sw/riscv/src/rtc.h
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@ -6,9 +6,9 @@
typedef struct {
uint8_t seconds;
uint8_t minutes;
uint8_t hours;
uint8_t second;
uint8_t minute;
uint8_t hour;
uint8_t weekday;
uint8_t day;
uint8_t month;

3
sw/riscv/src/sys.h
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@ -7,9 +7,6 @@
#include <stdbool.h>
#define DEBUG_ENABLED
typedef volatile uint8_t io8_t;
typedef volatile uint32_t io32_t;

15
sw/riscv/src/uart.c
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@ -1,43 +1,50 @@
#include "uart.h"
#include "rtc.h"
#ifdef DEBUG_ENABLED
#ifdef DEBUG
static const char hex_char_map[16] = {
'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
};
#endif
void uart_print (const char *text) {
#ifdef DEBUG
while (*text != '\0') {
while (!(UART->SCR & UART_SCR_TXE));
UART->DR = *text++;
}
#endif
}
void uart_print_02hex (uint8_t number) {
#ifdef DEBUG
char buffer[3];
buffer[0] = hex_char_map[(number >> 4) & 0x0F];
buffer[1] = hex_char_map[number & 0x0F];
buffer[2] = '\0';
uart_print(buffer);
#endif
}
void uart_print_08hex (uint32_t number) {
#ifdef DEBUG
uart_print_02hex((number >> 24) & 0xFF);
uart_print_02hex((number >> 16) & 0xFF);
uart_print_02hex((number >> 8) & 0xFF);
uart_print_02hex((number >> 0) & 0xFF);
}
#endif
}
void uart_init (void) {
#ifdef DEBUG_ENABLED
#ifdef DEBUG
uart_print("App ready!\n");
#endif
}
void process_uart (void) {
#ifdef DEBUG_ENABLED
#ifdef DEBUG
rtc_time_t *time;
if (UART->SCR & USB_SCR_RXNE) {

1
sw/riscv/src/usb.c
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@ -83,6 +83,7 @@ static struct process p;
void usb_init (void) {
USB->SCR = USB_SCR_FLUSH_TX | USB_SCR_FLUSH_RX;
p.state = STATE_IDLE;
}