diff --git a/.gitmodules b/.gitmodules index 55350ea..34acb04 100644 --- a/.gitmodules +++ b/.gitmodules @@ -2,3 +2,7 @@ path = sw/cic url = https://github.com/ManCloud/UltraCIC-III.git ignore = dirty +[submodule "fw/v2/picorv32"] + path = fw/v2/picorv32 + url = https://github.com/cliffordwolf/picorv32.git + ignore = dirty diff --git a/fw/.gitignore b/fw/v1/.gitignore similarity index 100% rename from fw/.gitignore rename to fw/v1/.gitignore diff --git a/fw/README.md b/fw/v1/README.md similarity index 100% rename from fw/README.md rename to fw/v1/README.md diff --git a/fw/SummerCart64.qpf b/fw/v1/SummerCart64.qpf similarity index 100% rename from fw/SummerCart64.qpf rename to fw/v1/SummerCart64.qpf diff --git a/fw/SummerCart64.qsf b/fw/v1/SummerCart64.qsf similarity index 100% rename from fw/SummerCart64.qsf rename to fw/v1/SummerCart64.qsf diff --git a/fw/constraints.sdc b/fw/v1/constraints.sdc similarity index 100% rename from fw/constraints.sdc rename to fw/v1/constraints.sdc diff --git a/fw/rtl/cart/cart_control.v b/fw/v1/rtl/cart/cart_control.v similarity index 100% rename from fw/rtl/cart/cart_control.v rename to fw/v1/rtl/cart/cart_control.v diff --git a/fw/rtl/cart/cart_led.v b/fw/v1/rtl/cart/cart_led.v similarity index 100% rename from fw/rtl/cart/cart_led.v rename to fw/v1/rtl/cart/cart_led.v diff --git a/fw/rtl/constants.vh b/fw/v1/rtl/constants.vh similarity index 100% rename from fw/rtl/constants.vh rename to fw/v1/rtl/constants.vh diff --git a/fw/rtl/flashram/flashram_controller.v b/fw/v1/rtl/flashram/flashram_controller.v similarity index 100% rename from fw/rtl/flashram/flashram_controller.v rename to fw/v1/rtl/flashram/flashram_controller.v diff --git a/fw/rtl/glue/device_arbiter.v b/fw/v1/rtl/glue/device_arbiter.v similarity index 100% rename from fw/rtl/glue/device_arbiter.v rename to fw/v1/rtl/glue/device_arbiter.v diff --git a/fw/rtl/intel/fifo/fifo_sd.qip b/fw/v1/rtl/intel/fifo/fifo_sd.qip similarity index 100% rename from fw/rtl/intel/fifo/fifo_sd.qip rename to fw/v1/rtl/intel/fifo/fifo_sd.qip diff --git a/fw/rtl/intel/fifo/fifo_sd.v b/fw/v1/rtl/intel/fifo/fifo_sd.v similarity index 100% rename from fw/rtl/intel/fifo/fifo_sd.v rename to fw/v1/rtl/intel/fifo/fifo_sd.v diff --git a/fw/rtl/intel/fifo/fifo_usb.qip b/fw/v1/rtl/intel/fifo/fifo_usb.qip similarity index 100% rename from fw/rtl/intel/fifo/fifo_usb.qip rename to fw/v1/rtl/intel/fifo/fifo_usb.qip diff --git a/fw/rtl/intel/fifo/fifo_usb.v b/fw/v1/rtl/intel/fifo/fifo_usb.v similarity index 100% rename from fw/rtl/intel/fifo/fifo_usb.v rename to fw/v1/rtl/intel/fifo/fifo_usb.v diff --git a/fw/rtl/intel/flash/onchip_flash.qsys b/fw/v1/rtl/intel/flash/onchip_flash.qsys similarity index 100% rename from fw/rtl/intel/flash/onchip_flash.qsys rename to fw/v1/rtl/intel/flash/onchip_flash.qsys diff --git a/fw/rtl/intel/gpio/gpio_ddro.qip b/fw/v1/rtl/intel/gpio/gpio_ddro.qip similarity index 100% rename from fw/rtl/intel/gpio/gpio_ddro.qip rename to fw/v1/rtl/intel/gpio/gpio_ddro.qip diff --git a/fw/rtl/intel/gpio/gpio_ddro.v b/fw/v1/rtl/intel/gpio/gpio_ddro.v similarity index 100% rename from fw/rtl/intel/gpio/gpio_ddro.v rename to fw/v1/rtl/intel/gpio/gpio_ddro.v diff --git a/fw/rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv b/fw/v1/rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv similarity index 100% rename from fw/rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv rename to fw/v1/rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv diff --git a/fw/rtl/intel/pll/pll.ppf b/fw/v1/rtl/intel/pll/pll.ppf similarity index 100% rename from fw/rtl/intel/pll/pll.ppf rename to fw/v1/rtl/intel/pll/pll.ppf diff --git a/fw/rtl/intel/pll/pll.qip b/fw/v1/rtl/intel/pll/pll.qip similarity index 100% rename from fw/rtl/intel/pll/pll.qip rename to fw/v1/rtl/intel/pll/pll.qip diff --git a/fw/rtl/intel/pll/pll.v b/fw/v1/rtl/intel/pll/pll.v similarity index 100% rename from fw/rtl/intel/pll/pll.v rename to fw/v1/rtl/intel/pll/pll.v diff --git a/fw/rtl/intel/ram/ram_flashram_write_buffer.qip b/fw/v1/rtl/intel/ram/ram_flashram_write_buffer.qip similarity index 100% rename from fw/rtl/intel/ram/ram_flashram_write_buffer.qip rename to fw/v1/rtl/intel/ram/ram_flashram_write_buffer.qip diff --git a/fw/rtl/intel/ram/ram_flashram_write_buffer.v b/fw/v1/rtl/intel/ram/ram_flashram_write_buffer.v similarity index 100% rename from fw/rtl/intel/ram/ram_flashram_write_buffer.v rename to fw/v1/rtl/intel/ram/ram_flashram_write_buffer.v diff --git a/fw/rtl/intel/ram/ram_n64_eeprom.qip b/fw/v1/rtl/intel/ram/ram_n64_eeprom.qip similarity index 100% rename from fw/rtl/intel/ram/ram_n64_eeprom.qip rename to fw/v1/rtl/intel/ram/ram_n64_eeprom.qip diff --git a/fw/rtl/intel/ram/ram_n64_eeprom.v b/fw/v1/rtl/intel/ram/ram_n64_eeprom.v similarity index 100% rename from fw/rtl/intel/ram/ram_n64_eeprom.v rename to fw/v1/rtl/intel/ram/ram_n64_eeprom.v diff --git a/fw/rtl/memory/memory_embedded_flash.v b/fw/v1/rtl/memory/memory_embedded_flash.v similarity index 100% rename from fw/rtl/memory/memory_embedded_flash.v rename to fw/v1/rtl/memory/memory_embedded_flash.v diff --git a/fw/rtl/memory/memory_sdram.v b/fw/v1/rtl/memory/memory_sdram.v similarity index 100% rename from fw/rtl/memory/memory_sdram.v rename to fw/v1/rtl/memory/memory_sdram.v diff --git a/fw/rtl/n64/n64_bank_decoder.v b/fw/v1/rtl/n64/n64_bank_decoder.v similarity index 100% rename from fw/rtl/n64/n64_bank_decoder.v rename to fw/v1/rtl/n64/n64_bank_decoder.v diff --git a/fw/rtl/n64/n64_pi.v b/fw/v1/rtl/n64/n64_pi.v similarity index 100% rename from fw/rtl/n64/n64_pi.v rename to fw/v1/rtl/n64/n64_pi.v diff --git a/fw/rtl/n64/n64_si.v b/fw/v1/rtl/n64/n64_si.v similarity index 100% rename from fw/rtl/n64/n64_si.v rename to fw/v1/rtl/n64/n64_si.v diff --git a/fw/rtl/sd/sd_clk.v b/fw/v1/rtl/sd/sd_clk.v similarity index 100% rename from fw/rtl/sd/sd_clk.v rename to fw/v1/rtl/sd/sd_clk.v diff --git a/fw/rtl/sd/sd_cmd.v b/fw/v1/rtl/sd/sd_cmd.v similarity index 100% rename from fw/rtl/sd/sd_cmd.v rename to fw/v1/rtl/sd/sd_cmd.v diff --git a/fw/rtl/sd/sd_crc_16.v b/fw/v1/rtl/sd/sd_crc_16.v similarity index 100% rename from fw/rtl/sd/sd_crc_16.v rename to fw/v1/rtl/sd/sd_crc_16.v diff --git a/fw/rtl/sd/sd_crc_7.v b/fw/v1/rtl/sd/sd_crc_7.v similarity index 100% rename from fw/rtl/sd/sd_crc_7.v rename to fw/v1/rtl/sd/sd_crc_7.v diff --git a/fw/rtl/sd/sd_dat.v b/fw/v1/rtl/sd/sd_dat.v similarity index 100% rename from fw/rtl/sd/sd_dat.v rename to fw/v1/rtl/sd/sd_dat.v diff --git a/fw/rtl/sd/sd_dma.v b/fw/v1/rtl/sd/sd_dma.v similarity index 100% rename from fw/rtl/sd/sd_dma.v rename to fw/v1/rtl/sd/sd_dma.v diff --git a/fw/rtl/sd/sd_fifo.v b/fw/v1/rtl/sd/sd_fifo.v similarity index 100% rename from fw/rtl/sd/sd_fifo.v rename to fw/v1/rtl/sd/sd_fifo.v diff --git a/fw/rtl/sd/sd_interface.v b/fw/v1/rtl/sd/sd_interface.v similarity index 100% rename from fw/rtl/sd/sd_interface.v rename to fw/v1/rtl/sd/sd_interface.v diff --git a/fw/rtl/sd/sd_regs.v b/fw/v1/rtl/sd/sd_regs.v similarity index 100% rename from fw/rtl/sd/sd_regs.v rename to fw/v1/rtl/sd/sd_regs.v diff --git a/fw/rtl/top.v b/fw/v1/rtl/top.v similarity index 100% rename from fw/rtl/top.v rename to fw/v1/rtl/top.v diff --git a/fw/rtl/usb/usb_ftdi_fsi.v b/fw/v1/rtl/usb/usb_ftdi_fsi.v similarity index 100% rename from fw/rtl/usb/usb_ftdi_fsi.v rename to fw/v1/rtl/usb/usb_ftdi_fsi.v diff --git a/fw/rtl/usb/usb_pc.v b/fw/v1/rtl/usb/usb_pc.v similarity index 100% rename from fw/rtl/usb/usb_pc.v rename to fw/v1/rtl/usb/usb_pc.v diff --git a/fw/v2/.gitignore b/fw/v2/.gitignore new file mode 100644 index 0000000..34a27b1 --- /dev/null +++ b/fw/v2/.gitignore @@ -0,0 +1,9 @@ +/db +/greybox_tmp +/incremental_db +/output_files +**/.qsys_edit +*.qws +*.rpt +*.txt +*.sopcinfo diff --git a/fw/v2/SummerCart64.qpf b/fw/v2/SummerCart64.qpf new file mode 100644 index 0000000..b58ed21 --- /dev/null +++ b/fw/v2/SummerCart64.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 10:53:32 August 01, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "10:53:32 August 01, 2021" + +# Revisions + +PROJECT_REVISION = "SummerCart64" diff --git a/fw/v2/SummerCart64.qsf b/fw/v2/SummerCart64.qsf new file mode 100644 index 0000000..6df6d94 --- /dev/null +++ b/fw/v2/SummerCart64.qsf @@ -0,0 +1,208 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:10:16 August 01, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# SummerCart64_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:53:32 AUGUST 01, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_6 -to io_pmod[3] +set_location_assignment PIN_7 -to io_pmod[4] +set_location_assignment PIN_8 -to io_pmod[5] +set_location_assignment PIN_10 -to io_pmod[6] +set_location_assignment PIN_11 -to io_pmod[7] +set_location_assignment PIN_12 -to o_ftdi_si +set_location_assignment PIN_13 -to o_ftdi_clk +set_location_assignment PIN_14 -to i_ftdi_so +set_location_assignment PIN_15 -to i_ftdi_cts +set_location_assignment PIN_17 -to o_led +set_location_assignment PIN_21 -to o_rtc_scl +set_location_assignment PIN_22 -to io_rtc_sda +set_location_assignment PIN_24 -to io_n64_si_dq +set_location_assignment PIN_25 -to i_n64_nmi +set_location_assignment PIN_26 -to i_clk +set_location_assignment PIN_27 -to i_n64_reset +set_location_assignment PIN_28 -to i_n64_si_clk +set_location_assignment PIN_32 -to io_n64_pi_ad[7] +set_location_assignment PIN_33 -to io_n64_pi_ad[8] +set_location_assignment PIN_38 -to io_n64_pi_ad[6] +set_location_assignment PIN_39 -to io_n64_pi_ad[9] +set_location_assignment PIN_41 -to io_n64_pi_ad[5] +set_location_assignment PIN_43 -to io_n64_pi_ad[10] +set_location_assignment PIN_44 -to io_n64_pi_ad[4] +set_location_assignment PIN_45 -to io_n64_pi_ad[11] +set_location_assignment PIN_46 -to i_n64_pi_aleh +set_location_assignment PIN_47 -to i_n64_pi_read +set_location_assignment PIN_48 -to i_n64_pi_write +set_location_assignment PIN_50 -to i_n64_pi_alel +set_location_assignment PIN_52 -to io_n64_pi_ad[12] +set_location_assignment PIN_54 -to io_n64_pi_ad[3] +set_location_assignment PIN_55 -to io_n64_pi_ad[13] +set_location_assignment PIN_56 -to io_n64_pi_ad[2] +set_location_assignment PIN_57 -to io_n64_pi_ad[14] +set_location_assignment PIN_58 -to io_n64_pi_ad[1] +set_location_assignment PIN_59 -to io_n64_pi_ad[15] +set_location_assignment PIN_60 -to io_n64_pi_ad[0] +set_location_assignment PIN_61 -to o_sdram_a[4] +set_location_assignment PIN_62 -to o_sdram_a[5] +set_location_assignment PIN_64 -to o_sdram_a[6] +set_location_assignment PIN_65 -to o_sdram_a[7] +set_location_assignment PIN_66 -to o_sdram_a[8] +set_location_assignment PIN_69 -to o_sdram_a[9] +set_location_assignment PIN_70 -to o_sdram_a[11] +set_location_assignment PIN_74 -to o_sdram_a[12] +set_location_assignment PIN_75 -to o_sdram_clk +set_location_assignment PIN_76 -to o_sdram_a[3] +set_location_assignment PIN_77 -to o_sdram_a[2] +set_location_assignment PIN_78 -to o_sdram_a[1] +set_location_assignment PIN_79 -to o_sdram_a[0] +set_location_assignment PIN_80 -to o_sdram_a[10] +set_location_assignment PIN_81 -to o_sdram_ba[1] +set_location_assignment PIN_84 -to o_sdram_ba[0] +set_location_assignment PIN_85 -to o_sdram_cs +set_location_assignment PIN_86 -to o_sdram_ras +set_location_assignment PIN_87 -to o_sdram_cas +set_location_assignment PIN_88 -to o_sdram_we +set_location_assignment PIN_89 -to io_sdram_dq[7] +set_location_assignment PIN_90 -to io_sdram_dq[6] +set_location_assignment PIN_91 -to io_sdram_dq[5] +set_location_assignment PIN_92 -to io_sdram_dq[4] +set_location_assignment PIN_93 -to io_sdram_dq[3] +set_location_assignment PIN_96 -to io_sdram_dq[2] +set_location_assignment PIN_97 -to io_sdram_dq[1] +set_location_assignment PIN_98 -to io_sdram_dq[0] +set_location_assignment PIN_99 -to io_sdram_dq[8] +set_location_assignment PIN_100 -to io_sdram_dq[9] +set_location_assignment PIN_101 -to io_sdram_dq[10] +set_location_assignment PIN_102 -to io_sdram_dq[11] +set_location_assignment PIN_105 -to io_sdram_dq[12] +set_location_assignment PIN_106 -to io_sdram_dq[13] +set_location_assignment PIN_110 -to io_sdram_dq[14] +set_location_assignment PIN_111 -to io_sdram_dq[15] +set_location_assignment PIN_112 -to io_sd_dat[1] +set_location_assignment PIN_113 -to io_sd_dat[0] +set_location_assignment PIN_114 -to o_sd_clk +set_location_assignment PIN_118 -to io_sd_cmd +set_location_assignment PIN_119 -to io_sd_dat[3] +set_location_assignment PIN_120 -to io_sd_dat[2] +set_location_assignment PIN_123 -to o_n64_int +set_location_assignment PIN_138 -to io_pmod[0] +set_location_assignment PIN_140 -to io_pmod[1] +set_location_assignment PIN_141 -to io_pmod[2] + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY SummerCart64 +set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE 10M08SCE144C8G +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + +# Assembler Assignments +# ===================== +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# -------------------------- +# start ENTITY(SummerCart64) + + # Fitter Assignments + # ================== +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_nmi +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_aleh +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_alel +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_read +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_write +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_n64_int + +# end ENTITY(SummerCart64) +# ------------------------ +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name SYSTEMVERILOG_FILE rtl/pll.sv +set_global_assignment -name SDC_FILE SummerCart64.sdc +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SummerCart64.sv +set_global_assignment -name QIP_FILE rtl/intel/intel_pll.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fw/v2/SummerCart64.sdc b/fw/v2/SummerCart64.sdc new file mode 100644 index 0000000..a6d4eba --- /dev/null +++ b/fw/v2/SummerCart64.sdc @@ -0,0 +1,74 @@ +# Clocks + +derive_pll_clocks -create_base_clocks + +# set sys_clk {sys_pll|altpll_component|auto_generated|pll1|clk[0]} +# set sdram_pll_clk {sys_pll|altpll_component|auto_generated|pll1|clk[1]} +# set sd_reg_clk {sd_interface_inst|sd_clk_inst|o_sd_clk|q} + +# create_generated_clock -name sdram_clk -source [get_pins $sdram_pll_clk] [get_ports {o_sdram_clk}] +# create_generated_clock -name sd_reg_clk -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] -divide_by 2 [get_pins $sd_reg_clk] +# create_generated_clock -name sd_clk -source [get_pins $sd_reg_clk] [get_ports {o_sd_clk}] + +# create_generated_clock -name flash_se_neg_reg \ +# -source [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk}] \ +# -divide_by 2 \ +# [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q}] + +derive_clock_uncertainty + + +# # SDRAM timings + +# set sdram_outputs {o_sdram_cs o_sdram_ras o_sdram_cas o_sdram_we o_sdram_a[*] o_sdram_ba[*] io_sdram_dq[*]} +# set sdram_inputs {io_sdram_dq[*]} + +# set_output_delay -clock [get_clocks {sdram_clk}] -max 1.5 [get_ports $sdram_outputs] +# set_output_delay -clock [get_clocks {sdram_clk}] -min -0.8 [get_ports $sdram_outputs] + +# set_input_delay -clock [get_clocks {sdram_clk}] -max 5.4 [get_ports $sdram_inputs] +# set_input_delay -clock [get_clocks {sdram_clk}] -min 2.5 [get_ports $sdram_inputs] + +# set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks $sys_clk] + + +# # FTDI timings + +# set_false_path -to [get_ports {o_ftdi_clk o_ftdi_si}] +# set_false_path -from [get_ports {i_ftdi_so i_ftdi_cts}] + + +# # SD card timings + +# set_output_delay -clock [get_clocks {sd_clk}] -max 6.0 [get_ports {io_sd_cmd io_sd_dat[*]}] +# set_output_delay -clock [get_clocks {sd_clk}] -min -2.0 [get_ports {io_sd_cmd io_sd_dat[*]}] + +# set_input_delay -clock [get_clocks {sd_clk}] -max 15.0 [get_ports {io_sd_cmd io_sd_dat[*]}] +# set_input_delay -clock [get_clocks {sd_clk}] -min 6.5 [get_ports {io_sd_cmd io_sd_dat[*]}] + +# set_multicycle_path -hold -start 1 -from [get_clocks $sys_clk] -to [get_clocks {sd_clk}] + +# set_multicycle_path -setup -end 3 -from [get_clocks {sd_clk}] -to [get_clocks $sys_clk] +# set_multicycle_path -hold -end 1 -from [get_clocks {sd_clk}] -to [get_clocks $sys_clk] + + +# # N64, PI and SI timings + +# set_false_path -from [get_ports {i_n64_reset i_n64_nmi}] + +# set_false_path -to [get_ports {io_n64_pi_ad[*]}] +# set_false_path -from [get_ports {i_n64_pi_* io_n64_pi_ad[*]}] + +# set_false_path -to [get_ports {io_n64_si_dq}] +# set_false_path -from [get_ports {i_n64_si_clk io_n64_si_dq}] + + +# LED timings + +set_false_path -to [get_ports {o_led}] + + +# # PMOD timings + +# set_false_path -to [get_ports {io_pmod[*]}] +# set_false_path -from [get_ports {io_pmod[*]}] diff --git a/fw/v2/picorv32 b/fw/v2/picorv32 new file mode 160000 index 0000000..f9b1beb --- /dev/null +++ b/fw/v2/picorv32 @@ -0,0 +1 @@ +Subproject commit f9b1beb4cfd6b382157b54bc8f38c61d5ae7d785 diff --git a/fw/v2/rtl/SummerCart64.sv b/fw/v2/rtl/SummerCart64.sv new file mode 100644 index 0000000..b6a2d61 --- /dev/null +++ b/fw/v2/rtl/SummerCart64.sv @@ -0,0 +1,62 @@ +module SummerCart64 ( + input i_clk, + + output o_ftdi_clk, + output o_ftdi_si, + input i_ftdi_so, + input i_ftdi_cts, + + input i_n64_reset, + input i_n64_nmi, + output o_n64_int, + + input i_n64_pi_alel, + input i_n64_pi_aleh, + input i_n64_pi_read, + input i_n64_pi_write, + inout [15:0] io_n64_pi_ad, + + input i_n64_si_clk, + inout io_n64_si_dq, + + output o_sdram_clk, + output o_sdram_cs, + output o_sdram_ras, + output o_sdram_cas, + output o_sdram_we, + output [1:0] o_sdram_ba, + output [12:0] o_sdram_a, + inout [15:0] io_sdram_dq, + + output o_sd_clk, + inout io_sd_cmd, + inout [3:0] io_sd_dat, + + output o_rtc_scl, + inout io_rtc_sda, + + output o_led, + + inout [7:0] io_pmod +); + + if_pll if_pll_inst (.in_clk(i_clk)); + + pll pll_inst (.iface(if_pll_inst)); + + + + reg [31:0] counter; + + always_ff @(posedge if_pll_inst.sys.clk) begin + counter <= counter + 1'd1; + if (counter >= 32'd100_000_000) begin + counter <= 1'd0; + end + end + + always_comb begin + o_led = counter < 32'd1_000_000; + end + +endmodule diff --git a/fw/v2/rtl/intel/intel_pll.ppf b/fw/v2/rtl/intel/intel_pll.ppf new file mode 100644 index 0000000..bf13a5c --- /dev/null +++ b/fw/v2/rtl/intel/intel_pll.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/fw/v2/rtl/intel/intel_pll.qip b/fw/v2/rtl/intel/intel_pll.qip new file mode 100644 index 0000000..f3d15cc --- /dev/null +++ b/fw/v2/rtl/intel/intel_pll.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "20.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "intel_pll.ppf"] diff --git a/fw/v2/rtl/intel/intel_pll.v b/fw/v2/rtl/intel/intel_pll.v new file mode 100644 index 0000000..7a4bdcc --- /dev/null +++ b/fw/v2/rtl/intel/intel_pll.v @@ -0,0 +1,341 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: intel_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 20.1.1 Build 720 11/11/2020 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2020 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module intel_pll ( + inclk0, + c0, + c1, + locked); + + input inclk0; + output c0; + output c1; + output locked; + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire6; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [1:1] sub_wire5 = sub_wire3[1:1]; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + wire c1 = sub_wire5; + wire locked = sub_wire6; + + altpll altpll_component ( + .inclk (sub_wire1), + .clk (sub_wire3), + .locked (sub_wire6), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 2, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 2, + altpll_component.clk1_phase_shift = "-1500", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "MAX 10", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=intel_pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "ON", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-54.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "intel_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1500" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/fw/v2/rtl/pll.sv b/fw/v2/rtl/pll.sv new file mode 100644 index 0000000..8c69ac4 --- /dev/null +++ b/fw/v2/rtl/pll.sv @@ -0,0 +1,41 @@ +interface if_pll ( + input in_clk +); + + logic clk; + logic sdram_clk; + logic reset; + + modport pll ( + input in_clk, + output clk, + output sdram_clk, + output reset + ); + + modport sys ( + input clk, + input reset + ); + + modport sdram ( + input sdram_clk + ); + +endinterface + + +module pll (if_pll.pll iface); + + wire locked; + + assign iface.reset = ~locked; + + intel_pll intel_pll_inst ( + .inclk0(iface.in_clk), + .c0(iface.clk), + .c1(iface.sdram_clk), + .locked(locked) + ); + +endmodule