diff --git a/fw/project/lcmxo2/release.sty b/fw/project/lcmxo2/release.sty
index 8224709..3408612 100644
--- a/fw/project/lcmxo2/release.sty
+++ b/fw/project/lcmxo2/release.sty
@@ -92,7 +92,7 @@
     <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
     <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
     <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
-    <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
     <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
     <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
     <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
diff --git a/fw/project/lcmxo2/sc64.ldf b/fw/project/lcmxo2/sc64.ldf
index d00a47e..9bdab48 100644
--- a/fw/project/lcmxo2/sc64.ldf
+++ b/fw/project/lcmxo2/sc64.ldf
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <BaliProject version="3.2" title="sc64" device="LCMXO2-7000HC-6TG144C" default_implementation="impl1">
     <Options/>
-    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="debug">
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="release">
         <Options VerilogStandard="System Verilog" def_top="top" top="top"/>
         <Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>