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register PI reg bus

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This commit is contained in:
Mateusz Faderewski 2024-06-12 02:21:13 +02:00
parent 0d9e23b787
commit 2a33bffd72
1 changed files with 8 additions and 6 deletions
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14
fw/rtl/n64/n64_pi.sv
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@ -476,7 +476,11 @@ module n64_pi (
// Reg bus controller // Reg bus controller
logic reg_bus_address_increment;
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
reg_bus_address_increment <= read_op || write_op;
if (aleh_op) begin if (aleh_op) begin
reg_bus.address[16] <= n64_pi_dq_in[0]; reg_bus.address[16] <= n64_pi_dq_in[0];
end end
@ -485,15 +489,13 @@ module n64_pi (
reg_bus.address[15:0] <= n64_pi_dq_in; reg_bus.address[15:0] <= n64_pi_dq_in;
end end
if (read_op || write_op) begin if (reg_bus_address_increment) begin
reg_bus.address <= reg_bus.address + 2'd2; reg_bus.address <= reg_bus.address + 2'd2;
end end
end
always_comb begin reg_bus.read <= read_op && (read_port == PORT_REG);
reg_bus.read = read_op && (read_port == PORT_REG); reg_bus.write <= write_op && (write_port == PORT_REG);
reg_bus.write = write_op && (write_port == PORT_REG); reg_bus.wdata <= n64_pi_dq_in;
reg_bus.wdata = n64_pi_dq_in;
end end
endmodule endmodule