mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2025-01-13 04:59:09 +01:00
another cleanup
This commit is contained in:
parent
5cba981f82
commit
392ad5bece
@ -31,7 +31,8 @@ SRC_FILES = \
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exception.S \
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exception.S \
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font.c \
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font.c \
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init.c \
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init.c \
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interrupt.c \
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interrupts.c \
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interrupts.S \
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io.c \
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io.c \
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main.c \
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main.c \
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menu.c \
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menu.c \
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@ -1,8 +1,6 @@
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#include "vr4300.h"
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#include "vr4300.h"
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#define WATCHDOG_TIMEOUT (5 * (93750000UL / 2))
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#define ZR_OFFSET (0)
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#define ZR_OFFSET (0)
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#define AT_OFFSET (8)
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#define AT_OFFSET (8)
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#define V0_OFFSET (16)
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#define V0_OFFSET (16)
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@ -51,14 +49,18 @@ exception_xtlb_miss:
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.org 0x0080
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.org 0x0080
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j exception_handler
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j exception_handler
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exception_ecc:
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.org 0x0100
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j exception_handler
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exception_other:
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exception_other:
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.org 0x0180
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.org 0x0180
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j exception_handler
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j exception_handler
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.section .text.exception_handler
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.section .text.exception_handler
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exception_handler:
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.type exception_handler, %function
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.type exception_handler, %function
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exception_handler:
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.set noat
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.set noat
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la $k0, (_esp - SAVE_REGISTERS_SIZE)
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la $k0, (_esp - SAVE_REGISTERS_SIZE)
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sd $zero, ZR_OFFSET($k0)
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sd $zero, ZR_OFFSET($k0)
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@ -124,7 +126,7 @@ exception_interrupt:
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andi $t0, C0_SR_IM_MASK
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andi $t0, C0_SR_IM_MASK
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srl $t0, C0_SR_IM_BIT
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srl $t0, C0_SR_IM_BIT
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and $a0, $t0
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and $a0, $t0
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jal exception_interrupt_handler
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jal interrupts_handler
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exception_restore:
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exception_restore:
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.set noat
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.set noat
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@ -160,51 +162,3 @@ exception_restore:
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.set at
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.set at
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eret
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eret
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.section .text.exception_enable_interrupts
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exception_enable_interrupts:
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.type exception_enable_interrupts, %function
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.global exception_enable_interrupts
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mfc0 $t0, C0_STATUS
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li $t1, (C0_SR_IM4 | C0_SR_IM3 | C0_SR_IE)
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or $t0, $t1
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mtc0 $t0, C0_STATUS
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jr $ra
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.section .text.exception_disable_interrupts
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exception_disable_interrupts:
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.type exception_disable_interrupts, %function
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.global exception_disable_interrupts
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mfc0 $t0, C0_STATUS
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li $t1, ~(C0_SR_IM4 | C0_SR_IM3 | C0_SR_IE)
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and $t0, $t1
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mtc0 $t0, C0_STATUS
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jr $ra
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.section .text.exception_enable_watchdog
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exception_enable_watchdog:
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.type exception_enable_watchdog, %function
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.global exception_enable_watchdog
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mtc0 $zero, C0_COUNT
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li $t1, WATCHDOG_TIMEOUT
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mtc0 $t1, C0_COMPARE
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mfc0 $t0, C0_STATUS
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li $t1, C0_SR_IM7
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or $t0, $t1
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mtc0 $t0, C0_STATUS
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jr $ra
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.section .text.exception_disable_watchdog
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exception_disable_watchdog:
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.type exception_disable_watchdog, %function
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.global exception_disable_watchdog
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mfc0 $t0, C0_STATUS
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li $t1, ~(C0_SR_IM7)
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and $t0, $t1
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mtc0 $t0, C0_STATUS
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mtc0 $zero, C0_COMPARE
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jr $ra
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@ -1,6 +1,5 @@
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#include <stdarg.h>
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#include <stdarg.h>
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#include "display.h"
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#include "display.h"
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#include "exception_regs.h"
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#include "exception.h"
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#include "exception.h"
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#include "io.h"
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#include "io.h"
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#include "version.h"
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#include "version.h"
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@ -2,10 +2,55 @@
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#define EXCEPTION_H__
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#define EXCEPTION_H__
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void exception_enable_interrupts (void);
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#include <stdint.h>
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void exception_disable_interrupts (void);
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void exception_enable_watchdog (void);
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void exception_disable_watchdog (void);
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typedef union {
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uint64_t u64;
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struct {
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uint32_t u32_h;
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uint32_t u32;
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};
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} uint64_32_t;
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typedef struct {
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uint64_32_t zr;
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uint64_32_t at;
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uint64_32_t v0;
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uint64_32_t v1;
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uint64_32_t a0;
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uint64_32_t a1;
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uint64_32_t a2;
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uint64_32_t a3;
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uint64_32_t t0;
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uint64_32_t t1;
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uint64_32_t t2;
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uint64_32_t t3;
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uint64_32_t t4;
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uint64_32_t t5;
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uint64_32_t t6;
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uint64_32_t t7;
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uint64_32_t s0;
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uint64_32_t s1;
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uint64_32_t s2;
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uint64_32_t s3;
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uint64_32_t s4;
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uint64_32_t s5;
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uint64_32_t s6;
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uint64_32_t s7;
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uint64_32_t t8;
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uint64_32_t t9;
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uint64_32_t k0;
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uint64_32_t k1;
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uint64_32_t gp;
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uint64_32_t sp;
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uint64_32_t s8;
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uint64_32_t ra;
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uint32_t sr;
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uint32_t cr;
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uint64_32_t epc;
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uint64_32_t badvaddr;
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} exception_t;
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#endif
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#endif
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@ -1,56 +0,0 @@
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#ifndef EXCEPTION_REGS_H__
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#define EXCEPTION_REGS_H__
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#include <stdint.h>
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typedef union {
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uint64_t u64;
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struct {
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uint32_t u32_h;
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uint32_t u32;
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};
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} uint64_32_t;
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typedef struct {
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uint64_32_t zr;
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uint64_32_t at;
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uint64_32_t v0;
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uint64_32_t v1;
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uint64_32_t a0;
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uint64_32_t a1;
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uint64_32_t a2;
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uint64_32_t a3;
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uint64_32_t t0;
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uint64_32_t t1;
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uint64_32_t t2;
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uint64_32_t t3;
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uint64_32_t t4;
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uint64_32_t t5;
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uint64_32_t t6;
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uint64_32_t t7;
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uint64_32_t s0;
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uint64_32_t s1;
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uint64_32_t s2;
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uint64_32_t s3;
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uint64_32_t s4;
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uint64_32_t s5;
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uint64_32_t s6;
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uint64_32_t s7;
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uint64_32_t t8;
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uint64_32_t t9;
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uint64_32_t k0;
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uint64_32_t k1;
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uint64_32_t gp;
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uint64_32_t sp;
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uint64_32_t s8;
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uint64_32_t ra;
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uint32_t sr;
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uint32_t cr;
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uint64_32_t epc;
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uint64_32_t badvaddr;
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} exception_t;
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#endif
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@ -1,6 +1,6 @@
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#include "error.h"
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#include "error.h"
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#include "exception.h"
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#include "init.h"
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#include "init.h"
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#include "interrupts.h"
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#include "io.h"
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#include "io.h"
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#include "sc64.h"
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#include "sc64.h"
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#include "test.h"
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#include "test.h"
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@ -24,22 +24,22 @@ void init (init_tv_type_t tv_type, init_reset_type_t reset_type, uint32_t entrop
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error_display("SC64 hardware not detected");
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error_display("SC64 hardware not detected");
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}
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}
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exception_enable_watchdog();
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interrupts_init();
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exception_enable_interrupts();
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interrupts_start_watchdog();
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if ((error = sc64_set_config(CFG_ID_BOOTLOADER_SWITCH, false)) != SC64_OK) {
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if ((error = sc64_set_config(CFG_ID_BOOTLOADER_SWITCH, false)) != SC64_OK) {
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error_display("Command CONFIG_SET [BOOTLOADER_SWITCH] failed\n (%08X) - %s", error, sc64_error_description(error));
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error_display("Command CONFIG_SET [BOOTLOADER_SWITCH] failed\n (%08X) - %s", error, sc64_error_description(error));
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}
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}
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if (test_check()) {
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if (test_check()) {
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exception_disable_watchdog();
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interrupts_stop_watchdog();
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test_execute();
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test_execute();
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}
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}
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}
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}
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void deinit (void) {
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void deinit (void) {
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exception_disable_interrupts();
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interrupts_stop_watchdog();
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exception_disable_watchdog();
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interrupts_disable();
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sc64_lock();
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sc64_lock();
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}
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}
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58
sw/bootloader/src/interrupts.S
Normal file
58
sw/bootloader/src/interrupts.S
Normal file
@ -0,0 +1,58 @@
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#include "vr4300.h"
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#define WATCHDOG_TIMEOUT (5 * (93750000UL / 2))
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.section .text.interrupts
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.type interrupts_init, %function
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.global interrupts_init
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interrupts_init:
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li $t1, (C0_SR_IM4 | C0_SR_IM3 | C0_SR_IE)
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mfc0 $t0, C0_STATUS
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or $t0, $t1
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mtc0 $t0, C0_STATUS
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jr $ra
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.type interrupts_disable, %function
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.global interrupts_disable
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interrupts_disable:
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li $t0, ~(C0_SR_IE)
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mfc0 $v0, C0_STATUS
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and $t0, $v0
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mtc0 $t0, C0_STATUS
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jr $ra
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.type interrupts_restore, %function
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.global interrupts_restore
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interrupts_restore:
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mtc0 $a0, C0_STATUS
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jr $ra
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.type interrupts_start_watchdog, %function
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.global interrupts_start_watchdog
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interrupts_start_watchdog:
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mtc0 $zero, C0_COUNT
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li $t1, WATCHDOG_TIMEOUT
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mtc0 $t1, C0_COMPARE
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li $t1, C0_SR_IM7
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mfc0 $t0, C0_STATUS
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or $t0, $t1
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mtc0 $t0, C0_STATUS
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jr $ra
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.type interrupts_stop_watchdog, %function
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.global interrupts_stop_watchdog
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interrupts_stop_watchdog:
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li $t1, ~(C0_SR_IM7)
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mfc0 $t0, C0_STATUS
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and $t0, $t1
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mtc0 $t0, C0_STATUS
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mtc0 $zero, C0_COMPARE
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jr $ra
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@ -17,8 +17,8 @@ typedef enum {
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} interrupt_t;
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} interrupt_t;
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void exception_interrupt_handler (uint8_t interrupt) {
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void interrupts_handler (uint8_t interrupts) {
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if (interrupt == INTERRUPT_NONE) {
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if (interrupts == INTERRUPT_NONE) {
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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version_print();
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version_print();
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@ -28,8 +28,8 @@ void exception_interrupt_handler (uint8_t interrupt) {
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while (true);
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while (true);
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}
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}
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if (interrupt & INTERRUPT_CART) {
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if (interrupts & INTERRUPT_CART) {
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interrupt &= ~(INTERRUPT_CART);
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interrupts &= ~(INTERRUPT_CART);
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sc64_irq_t irq = sc64_irq_pending();
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sc64_irq_t irq = sc64_irq_pending();
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@ -38,8 +38,8 @@ void exception_interrupt_handler (uint8_t interrupt) {
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}
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}
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}
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}
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if (interrupt & INTERRUPT_PRENMI) {
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if (interrupts & INTERRUPT_PRENMI) {
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interrupt &= ~(INTERRUPT_PRENMI);
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interrupts &= ~(INTERRUPT_PRENMI);
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if (display_ready()) {
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if (display_ready()) {
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display_init(NULL);
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display_init(NULL);
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@ -50,8 +50,8 @@ void exception_interrupt_handler (uint8_t interrupt) {
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while (true);
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while (true);
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}
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}
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if (interrupt & INTERRUPT_TIMER) {
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if (interrupts & INTERRUPT_TIMER) {
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interrupt &= ~(INTERRUPT_TIMER);
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interrupts &= ~(INTERRUPT_TIMER);
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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@ -62,14 +62,14 @@ void exception_interrupt_handler (uint8_t interrupt) {
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while (true);
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while (true);
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}
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}
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if (interrupt != INTERRUPT_NONE) {
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if (interrupts != INTERRUPT_NONE) {
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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version_print();
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version_print();
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display_printf("[ Unhandled interrupt ]\n");
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display_printf("[ Unhandled interrupt(s) ]\n");
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display_printf("Pending (0x%02X):\n", interrupt);
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display_printf("Pending (0x%02X):\n", interrupts);
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for (int i = 0; i < 8; i++) {
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for (int i = 0; i < 8; i++) {
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switch (interrupt & (1 << i)) {
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switch (interrupts & (1 << i)) {
|
||||||
case INTERRUPT_SW_0: display_printf(" (0) Software interrupt\n"); break;
|
case INTERRUPT_SW_0: display_printf(" (0) Software interrupt\n"); break;
|
||||||
case INTERRUPT_SW_1: display_printf(" (1) Software interrupt\n"); break;
|
case INTERRUPT_SW_1: display_printf(" (1) Software interrupt\n"); break;
|
||||||
case INTERRUPT_RCP: display_printf(" (2) RCP interrupt\n"); break;
|
case INTERRUPT_RCP: display_printf(" (2) RCP interrupt\n"); break;
|
15
sw/bootloader/src/interrupts.h
Normal file
15
sw/bootloader/src/interrupts.h
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
#ifndef INTERRUPTS_H__
|
||||||
|
#define INTERRUPTS_H__
|
||||||
|
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
|
||||||
|
void interrupts_init (void);
|
||||||
|
uint32_t interrupts_disable (void);
|
||||||
|
void interrupts_restore (uint32_t sr);
|
||||||
|
void interrupts_start_watchdog (void);
|
||||||
|
void interrupts_stop_watchdog (void);
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
@ -1,3 +1,4 @@
|
|||||||
|
#include "interrupts.h"
|
||||||
#include "io.h"
|
#include "io.h"
|
||||||
#include "vr4300.h"
|
#include "vr4300.h"
|
||||||
|
|
||||||
@ -72,26 +73,38 @@ uint32_t pi_busy (void) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
uint32_t pi_io_read (io32_t *address) {
|
uint32_t pi_io_read (io32_t *address) {
|
||||||
return cpu_io_read(address);
|
uint32_t sr = interrupts_disable();
|
||||||
|
while (pi_busy());
|
||||||
|
uint32_t value = cpu_io_read(address);
|
||||||
|
interrupts_restore(sr);
|
||||||
|
return value;
|
||||||
}
|
}
|
||||||
|
|
||||||
void pi_io_write (io32_t *address, uint32_t value) {
|
void pi_io_write (io32_t *address, uint32_t value) {
|
||||||
cpu_io_write(address, value);
|
uint32_t sr = interrupts_disable();
|
||||||
while (pi_busy());
|
while (pi_busy());
|
||||||
|
cpu_io_write(address, value);
|
||||||
|
interrupts_restore(sr);
|
||||||
}
|
}
|
||||||
|
|
||||||
void pi_dma_read (io32_t *address, void *buffer, size_t length) {
|
void pi_dma_read (io32_t *address, void *buffer, size_t length) {
|
||||||
cache_data_hit_writeback_invalidate(buffer, length);
|
cache_data_hit_writeback_invalidate(buffer, length);
|
||||||
|
uint32_t sr = interrupts_disable();
|
||||||
|
while (pi_busy());
|
||||||
cpu_io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
|
cpu_io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
|
||||||
cpu_io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
|
cpu_io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
|
||||||
cpu_io_write(&PI->WDMA, length - 1);
|
cpu_io_write(&PI->WDMA, length - 1);
|
||||||
|
interrupts_restore(sr);
|
||||||
while (pi_busy());
|
while (pi_busy());
|
||||||
}
|
}
|
||||||
|
|
||||||
void pi_dma_write (io32_t *address, void *buffer, size_t length) {
|
void pi_dma_write (io32_t *address, void *buffer, size_t length) {
|
||||||
cache_data_hit_writeback(buffer, length);
|
cache_data_hit_writeback(buffer, length);
|
||||||
|
uint32_t sr = interrupts_disable();
|
||||||
|
while (pi_busy());
|
||||||
cpu_io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
|
cpu_io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
|
||||||
cpu_io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
|
cpu_io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
|
||||||
cpu_io_write(&PI->RDMA, length - 1);
|
cpu_io_write(&PI->RDMA, length - 1);
|
||||||
|
interrupts_restore(sr);
|
||||||
while (pi_busy());
|
while (pi_busy());
|
||||||
}
|
}
|
||||||
|
@ -214,14 +214,21 @@ sc64_irq_t sc64_irq_pending (void) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void sc64_irq_callback (sc64_irq_t irq) {
|
void sc64_irq_callback (sc64_irq_t irq) {
|
||||||
|
uint32_t clear = 0;
|
||||||
|
if (irq & SC64_IRQ_MCU) {
|
||||||
|
clear |= SC64_IRQ_MCU_CLEAR;
|
||||||
|
}
|
||||||
|
if (irq & SC64_IRQ_CMD) {
|
||||||
|
clear |= SC64_IRQ_CMD_CLEAR;
|
||||||
|
}
|
||||||
|
pi_io_write(&SC64_REGS->IRQ, clear);
|
||||||
if (irq & SC64_IRQ_MCU) {
|
if (irq & SC64_IRQ_MCU) {
|
||||||
sc64_mcu_irq_callback();
|
sc64_mcu_irq_callback();
|
||||||
pi_io_write(&SC64_REGS->IRQ, SC64_IRQ_MCU_CLEAR);
|
|
||||||
}
|
}
|
||||||
if (irq & SC64_IRQ_CMD) {
|
if (irq & SC64_IRQ_CMD) {
|
||||||
sc64_cmd_irq_callback();
|
sc64_cmd_irq_callback();
|
||||||
pi_io_write(&SC64_REGS->IRQ, SC64_IRQ_CMD_CLEAR);
|
|
||||||
}
|
}
|
||||||
|
while (pi_busy());
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -1,27 +1,27 @@
|
|||||||
#include "vr4300.h"
|
#include "vr4300.h"
|
||||||
|
|
||||||
|
|
||||||
|
#define RSP_DMEM_ADDRESS 0xA4000000
|
||||||
|
|
||||||
|
|
||||||
.section .text.entry_handler, "ax", %progbits
|
.section .text.entry_handler, "ax", %progbits
|
||||||
entry_handler:
|
|
||||||
.type entry_handler, %function
|
.type entry_handler, %function
|
||||||
.global entry_handler
|
.global entry_handler
|
||||||
|
entry_handler:
|
||||||
|
li $t0, (C0_SR_CU1 | C0_SR_CU0 | C0_SR_FR)
|
||||||
|
mtc0 $t0, C0_STATUS
|
||||||
|
|
||||||
la $gp, _gp
|
la $gp, _gp
|
||||||
la $sp, _sp
|
la $sp, _sp
|
||||||
|
|
||||||
li $v0, (C0_SR_CU0)
|
li $t0, RSP_DMEM_ADDRESS # IPL3 Boot flags location
|
||||||
mtc0 $v0, C0_STATUS
|
|
||||||
|
|
||||||
lui $t0, 0xA400
|
|
||||||
lbu $a0, 9($t0) # TV type
|
lbu $a0, 9($t0) # TV type
|
||||||
lbu $a1, 10($t0) # Reset type
|
lbu $a1, 10($t0) # Reset type
|
||||||
lw $a2, 4($t0) # Entropy
|
lw $a2, 4($t0) # Entropy
|
||||||
|
|
||||||
la $t0, init
|
jal init
|
||||||
jalr $t0
|
|
||||||
|
|
||||||
la $t0, main
|
jal main
|
||||||
jalr $t0
|
|
||||||
|
|
||||||
loop:
|
loop:
|
||||||
j loop
|
j loop
|
||||||
|
@ -9,6 +9,7 @@
|
|||||||
#define CACHE_LINE_SIZE_I (32)
|
#define CACHE_LINE_SIZE_I (32)
|
||||||
#define CACHE_LINE_SIZE_D (16)
|
#define CACHE_LINE_SIZE_D (16)
|
||||||
|
|
||||||
|
|
||||||
#define C0_BADVADDR $8
|
#define C0_BADVADDR $8
|
||||||
#define C0_COUNT $9
|
#define C0_COUNT $9
|
||||||
#define C0_COMPARE $11
|
#define C0_COMPARE $11
|
||||||
|
Loading…
x
Reference in New Issue
Block a user