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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 07:06:52 +01:00
usb gets fast
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parent
1c8e7a4765
commit
39c2edbb9a
@ -28,6 +28,7 @@ module cpu_usb (
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logic cpu_tx_write;
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logic cpu_tx_write;
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logic usb_enabled;
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logic usb_enabled;
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logic tx_force;
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always_comb begin
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always_comb begin
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dma.rx_empty = rx_empty;
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dma.rx_empty = rx_empty;
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@ -66,6 +67,7 @@ module cpu_usb (
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cpu_tx_write <= 1'b0;
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cpu_tx_write <= 1'b0;
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rx_escape_ack <= 1'b0;
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rx_escape_ack <= 1'b0;
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tx_force <= 1'b0;
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if (sys.reset) begin
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if (sys.reset) begin
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usb_enabled <= 1'b0;
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usb_enabled <= 1'b0;
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@ -73,6 +75,9 @@ module cpu_usb (
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if (bus.request) begin
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if (bus.request) begin
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case (bus.address[2:2])
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case (bus.address[2:2])
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2'd0: begin
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2'd0: begin
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if (bus.wmask[1]) begin
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tx_force <= bus.wdata[8];
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end
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if (bus.wmask[0]) begin
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if (bus.wmask[0]) begin
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rx_escape_ack <= bus.wdata[7];
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rx_escape_ack <= bus.wdata[7];
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{usb_enabled, tx_flush, rx_flush} <= bus.wdata[4:2];
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{usb_enabled, tx_flush, rx_flush} <= bus.wdata[4:2];
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@ -95,6 +100,7 @@ module cpu_usb (
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.sys(sys),
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.sys(sys),
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.usb_enabled(usb_enabled),
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.usb_enabled(usb_enabled),
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.tx_force(tx_force),
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.usb_clk(usb_clk),
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.usb_clk(usb_clk),
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.usb_cs(usb_cs),
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.usb_cs(usb_cs),
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@ -2,6 +2,7 @@ module usb_ft1248 (
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if_system.sys sys,
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if_system.sys sys,
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input usb_enabled,
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input usb_enabled,
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input tx_force,
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output usb_clk,
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output usb_clk,
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output usb_cs,
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output usb_cs,
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@ -111,7 +112,8 @@ module usb_ft1248 (
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typedef enum bit [7:0] {
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typedef enum bit [7:0] {
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C_WRITE = 8'h00,
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C_WRITE = 8'h00,
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C_READ = 8'h04
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C_READ = 8'h04,
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C_FORCE = 8'h80
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} e_command;
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} e_command;
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typedef enum bit [1:0] {
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typedef enum bit [1:0] {
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@ -134,7 +136,9 @@ module usb_ft1248 (
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logic usb_miosi_output_enable_data;
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logic usb_miosi_output_enable_data;
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logic usb_miso_input;
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logic usb_miso_input;
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logic tx_force_pending;
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logic is_cmd_write;
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logic is_cmd_write;
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logic is_cmd_tx_force;
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logic [1:0] nibble_counter;
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logic [1:0] nibble_counter;
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logic [7:0] tx_buffer;
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logic [7:0] tx_buffer;
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@ -168,7 +172,9 @@ module usb_ft1248 (
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S_COMMAND: begin
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S_COMMAND: begin
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usb_clk_output = clock_phase[P_PRE_FALLING] || clock_phase[P_FALLING];
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usb_clk_output = clock_phase[P_PRE_FALLING] || clock_phase[P_FALLING];
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usb_cs_output = 1'b0;
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usb_cs_output = 1'b0;
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if (is_cmd_write) begin
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if (is_cmd_tx_force) begin
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usb_miosi_output_data = nibble_counter[0] ? C_FORCE[3:0] : C_FORCE[7:4];
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end else if (is_cmd_write) begin
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usb_miosi_output_data = nibble_counter[0] ? C_WRITE[3:0] : C_WRITE[7:4];
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usb_miosi_output_data = nibble_counter[0] ? C_WRITE[3:0] : C_WRITE[7:4];
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end else begin
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end else begin
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usb_miosi_output_data = nibble_counter[0] ? C_READ[3:0] : C_READ[7:4];
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usb_miosi_output_data = nibble_counter[0] ? C_READ[3:0] : C_READ[7:4];
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@ -202,12 +208,18 @@ module usb_ft1248 (
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if (sys.reset || !usb_enabled) begin
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if (sys.reset || !usb_enabled) begin
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state <= S_TRY_RX;
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state <= S_TRY_RX;
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tx_force_pending <= 1'b0;
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end else begin
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end else begin
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if (tx_force) begin
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tx_force_pending <= 1'b1;
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end
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case (state)
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case (state)
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S_TRY_RX: begin
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S_TRY_RX: begin
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if (!rx_full && !rx_escape_valid) begin
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if (!rx_full && !rx_escape_valid) begin
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state <= S_COMMAND;
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state <= S_COMMAND;
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is_cmd_write <= 1'b0;
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is_cmd_write <= 1'b0;
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is_cmd_tx_force <= 1'b0;
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nibble_counter <= 2'b11;
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nibble_counter <= 2'b11;
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end else begin
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end else begin
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state <= S_TRY_TX;
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state <= S_TRY_TX;
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@ -218,6 +230,13 @@ module usb_ft1248 (
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if (!tx_empty) begin
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if (!tx_empty) begin
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state <= S_COMMAND;
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state <= S_COMMAND;
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is_cmd_write <= 1'b1;
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is_cmd_write <= 1'b1;
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is_cmd_tx_force <= 1'b0;
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nibble_counter <= 2'b11;
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end else if (tx_force_pending) begin
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state <= S_COMMAND;
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tx_force_pending <= 1'b0;
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is_cmd_write <= 1'b1;
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is_cmd_tx_force <= 1'b1;
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nibble_counter <= 2'b11;
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nibble_counter <= 2'b11;
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end else begin
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end else begin
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state <= S_TRY_RX;
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state <= S_TRY_RX;
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@ -227,7 +246,7 @@ module usb_ft1248 (
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S_COMMAND: begin
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S_COMMAND: begin
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if (clock_phase[P_RISING]) begin
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if (clock_phase[P_RISING]) begin
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if (nibble_counter == 2'd2) begin
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if (nibble_counter == 2'd2) begin
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if (usb_miso_input) begin
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if (usb_miso_input || is_cmd_tx_force) begin
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state <= is_cmd_write ? S_TRY_RX : S_TRY_TX;
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state <= is_cmd_write ? S_TRY_RX : S_TRY_TX;
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end else begin
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end else begin
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state <= S_DATA;
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state <= S_DATA;
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@ -1,7 +1,7 @@
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#include "vr4300.h"
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#include "vr4300.h"
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#define WATCHDOG_TIMEOUT (1 * (93750000UL / 2))
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#define WATCHDOG_TIMEOUT (5 * (93750000UL / 2))
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#define VECTOR_LOCATION (0xA0000000UL)
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#define VECTOR_LOCATION (0xA0000000UL)
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#define VECTOR_SIZE (0x80)
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#define VECTOR_SIZE (0x80)
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@ -276,7 +276,7 @@ void exception_fatal_handler (uint32_t exception_code, uint32_t interrupt_mask,
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if (exception_code == EXCEPTION_INTERRUPT) {
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if (exception_code == EXCEPTION_INTERRUPT) {
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if (interrupt_mask & INTERRUPT_MASK_TIMER) {
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if (interrupt_mask & INTERRUPT_MASK_TIMER) {
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exception_disable_watchdog();
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exception_disable_watchdog();
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exception_print("Still loading after 1 second limit...\n\n");
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exception_print("Still loading after 5 second limit...\n\n");
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return;
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return;
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}
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}
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} else if (exception_code == EXCEPTION_SYSCALL) {
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} else if (exception_code == EXCEPTION_SYSCALL) {
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@ -105,6 +105,7 @@ typedef volatile struct usb_regs {
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#define USB_SCR_PWREN (1 << 5)
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#define USB_SCR_PWREN (1 << 5)
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#define USB_SCR_ESCAPE_PENDING (1 << 6)
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#define USB_SCR_ESCAPE_PENDING (1 << 6)
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#define USB_SCR_ESCAPE_ACK (1 << 7)
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#define USB_SCR_ESCAPE_ACK (1 << 7)
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#define USB_SCR_FORCE_TX (1 << 8)
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typedef volatile struct uart_regs {
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typedef volatile struct uart_regs {
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@ -252,6 +252,9 @@ void process_usb (void) {
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}
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}
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}
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}
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p.state = STATE_IDLE;
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p.state = STATE_IDLE;
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if (p.cmd == 'L') {
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USB->SCR |= USB_SCR_FORCE_TX;
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}
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} else {
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} else {
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p.state = STATE_RESPONSE;
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p.state = STATE_RESPONSE;
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}
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}
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@ -303,6 +306,7 @@ void process_usb (void) {
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case STATE_RESPONSE:
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case STATE_RESPONSE:
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if (tx_word((p.error ? USB_ERR_TOKEN : USB_CMP_TOKEN) | p.cmd)) {
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if (tx_word((p.error ? USB_ERR_TOKEN : USB_CMP_TOKEN) | p.cmd)) {
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p.state = STATE_IDLE;
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p.state = STATE_IDLE;
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USB->SCR |= USB_SCR_FORCE_TX;
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}
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}
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break;
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break;
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@ -327,6 +331,7 @@ void process_usb (void) {
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}
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}
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p.event_pending = false;
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p.event_pending = false;
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p.state = STATE_IDLE;
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p.state = STATE_IDLE;
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USB->SCR |= USB_SCR_FORCE_TX;
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}
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}
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break;
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break;
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}
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}
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