joybus rtc side sorted out

fw/SummerCart64.qsf

@@ -19,7 +19,7 @@
 #
 # Quartus Prime
 # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 02:09:23  August 29, 2021
+# Date created = 00:28:50  September 07, 2021
 #
 # -------------------------------------------------------------------------- #
 #
@@ -86,6 +86,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
 set_global_assignment -name SIGNALTAP_FILE output_files/signaltap.stp
+set_global_assignment -name SLD_FILE db/signaltap_auto_stripped.stp
 
 # Pin & Location Assignments
 # ==========================
@@ -304,6 +305,7 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_usb_miso
 		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
@@ -328,5 +330,3 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 # end ENTITY(intel_gpio_ddro)
 # ---------------------------
-set_global_assignment -name SLD_FILE db/signaltap_auto_stripped.stp
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

sw/riscv/src/controller.c

@@ -6,8 +6,15 @@
 static e_cfg_save_type_t save_type = CFG_SAVE_TYPE_NONE;
 static uint16_t cic_seed = 0xFFFF;
 static uint8_t tv_type = 0xFF;
+
 static bool eeprom_enabled = false;
 
+static bool rtc_running = true;
+static uint8_t rtc_wp_bits = SI_RTC_WP_MASK;
+static uint8_t current_time[7];
+static uint8_t new_time[7];
+static bool new_time_pending = false;
+
 static bool n64_to_pc_pending = false;
 static uint32_t n64_to_pc_address;
 static uint32_t n64_to_pc_length;
@@ -17,10 +24,13 @@ static uint32_t pc_to_n64_arg;
 static uint32_t pc_to_n64_address;
 static uint32_t pc_to_n64_length;
 
+
 void process_usb (void);
 void process_cfg (void);
 void process_flashram (void);
 void process_si (void);
+void process_rtc (void);
+
 
 bool debug_decide (uint32_t *args);
 void config_update (uint32_t *args);
@@ -28,8 +38,7 @@ void config_query (uint32_t *args);
 
 
 void main (void) {
-    UART->DR = 'X';
+    GPIO->ODR = 0x00;
-    GPIO->ODR = 0;
     GPIO->OER = (1 << 0);
 
     dma_abort();
@@ -42,11 +51,20 @@ void main (void) {
     cfg_set_dd_offset(CFG_DEFAULT_DD_OFFSET);
     cfg_set_cpu_ready(true);
 
+    current_time[0] = 0x10;
+    current_time[1] = 0x30;
+    current_time[2] = 0x90;
+    current_time[3] = 0x06;
+    current_time[4] = 0x01;
+    current_time[5] = 0x09;
+    current_time[6] = 0x21;
+
     while (1) {
         process_usb();
         process_cfg();
         process_flashram();
         process_si();
+        process_rtc();
     }
 }
 
@@ -220,8 +238,8 @@ void process_flashram (void) {
 }
 
 void process_si (void) {
-    uint8_t rx_data[10];
+    uint8_t rx_data[12];
-    uint8_t tx_data[10];
+    uint8_t tx_data[12];
     uint32_t *save_data;
     uint32_t *data_offset;
 
@@ -229,27 +247,29 @@ void process_si (void) {
         if (si_rx_stop_bit()) {
             si_rx(rx_data);
 
+            for (size_t i = 0; i < sizeof(tx_data); i++) {
+                tx_data[i] = 0x00;
+            }
+
             if (eeprom_enabled) {
                 save_data = (uint32_t *) (SDRAM_BASE + cfg_get_save_offset() + (rx_data[1] * 8));
-
                 switch (rx_data[0]) {
                     case SI_CMD_EEPROM_STATUS:
-                        tx_data[0] = 0x00;
                         tx_data[1] = save_type == CFG_SAVE_TYPE_EEPROM_4K ? SI_EEPROM_ID_4K : SI_EEPROM_ID_16K;
-                        tx_data[2] = 0x00;
                         si_tx(tx_data, 3);
                         break;
+
                     case SI_CMD_EEPROM_READ:
                         data_offset = (uint32_t *) (&tx_data[0]);
                         data_offset[0] = swapb(save_data[0]);
                         data_offset[1] = swapb(save_data[1]);
                         si_tx(tx_data, 8);
                         break;
+
                     case SI_CMD_EEPROM_WRITE:
                         data_offset = (uint32_t *) (&rx_data[2]);
                         save_data[0] = swapb(data_offset[0]);
                         save_data[1] = swapb(data_offset[1]);
-                        tx_data[0] = 0x00;
                         si_tx(tx_data, 1);
                         break;
                 }
@@ -257,36 +277,43 @@ void process_si (void) {
 
             switch (rx_data[0]) {
                 case SI_CMD_RTC_STATUS:
-                    tx_data[0] = 0x00;
+                    tx_data[1] = SI_RTC_ID;
-                    tx_data[1] = 0x10;
+                    tx_data[2] = SI_RTC_STATUS(rtc_running);
-                    tx_data[2] = 0x00;
                     si_tx(tx_data, 3);
                     break;
+
                 case SI_CMD_RTC_READ:
                     if (rx_data[1] == 0) {
-                        tx_data[0] = 0x03;
+                        tx_data[0] = rtc_wp_bits;
-                        tx_data[1] = 0x00;
+                        if (!rtc_running) {
-                        tx_data[2] = 0x00;
+                            tx_data[1] = SI_RTC_ST_MASK;
-                        tx_data[3] = 0x00;
-                        tx_data[4] = 0x00;
-                        tx_data[5] = 0x00;
-                        tx_data[6] = 0x00;
-                        tx_data[7] = 0x00;
-                    } else {
-                        tx_data[0] = 0x00;
-                        tx_data[1] = 0x00;
-                        tx_data[2] = 0x92;
-                        tx_data[3] = 0x06;
-                        tx_data[4] = 0x01;
-                        tx_data[5] = 0x09;
-                        tx_data[6] = 0x21;
-                        tx_data[7] = 0x01;
                         }
-                    tx_data[8] = 0x00;
+                    } else if (rx_data[1] == 1) {
+                        // Backup SRAM
+                    } else {
+                        for (size_t i = 0; i < 7; i++) {
+                            tx_data[i] = current_time[i];
+                        }
+                        tx_data[2] |= 0x80;
+                        tx_data[7] = SI_RTC_CENTURY_20XX;
+                    }
+                    tx_data[8] = SI_RTC_STATUS(rtc_running);
                     si_tx(tx_data, 9);
                     break;
+
                 case SI_CMD_RTC_WRITE:
-                    tx_data[0] = 0x00;
+                    if (rx_data[1] == 0) {
+                        rtc_wp_bits = rx_data[2] & SI_RTC_WP_MASK;
+                        rtc_running = (!(rx_data[3] & SI_RTC_ST_MASK));
+                    } else if (rx_data[1] == 1) {
+                        // Backup SRAM
+                    } else {
+                        for (size_t i = 0; i < 7; i++) {
+                            new_time[i] = rx_data[i + 2];
+                        }
+                        new_time_pending = !rtc_running;
+                    }
+                    tx_data[0] = SI_RTC_STATUS(rtc_running);
                     si_tx(tx_data, 1);
                     break;
             }
@@ -296,6 +323,16 @@ void process_si (void) {
     }
 }
 
+void process_rtc (void) {
+    if (new_time_pending) {
+        for (int i = 0; i < 7; i++) {
+            current_time[i] = new_time[i];
+        }
+        new_time_pending = false;
+    }
+}
+
+
 bool debug_decide (uint32_t *args) {
     switch (args[0]) {
         case DEBUG_WRITE_ADDRESS:

sw/riscv/src/driver.c

@@ -295,6 +295,34 @@ void si_tx (uint8_t *data, size_t length) {
 }
 
 
+// I2C
+
+bool i2c_busy (void) {
+    return I2C->SCR & I2C_SCR_BUSY;
+}
+
+bool i2c_ack (void) {
+    return I2C->SCR & I2C_SCR_ACK;
+}
+
+void i2c_start (void) {
+    I2C->SCR = I2C_SCR_START;
+}
+
+void i2c_stop (void) {
+    I2C->SCR = I2C_SCR_STOP;
+}
+
+void i2c_begin_trx (uint8_t data, bool mack) {
+    I2C->SCR = mack ? I2C_SCR_MACK : 0;
+    I2C->DR = data;
+}
+
+uint8_t i2c_get_data (void) {
+    return I2C->DR;
+}
+
+
 // misc
 
 const char hex_char_map[16] = {

sw/riscv/src/driver.h

@@ -104,6 +104,16 @@ void cfg_set_response (uint32_t *args, bool error);
 #define SI_EEPROM_ID_4K             (0x80)
 #define SI_EEPROM_ID_16K            (0xC0)
 
+#define SI_RTC_ID                   (0x10)
+
+#define SI_RTC_STATUS_STOPPED       (0x80)
+#define SI_RTC_STATUS_RUNNING       (0x00)
+#define SI_RTC_STATUS(running)      (running ? SI_RTC_STATUS_RUNNING : SI_RTC_STATUS_STOPPED)
+
+#define SI_RTC_WP_MASK              (0x03)
+#define SI_RTC_ST_MASK              (0x04)
+#define SI_RTC_CENTURY_20XX         (0x01)
+
 bool si_rx_ready (void);
 bool si_rx_stop_bit (void);
 bool si_tx_busy (void);
@@ -113,6 +123,16 @@ void si_rx (uint8_t *data);
 void si_tx (uint8_t *data, size_t length);
 
 
+// I2C
+
+bool i2c_busy (void);
+bool i2c_ack (void);
+void i2c_start (void);
+void i2c_stop (void);
+void i2c_begin_trx (uint8_t data, bool mack);
+uint8_t i2c_get_data (void);
+
+
 // misc
 
 void print (const char *text);