From 470b61aad9592f3679a334e5aacb28b9fbe1b7b9 Mon Sep 17 00:00:00 2001 From: Polprzewodnikowy Date: Mon, 18 Jul 2022 21:15:19 +0200 Subject: [PATCH] pre DMA rewrite, created dedicated buffer memory space, simplified code --- fw/project/lcmxo2/sc64.ldf | 7 +- fw/project/lcmxo2/sc64.sty | 4 +- fw/rtl/mcu/mcu_top.sv | 50 +--------- fw/rtl/memory/memory_arbiter.sv | 146 +++++++++++++++++++++-------- fw/rtl/memory/memory_bram.sv | 157 ++++++++++++++++++++++++++++++++ fw/rtl/memory/memory_flash.sv | 1 - fw/rtl/n64/n64_flashram.sv | 16 ++-- fw/rtl/n64/n64_pi.sv | 16 ++-- fw/rtl/n64/n64_reg_bus.sv | 28 +++--- fw/rtl/n64/n64_scb.sv | 122 +++++++++++++++---------- fw/rtl/n64/n64_si.sv | 20 +--- fw/rtl/top.sv | 48 ++++++---- sw/controller/src/flashram.c | 7 +- sw/controller/src/fpga.c | 33 ------- sw/controller/src/fpga.h | 8 +- sw/controller/src/usb.c | 30 ------ sw/pc/sc64.py | 61 +++---------- 17 files changed, 430 insertions(+), 324 deletions(-) create mode 100644 fw/rtl/memory/memory_bram.sv diff --git a/fw/project/lcmxo2/sc64.ldf b/fw/project/lcmxo2/sc64.ldf index 3eb7e40..bfead05 100644 --- a/fw/project/lcmxo2/sc64.ldf +++ b/fw/project/lcmxo2/sc64.ldf @@ -2,7 +2,7 @@ - + @@ -21,6 +21,9 @@ + + + @@ -63,7 +66,7 @@ - + diff --git a/fw/project/lcmxo2/sc64.sty b/fw/project/lcmxo2/sc64.sty index ee5086b..a5746dd 100644 --- a/fw/project/lcmxo2/sc64.sty +++ b/fw/project/lcmxo2/sc64.sty @@ -103,7 +103,7 @@ - + @@ -172,7 +172,7 @@ - + diff --git a/fw/rtl/mcu/mcu_top.sv b/fw/rtl/mcu/mcu_top.sv index 594b644..d334a4e 100644 --- a/fw/rtl/mcu/mcu_top.sv +++ b/fw/rtl/mcu/mcu_top.sv @@ -75,10 +75,7 @@ module mcu_top ( CMD_MEM_WRITE, CMD_USB_STATUS, CMD_USB_READ, - CMD_USB_WRITE, - CMD_FLASHRAM_READ, - CMD_EEPROM_READ, - CMD_EEPROM_WRITE + CMD_USB_WRITE } cmd_e; phase_e phase; @@ -102,8 +99,6 @@ module mcu_top ( fifo_bus.rx_read <= 1'b0; fifo_bus.tx_write <= 1'b0; - n64_scb.eeprom_write <= 1'b0; - reg_read <= 1'b0; reg_write <= 1'b0; @@ -121,10 +116,6 @@ module mcu_top ( address <= address + 1'd1; end - if (n64_scb.eeprom_write) begin - n64_scb.eeprom_address <= n64_scb.eeprom_address + 1'd1; - end - if (data_ready) begin case (phase) PHASE_CMD: begin @@ -157,15 +148,6 @@ module mcu_top ( mem_read <= 1'b1; mem_word_select <= 1'b0; end - - if (cmd == CMD_FLASHRAM_READ) begin - n64_scb.flashram_buffer_address <= rdata[6:1]; - counter <= {1'b0, rdata[0]}; - end - - if ((cmd == CMD_EEPROM_READ) || (cmd == CMD_EEPROM_WRITE)) begin - n64_scb.eeprom_address <= {rdata, 3'd0}; - end end PHASE_DATA: begin @@ -216,21 +198,6 @@ module mcu_top ( fifo_bus.tx_wdata <= rdata; phase <= PHASE_NOP; end - - if (cmd == CMD_FLASHRAM_READ) begin - if (counter[0]) begin - n64_scb.flashram_buffer_address <= n64_scb.flashram_buffer_address + 1'd1; - end - end - - if (cmd == CMD_EEPROM_READ) begin - n64_scb.eeprom_address <= n64_scb.eeprom_address + 1'd1; - end - - if (cmd == CMD_EEPROM_WRITE) begin - n64_scb.eeprom_write <= 1'b1; - n64_scb.eeprom_wdata <= rdata; - end end PHASE_NOP: begin end @@ -282,21 +249,6 @@ module mcu_top ( CMD_USB_WRITE: begin wdata = 8'h00; end - - CMD_FLASHRAM_READ: begin - case (counter[0]) - 1'd0: wdata = n64_scb.flashram_buffer_rdata[15:8]; - 1'd1: wdata = n64_scb.flashram_buffer_rdata[7:0]; - endcase - end - - CMD_EEPROM_READ: begin - wdata = n64_scb.eeprom_rdata; - end - - CMD_EEPROM_WRITE: begin - wdata = 8'h00; - end endcase end diff --git a/fw/rtl/memory/memory_arbiter.sv b/fw/rtl/memory/memory_arbiter.sv index 0b0453a..6df15e3 100644 --- a/fw/rtl/memory/memory_arbiter.sv +++ b/fw/rtl/memory/memory_arbiter.sv @@ -5,38 +5,49 @@ module memory_arbiter ( mem_bus.memory n64_bus, mem_bus.memory cfg_bus, mem_bus.memory usb_dma_bus, - mem_bus.memory sd_dma_bus, + // mem_bus.memory sd_dma_bus, mem_bus.controller sdram_mem_bus, - mem_bus.controller flash_mem_bus + mem_bus.controller flash_mem_bus, + mem_bus.controller bram_mem_bus ); typedef enum bit [1:0] { SOURCE_N64, SOURCE_CFG, - SOURCE_USB_DMA, - SOURCE_SD_DMA + SOURCE_USB_DMA//, + // SOURCE_SD_DMA } e_source_request; logic n64_sdram_request; logic cfg_sdram_request; logic usb_dma_sdram_request; - logic sd_dma_sdram_request; + // logic sd_dma_sdram_request; logic n64_flash_request; logic cfg_flash_request; logic usb_dma_flash_request; - logic sd_dma_flash_request; + // logic sd_dma_flash_request; + + logic n64_bram_request; + logic cfg_bram_request; + logic usb_dma_bram_request; + // logic sd_dma_bram_request; assign n64_sdram_request = n64_bus.request && !n64_bus.address[26]; assign cfg_sdram_request = cfg_bus.request && !cfg_bus.address[26]; assign usb_dma_sdram_request = usb_dma_bus.request && !usb_dma_bus.address[26]; - assign sd_dma_sdram_request = sd_dma_bus.request && !sd_dma_bus.address[26]; + // assign sd_dma_sdram_request = sd_dma_bus.request && !sd_dma_bus.address[26]; - assign n64_flash_request = n64_bus.request && n64_bus.address[26]; - assign cfg_flash_request = cfg_bus.request && cfg_bus.address[26]; - assign usb_dma_flash_request = usb_dma_bus.request && usb_dma_bus.address[26]; - assign sd_dma_flash_request = sd_dma_bus.request && sd_dma_bus.address[26]; + assign n64_flash_request = n64_bus.request && (n64_bus.address[26:25] == 2'b10); + assign cfg_flash_request = cfg_bus.request && (cfg_bus.address[26:25] == 2'b10); + assign usb_dma_flash_request = usb_dma_bus.request && (usb_dma_bus.address[26:25] == 2'b10); + // assign sd_dma_flash_request = sd_dma_bus.request && (sd_dma_bus.address[26:25] == 2'b10); + + assign n64_bram_request = n64_bus.request && (n64_bus.address[26:25] == 2'b11); + assign cfg_bram_request = cfg_bus.request && (cfg_bus.address[26:25] == 2'b11); + assign usb_dma_bram_request = usb_dma_bus.request && (usb_dma_bus.address[26:25] == 2'b11); + // assign sd_dma_bram_request = sd_dma_bus.request && (sd_dma_bus.address[26:25] == 2'b11); e_source_request sdram_source_request; @@ -48,8 +59,8 @@ module memory_arbiter ( sdram_mem_bus.request <= ( n64_sdram_request || cfg_sdram_request || - usb_dma_sdram_request || - sd_dma_sdram_request + usb_dma_sdram_request// || + // sd_dma_sdram_request ); if (n64_sdram_request) begin @@ -70,12 +81,12 @@ module memory_arbiter ( sdram_mem_bus.address <= usb_dma_bus.address; sdram_mem_bus.wdata <= usb_dma_bus.wdata; sdram_source_request <= SOURCE_USB_DMA; - end else if (sd_dma_sdram_request) begin - sdram_mem_bus.write <= sd_dma_bus.write; - sdram_mem_bus.wmask <= sd_dma_bus.wmask; - sdram_mem_bus.address <= sd_dma_bus.address; - sdram_mem_bus.wdata <= sd_dma_bus.wdata; - sdram_source_request <= SOURCE_SD_DMA; + // end else if (sd_dma_sdram_request) begin + // sdram_mem_bus.write <= sd_dma_bus.write; + // sdram_mem_bus.wmask <= sd_dma_bus.wmask; + // sdram_mem_bus.address <= sd_dma_bus.address; + // sdram_mem_bus.wdata <= sd_dma_bus.wdata; + // sdram_source_request <= SOURCE_SD_DMA; end end @@ -95,8 +106,8 @@ module memory_arbiter ( flash_mem_bus.request <= ( n64_flash_request || cfg_flash_request || - usb_dma_flash_request || - sd_dma_flash_request + usb_dma_flash_request// || + // sd_dma_flash_request ); if (n64_flash_request) begin @@ -117,12 +128,12 @@ module memory_arbiter ( flash_mem_bus.address <= usb_dma_bus.address; flash_mem_bus.wdata <= usb_dma_bus.wdata; flash_source_request <= SOURCE_USB_DMA; - end else if (sd_dma_flash_request) begin - flash_mem_bus.write <= sd_dma_bus.write; - flash_mem_bus.wmask <= sd_dma_bus.wmask; - flash_mem_bus.address <= sd_dma_bus.address; - flash_mem_bus.wdata <= sd_dma_bus.wdata; - flash_source_request <= SOURCE_SD_DMA; + // end else if (sd_dma_flash_request) begin + // flash_mem_bus.write <= sd_dma_bus.write; + // flash_mem_bus.wmask <= sd_dma_bus.wmask; + // flash_mem_bus.address <= sd_dma_bus.address; + // flash_mem_bus.wdata <= sd_dma_bus.wdata; + // flash_source_request <= SOURCE_SD_DMA; end end @@ -132,28 +143,87 @@ module memory_arbiter ( end end + e_source_request bram_source_request; + + always_ff @(posedge clk) begin + if (reset) begin + bram_mem_bus.request <= 1'b0; + end else begin + if (!bram_mem_bus.request) begin + bram_mem_bus.request <= ( + n64_bram_request || + cfg_bram_request || + usb_dma_bram_request// || + // sd_dma_bram_request + ); + + if (n64_bram_request) begin + bram_mem_bus.write <= n64_bus.write; + bram_mem_bus.wmask <= n64_bus.wmask; + bram_mem_bus.address <= n64_bus.address; + bram_mem_bus.wdata <= n64_bus.wdata; + bram_source_request <= SOURCE_N64; + end else if (cfg_bram_request) begin + bram_mem_bus.write <= cfg_bus.write; + bram_mem_bus.wmask <= cfg_bus.wmask; + bram_mem_bus.address <= cfg_bus.address; + bram_mem_bus.wdata <= cfg_bus.wdata; + bram_source_request <= SOURCE_CFG; + end else if (usb_dma_bram_request) begin + bram_mem_bus.write <= usb_dma_bus.write; + bram_mem_bus.wmask <= usb_dma_bus.wmask; + bram_mem_bus.address <= usb_dma_bus.address; + bram_mem_bus.wdata <= usb_dma_bus.wdata; + bram_source_request <= SOURCE_USB_DMA; + // end else if (sd_dma_bram_request) begin + // bram_mem_bus.write <= sd_dma_bus.write; + // bram_mem_bus.wmask <= sd_dma_bus.wmask; + // bram_mem_bus.address <= sd_dma_bus.address; + // bram_mem_bus.wdata <= sd_dma_bus.wdata; + // bram_source_request <= SOURCE_SD_DMA; + end + end + + if (bram_mem_bus.ack) begin + bram_mem_bus.request <= 1'b0; + end + end + end + always_comb begin n64_bus.ack = ( ((sdram_source_request == SOURCE_N64) && sdram_mem_bus.ack) || - ((flash_source_request == SOURCE_N64) && flash_mem_bus.ack) + ((flash_source_request == SOURCE_N64) && flash_mem_bus.ack) || + ((bram_source_request == SOURCE_N64) && bram_mem_bus.ack) ); cfg_bus.ack = ( ((sdram_source_request == SOURCE_CFG) && sdram_mem_bus.ack) || - ((flash_source_request == SOURCE_CFG) && flash_mem_bus.ack) + ((flash_source_request == SOURCE_CFG) && flash_mem_bus.ack) || + ((bram_source_request == SOURCE_CFG) && bram_mem_bus.ack) ); usb_dma_bus.ack = ( ((sdram_source_request == SOURCE_USB_DMA) && sdram_mem_bus.ack) || - ((flash_source_request == SOURCE_USB_DMA) && flash_mem_bus.ack) - ); - sd_dma_bus.ack = ( - ((sdram_source_request == SOURCE_SD_DMA) && sdram_mem_bus.ack) || - ((flash_source_request == SOURCE_SD_DMA) && flash_mem_bus.ack) + ((flash_source_request == SOURCE_USB_DMA) && flash_mem_bus.ack) || + ((bram_source_request == SOURCE_USB_DMA) && bram_mem_bus.ack) ); + // sd_dma_bus.ack = ( + // ((sdram_source_request == SOURCE_SD_DMA) && sdram_mem_bus.ack) || + // ((flash_source_request == SOURCE_SD_DMA) && flash_mem_bus.ack) || + // ((bram_source_request == SOURCE_SD_DMA) && bram_mem_bus.ack) + // ); - n64_bus.rdata = n64_flash_request ? flash_mem_bus.rdata : sdram_mem_bus.rdata; - cfg_bus.rdata = cfg_flash_request ? flash_mem_bus.rdata : sdram_mem_bus.rdata; - usb_dma_bus.rdata = usb_dma_flash_request ? flash_mem_bus.rdata : sdram_mem_bus.rdata; - sd_dma_bus.rdata = sd_dma_flash_request ? flash_mem_bus.rdata : sdram_mem_bus.rdata; + n64_bus.rdata = n64_bram_request ? bram_mem_bus.rdata : + n64_flash_request ? flash_mem_bus.rdata : + sdram_mem_bus.rdata; + cfg_bus.rdata = cfg_bram_request ? bram_mem_bus.rdata : + cfg_flash_request ? flash_mem_bus.rdata : + sdram_mem_bus.rdata; + usb_dma_bus.rdata = usb_dma_bram_request ? bram_mem_bus.rdata : + usb_dma_flash_request ? flash_mem_bus.rdata : + sdram_mem_bus.rdata; + // sd_dma_bus.rdata = sd_dma_bram_request ? bram_mem_bus.rdata : + // sd_dma_flash_request ? flash_mem_bus.rdata : + // sdram_mem_bus.rdata; end endmodule diff --git a/fw/rtl/memory/memory_bram.sv b/fw/rtl/memory/memory_bram.sv new file mode 100644 index 0000000..9505e17 --- /dev/null +++ b/fw/rtl/memory/memory_bram.sv @@ -0,0 +1,157 @@ +module memory_bram ( + input clk, + + n64_scb.bram n64_scb, + + mem_bus.memory mem_bus +); + + // Request logic + + logic [1:0] last_request; + logic write; + + always_ff @(posedge clk) begin + last_request <= {last_request[0], mem_bus.request}; + end + + always_ff @(posedge clk) begin + mem_bus.ack <= mem_bus.request && last_request[0] && !last_request[1]; + end + + always_comb begin + write = mem_bus.request && !last_request[0] && mem_bus.write; + end + + + // Address decoding + + logic buffer_selected; + logic eeprom_selected; + logic flashram_selected; + logic dd_selected; + + always_comb begin + buffer_selected = mem_bus.address[14:13] == 2'b00; + eeprom_selected = mem_bus.address[14:13] == 2'b01; + flashram_selected = mem_bus.address[14:13] == 2'b10; + dd_selected = mem_bus.address[14:13] == 2'b11; + end + + + // Buffer memory + + logic [15:0] buffer_bram [0:4095]; + logic [15:0] buffer_bram_rdata; + + always_ff @(posedge clk) begin + if (write && buffer_selected) begin + buffer_bram[mem_bus.address[12:1]] <= mem_bus.wdata; + end + end + + always_ff @(posedge clk) begin + buffer_bram_rdata <= buffer_bram[mem_bus.address[12:1]]; + end + + + // EEPROM memory + + logic [7:0] eeprom_bram_high [0:1023]; + logic [7:0] eeprom_bram_low [0:1023]; + logic [7:0] eeprom_bram_high_rdata; + logic [7:0] eeprom_bram_low_rdata; + logic [7:0] eeprom_bram_high_n64_rdata; + logic [7:0] eeprom_bram_low_n64_rdata; + logic [15:0] eeprom_bram_rdata; + + always_ff @(posedge clk) begin + if (write && eeprom_selected) begin + eeprom_bram_high[mem_bus.address[10:1]] <= mem_bus.wdata[15:8]; + end + if (n64_scb.eeprom_write && !n64_scb.eeprom_address[0]) begin + eeprom_bram_high[n64_scb.eeprom_address[10:1]] <= n64_scb.eeprom_wdata; + end + end + + always_ff @(posedge clk) begin + if (write && eeprom_selected) begin + eeprom_bram_low[mem_bus.address[10:1]] <= mem_bus.wdata[7:0]; + end + if (n64_scb.eeprom_write && n64_scb.eeprom_address[0]) begin + eeprom_bram_low[n64_scb.eeprom_address[10:1]] <= n64_scb.eeprom_wdata; + end + end + + always_ff @(posedge clk) begin + eeprom_bram_high_rdata <= eeprom_bram_high[mem_bus.address[10:1]]; + end + + always_ff @(posedge clk) begin + eeprom_bram_low_rdata <= eeprom_bram_low[mem_bus.address[10:1]]; + end + + always_ff @(posedge clk) begin + eeprom_bram_high_n64_rdata <= eeprom_bram_high[n64_scb.eeprom_address[10:1]]; + end + + always_ff @(posedge clk) begin + eeprom_bram_low_n64_rdata <= eeprom_bram_low[n64_scb.eeprom_address[10:1]]; + end + + always_comb begin + eeprom_bram_rdata = {eeprom_bram_high_rdata, eeprom_bram_low_rdata}; + n64_scb.eeprom_rdata = n64_scb.eeprom_address[0] ? eeprom_bram_low_n64_rdata : eeprom_bram_high_n64_rdata; + end + + + // FlashRAM memory + + logic [15:0] flashram_bram [0:63]; + logic [15:0] flashram_bram_rdata; + + always_ff @(posedge clk) begin + if (n64_scb.flashram_write) begin + flashram_bram[n64_scb.flashram_address] <= n64_scb.flashram_wdata; + end + end + + always_ff @(posedge clk) begin + flashram_bram_rdata <= flashram_bram[mem_bus.address[6:1]]; + end + + + // DD memory + + logic [15:0] dd_bram [0:511]; + logic [15:0] dd_bram_rdata; + + always_ff @(posedge clk) begin + if (write && dd_selected) begin + dd_bram[mem_bus.address[9:1]] <= mem_bus.wdata; + end + if (n64_scb.dd_write) begin + dd_bram[n64_scb.dd_address] <= n64_scb.dd_wdata; + end + end + + always_ff @(posedge clk) begin + dd_bram_rdata <= dd_bram[mem_bus.address[9:1]]; + end + + always_ff @(posedge clk) begin + n64_scb.dd_rdata <= dd_bram[n64_scb.dd_address]; + end + + + // Output data mux + + always_ff @(posedge clk) begin + mem_bus.rdata <= 16'd0; + if (buffer_selected) mem_bus.rdata <= buffer_bram_rdata; + if (eeprom_selected) mem_bus.rdata <= eeprom_bram_rdata; + if (flashram_selected) mem_bus.rdata <= flashram_bram_rdata; + if (dd_selected) mem_bus.rdata <= dd_bram_rdata; + end + +endmodule diff --git a/fw/rtl/memory/memory_flash.sv b/fw/rtl/memory/memory_flash.sv index 007e06a..5d3abfc 100644 --- a/fw/rtl/memory/memory_flash.sv +++ b/fw/rtl/memory/memory_flash.sv @@ -221,7 +221,6 @@ module memory_flash ( } e_state; e_state state; - e_state next_state; logic [2:0] counter; logic valid_counter; logic [23:0] current_address; diff --git a/fw/rtl/n64/n64_flashram.sv b/fw/rtl/n64/n64_flashram.sv index 79199c7..bbc9464 100644 --- a/fw/rtl/n64/n64_flashram.sv +++ b/fw/rtl/n64/n64_flashram.sv @@ -40,12 +40,6 @@ module n64_flashram ( logic [7:0] cmd; logic erase_enabled; - logic [15:0] write_buffer [0:63]; - - always_ff @(posedge clk) begin - n64_scb.flashram_buffer_rdata <= write_buffer[n64_scb.flashram_buffer_address]; - end - always_comb begin n64_scb.flashram_read_mode = (state == STATE_READ); @@ -140,9 +134,7 @@ module n64_flashram ( endcase end end else begin - if (state == STATE_BUFFER) begin - write_buffer[reg_bus.address[6:1]] <= reg_bus.wdata; - end else if (reg_bus.address[1]) begin + if (reg_bus.address[1] && state != STATE_BUFFER) begin status[ERASE_BUSY] <= reg_bus.wdata[ERASE_BUSY]; status[WRITE_BUSY] <= reg_bus.wdata[WRITE_BUSY]; end @@ -151,4 +143,10 @@ module n64_flashram ( end end + always_comb begin + n64_scb.flashram_write = reg_bus.write && !reg_bus.address[16] && state == STATE_BUFFER; + n64_scb.flashram_address = reg_bus.address[6:1]; + n64_scb.flashram_wdata = reg_bus.wdata; + end + endmodule diff --git a/fw/rtl/n64/n64_pi.sv b/fw/rtl/n64/n64_pi.sv index fb5b2cd..77120eb 100644 --- a/fw/rtl/n64/n64_pi.sv +++ b/fw/rtl/n64/n64_pi.sv @@ -125,11 +125,11 @@ module n64_pi ( // Address decoding const bit [31:0] DDIPL_OFFSET = 32'h03BC_0000; - const bit [31:0] SAVE_OFFSET = 32'h03FC_0000; - const bit [31:0] BUFFER_OFFSET = 32'h03FE_0000; + const bit [31:0] SAVE_OFFSET = 32'h03FE_0000; const bit [31:0] FLASH_OFFSET = 32'h0400_0000; const bit [31:0] BOOTLOADER_OFFSET = 32'h04E0_0000; - const bit [31:0] SHADOW_OFFSET = 32'h04FC_0000; + const bit [31:0] SHADOW_OFFSET = 32'h04FE_0000; + const bit [31:0] BUFFER_OFFSET = 32'h0600_0000; logic [31:0] mem_offset; @@ -207,10 +207,10 @@ module n64_pi ( end if (n64_scb.rom_shadow_enabled) begin - if (n64_pi_dq_in >= 16'h13FC && n64_pi_dq_in < 16'h1400) begin + if (n64_pi_dq_in >= 16'h13FE && n64_pi_dq_in < 16'h1400) begin read_port <= PORT_MEM; write_port <= PORT_NONE; - mem_offset <= (-32'h13FC_0000) + SHADOW_OFFSET; + mem_offset <= (-32'h13FE_0000) + SHADOW_OFFSET; end end @@ -220,13 +220,13 @@ module n64_pi ( mem_offset <= (-32'h1400_0000) + FLASH_OFFSET; end - if (n64_pi_dq_in >= 16'h1FFC && n64_pi_dq_in < 16'h1FFE) begin + if (n64_pi_dq_in >= 16'h1FFE && n64_pi_dq_in < 16'h1FFF) begin read_port <= PORT_MEM; write_port <= PORT_MEM; - mem_offset <= (-32'h1FFC_0000) + BUFFER_OFFSET; + mem_offset <= (-32'h1FFE_0000) + BUFFER_OFFSET; end - if (n64_pi_dq_in >= 16'h1FFE && n64_pi_dq_in < 16'h2000) begin + if (n64_pi_dq_in >= 16'h1FFF && n64_pi_dq_in < 16'h2000) begin read_port <= PORT_REG; write_port <= PORT_REG; reg_bus.cfg_select <= 1'b1; diff --git a/fw/rtl/n64/n64_reg_bus.sv b/fw/rtl/n64/n64_reg_bus.sv index 7e59f42..07573b7 100644 --- a/fw/rtl/n64/n64_reg_bus.sv +++ b/fw/rtl/n64/n64_reg_bus.sv @@ -1,7 +1,7 @@ interface n64_reg_bus (); - logic dd_select; logic flashram_select; + logic dd_select; logic cfg_select; logic read; @@ -10,13 +10,13 @@ interface n64_reg_bus (); logic [15:0] rdata; logic [15:0] wdata; - logic [15:0] dd_rdata; logic [15:0] flashram_rdata; + logic [15:0] dd_rdata; logic [15:0] cfg_rdata; modport controller ( - output dd_select, output flashram_select, + output dd_select, output cfg_select, output read, @@ -28,25 +28,17 @@ interface n64_reg_bus (); always_comb begin rdata = 16'd0; - if (dd_select) begin - rdata = dd_rdata; - end if (flashram_select) begin rdata = flashram_rdata; end + if (dd_select) begin + rdata = dd_rdata; + end if (cfg_select) begin rdata = cfg_rdata; end end - modport dd ( - input .read(read && dd_select), - input .write(write && dd_select), - input address, - output .rdata(dd_rdata), - input wdata - ); - modport flashram ( input .read(read && flashram_select), input .write(write && flashram_select), @@ -55,6 +47,14 @@ interface n64_reg_bus (); input wdata ); + modport dd ( + input .read(read && dd_select), + input .write(write && dd_select), + input address, + output .rdata(dd_rdata), + input wdata + ); + modport cfg ( input .read(read && cfg_select), input .write(write && cfg_select), diff --git a/fw/rtl/n64/n64_scb.sv b/fw/rtl/n64/n64_scb.sv index 17f0681..e3a11e0 100644 --- a/fw/rtl/n64/n64_scb.sv +++ b/fw/rtl/n64/n64_scb.sv @@ -9,28 +9,25 @@ interface n64_scb (); logic sram_enabled; logic sram_banked; logic flashram_enabled; - logic flashram_read_mode; logic dd_enabled; logic ddipl_enabled; logic eeprom_enabled; logic eeprom_16k_mode; + logic dd_write; + logic [8:0] dd_address; + logic [15:0] dd_rdata; + logic [15:0] dd_wdata; + logic flashram_pending; logic flashram_done; logic [9:0] flashram_sector; logic flashram_sector_or_all; logic flashram_write_or_erase; - logic [5:0] flashram_buffer_address; - logic [15:0] flashram_buffer_rdata; - - logic cfg_pending; - logic cfg_done; - logic cfg_error; - logic cfg_irq; - logic [7:0] cfg_cmd; - logic [31:0] cfg_rdata [0:1]; - logic [31:0] cfg_wdata [0:1]; - logic [31:0] cfg_version; + logic flashram_read_mode; + logic flashram_write; + logic [5:0] flashram_address; + logic [15:0] flashram_wdata; logic eeprom_write; logic [10:0] eeprom_address; @@ -42,6 +39,15 @@ interface n64_scb (); logic [41:0] rtc_rdata; logic [41:0] rtc_wdata; + logic cfg_pending; + logic cfg_done; + logic cfg_error; + logic cfg_irq; + logic [7:0] cfg_cmd; + logic [31:0] cfg_rdata [0:1]; + logic [31:0] cfg_wdata [0:1]; + logic [31:0] cfg_version; + modport controller ( input n64_reset, input n64_nmi, @@ -62,8 +68,11 @@ interface n64_scb (); input flashram_sector, input flashram_sector_or_all, input flashram_write_or_erase, - output flashram_buffer_address, - input flashram_buffer_rdata, + + input rtc_pending, + output rtc_done, + input rtc_rdata, + output rtc_wdata, input cfg_pending, output cfg_done, @@ -72,17 +81,7 @@ interface n64_scb (); input cfg_cmd, input cfg_rdata, output cfg_wdata, - output cfg_version, - - output eeprom_write, - output eeprom_address, - input eeprom_rdata, - output eeprom_wdata, - - input rtc_pending, - output rtc_done, - input rtc_rdata, - output rtc_wdata + output cfg_version ); modport pi ( @@ -95,25 +94,65 @@ interface n64_scb (); input sram_enabled, input sram_banked, input flashram_enabled, - input flashram_read_mode, input dd_enabled, - input ddipl_enabled - ); + input ddipl_enabled, - modport dd ( - input n64_reset, - input n64_nmi + input flashram_read_mode ); modport flashram ( - output flashram_read_mode, output flashram_pending, input flashram_done, output flashram_sector, output flashram_sector_or_all, output flashram_write_or_erase, - input flashram_buffer_address, - output flashram_buffer_rdata + + output flashram_read_mode, + + output flashram_write, + output flashram_address, + output flashram_wdata + ); + + modport si ( + input eeprom_enabled, + input eeprom_16k_mode, + + output eeprom_write, + output eeprom_address, + input eeprom_rdata, + output eeprom_wdata, + + output rtc_pending, + input rtc_done, + output rtc_rdata, + input rtc_wdata + ); + + modport dd ( + input n64_reset, + input n64_nmi, + + output dd_write, + output dd_address, + input dd_rdata, + output dd_wdata + ); + + modport bram ( + input flashram_write, + input flashram_address, + input flashram_wdata, + + input eeprom_write, + input eeprom_address, + output eeprom_rdata, + input eeprom_wdata, + + input dd_write, + input dd_address, + output dd_rdata, + input dd_wdata ); modport cfg ( @@ -127,19 +166,4 @@ interface n64_scb (); input cfg_version ); - modport si ( - input eeprom_enabled, - input eeprom_16k_mode, - - input eeprom_write, - input eeprom_address, - output eeprom_rdata, - input eeprom_wdata, - - output rtc_pending, - input rtc_done, - output rtc_rdata, - input rtc_wdata - ); - endinterface diff --git a/fw/rtl/n64/n64_si.sv b/fw/rtl/n64/n64_si.sv index abac4e3..a82c548 100644 --- a/fw/rtl/n64/n64_si.sv +++ b/fw/rtl/n64/n64_si.sv @@ -332,20 +332,10 @@ module n64_si ( // EEPROM controller - logic [7:0] eeprom_memory [0:2047]; - logic [7:0] eeprom_data; - - always_ff @(posedge clk) begin - eeprom_data <= eeprom_memory[joybus_full_address]; - n64_scb.eeprom_rdata <= eeprom_memory[n64_scb.eeprom_address]; - if (rx_data_valid && (cmd == CMD_EEPROM_WRITE)) begin - if (rx_byte_counter > 4'd0) begin - eeprom_memory[joybus_full_address] <= rx_byte_data; - end - end - if (n64_scb.eeprom_write) begin - eeprom_memory[n64_scb.eeprom_address] <= n64_scb.eeprom_wdata; - end + always_comb begin + n64_scb.eeprom_write = rx_data_valid && (cmd == CMD_EEPROM_WRITE) && rx_byte_counter > 4'd0; + n64_scb.eeprom_address = joybus_full_address; + n64_scb.eeprom_wdata = rx_byte_data; end @@ -439,7 +429,7 @@ module n64_si ( end CMD_EEPROM_READ: begin tx_length = 4'd7; - tx_byte_data = eeprom_data; + tx_byte_data = n64_scb.eeprom_rdata; end CMD_EEPROM_WRITE: begin tx_length = 4'd0; diff --git a/fw/rtl/top.sv b/fw/rtl/top.sv index d0031e1..97c9d1e 100644 --- a/fw/rtl/top.sv +++ b/fw/rtl/top.sv @@ -66,9 +66,10 @@ module top ( mem_bus n64_mem_bus (); mem_bus cfg_mem_bus (); mem_bus usb_dma_mem_bus (); - mem_bus sd_dma_mem_bus (); + // mem_bus sd_dma_mem_bus (); mem_bus sdram_mem_bus (); mem_bus flash_mem_bus (); + mem_bus bram_mem_bus (); pll pll_inst ( .inclk(inclk), @@ -166,28 +167,28 @@ module top ( // SD card - sd_top sd_top_inst ( - .clk(clk), - .reset(reset), + // sd_top sd_top_inst ( + // .clk(clk), + // .reset(reset), - .sd_scb(sd_scb), + // .sd_scb(sd_scb), - .fifo_bus(sd_fifo_bus), + // .fifo_bus(sd_fifo_bus), - .sd_clk(sd_clk), - .sd_cmd(sd_cmd), - .sd_dat(sd_dat) - ); + // .sd_clk(sd_clk), + // .sd_cmd(sd_cmd), + // .sd_dat(sd_dat) + // ); - memory_dma memory_sd_dma_inst ( - .clk(clk), - .reset(reset), + // memory_dma memory_sd_dma_inst ( + // .clk(clk), + // .reset(reset), - .dma_scb(sd_dma_scb), + // .dma_scb(sd_dma_scb), - .fifo_bus(sd_fifo_bus), - .mem_bus(sd_dma_mem_bus) - ); + // .fifo_bus(sd_fifo_bus), + // .mem_bus(sd_dma_mem_bus) + // ); // Memory bus arbiter @@ -199,10 +200,11 @@ module top ( .n64_bus(n64_mem_bus), .cfg_bus(cfg_mem_bus), .usb_dma_bus(usb_dma_mem_bus), - .sd_dma_bus(sd_dma_mem_bus), + // .sd_dma_bus(sd_dma_mem_bus), .sdram_mem_bus(sdram_mem_bus), - .flash_mem_bus(flash_mem_bus) + .flash_mem_bus(flash_mem_bus), + .bram_mem_bus(bram_mem_bus) ); @@ -237,4 +239,12 @@ module top ( .flash_dq(flash_dq) ); + memory_bram memory_bram_inst ( + .clk(clk), + + .n64_scb(n64_scb), + + .mem_bus(bram_mem_bus) + ); + endmodule diff --git a/sw/controller/src/flashram.c b/sw/controller/src/flashram.c index 04d5407..e0d6855 100644 --- a/sw/controller/src/flashram.c +++ b/sw/controller/src/flashram.c @@ -7,6 +7,9 @@ #define FLASHRAM_SECTOR_SIZE (16 * 1024) #define FLASHRAM_PAGE_SIZE (128) +#define FLASHRAM_OFFSET ((64 * 1024 * 1024) - (128 * 1024)) +#define FLASHRAM_BUFFER_OFFSET (((64 + 32) * 1024 * 1024) + ((8 + 8) * 1024)) + enum operation { OP_NONE, OP_ERASE_ALL, @@ -41,7 +44,7 @@ void flashram_process (void) { uint32_t scr = fpga_reg_get(REG_FLASHRAM_SCR); enum operation op = flashram_operation_type(scr); uint8_t buffer[FLASHRAM_PAGE_SIZE]; - uint32_t address = (64 * 1024 * 1024) - (256 * 1024); + uint32_t address = FLASHRAM_OFFSET; uint32_t erase_size = (op == OP_ERASE_SECTOR) ? FLASHRAM_SECTOR_SIZE : FLASHRAM_SIZE; uint32_t sector = (op != OP_ERASE_ALL) ? ((scr & FLASHRAM_SCR_PAGE_MASK) >> FLASHRAM_SCR_PAGE_BIT) : 0; address += sector * FLASHRAM_PAGE_SIZE; @@ -59,7 +62,7 @@ void flashram_process (void) { break; case OP_WRITE_PAGE: - fpga_flashram_buffer_read(buffer); + fpga_mem_read(FLASHRAM_BUFFER_OFFSET, FLASHRAM_PAGE_SIZE, buffer); fpga_mem_write(address, FLASHRAM_PAGE_SIZE, buffer); fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); break; diff --git a/sw/controller/src/fpga.c b/sw/controller/src/fpga.c index 87bd7ea..4182608 100644 --- a/sw/controller/src/fpga.c +++ b/sw/controller/src/fpga.c @@ -99,36 +99,3 @@ void fpga_usb_push (uint8_t data) { hw_spi_trx(&data, 1, SPI_TX); hw_spi_stop(); } - -void fpga_flashram_buffer_read (uint8_t *buffer) { - fpga_cmd_t cmd = CMD_FLASHRAM_READ; - uint8_t address = 0; - - hw_spi_start(); - hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); - hw_spi_trx(&address, 1, SPI_TX); - hw_spi_trx(buffer, 128, SPI_RX); - hw_spi_stop(); -} - -void fpga_eeprom_read (uint16_t address, size_t length, uint8_t *buffer) { - fpga_cmd_t cmd = CMD_EEPROM_READ; - uint8_t adjusted_address = ((address >> 3) & 0xFF); - - hw_spi_start(); - hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); - hw_spi_trx(&adjusted_address, 1, SPI_TX); - hw_spi_trx(buffer, length, SPI_RX); - hw_spi_stop(); -} - -void fpga_eeprom_write (uint16_t address, size_t length, uint8_t *buffer) { - fpga_cmd_t cmd = CMD_EEPROM_WRITE; - uint8_t adjusted_address = ((address >> 3) & 0xFF); - - hw_spi_start(); - hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); - hw_spi_trx(&adjusted_address, 1, SPI_TX); - hw_spi_trx(buffer, length, SPI_TX); - hw_spi_stop(); -} diff --git a/sw/controller/src/fpga.h b/sw/controller/src/fpga.h index c769c18..e2666dd 100644 --- a/sw/controller/src/fpga.h +++ b/sw/controller/src/fpga.h @@ -14,10 +14,7 @@ typedef enum { CMD_MEM_WRITE, CMD_USB_STATUS, CMD_USB_READ, - CMD_USB_WRITE, - CMD_FLASHRAM_READ, - CMD_EEPROM_READ, - CMD_EEPROM_WRITE + CMD_USB_WRITE } fpga_cmd_t; typedef enum { @@ -127,9 +124,6 @@ void fpga_mem_write (uint32_t address, size_t length, uint8_t *buffer); uint8_t fpga_usb_status_get (void); uint8_t fpga_usb_pop (void); void fpga_usb_push (uint8_t data); -void fpga_flashram_buffer_read (uint8_t *buffer); -void fpga_eeprom_read (uint16_t address, size_t length, uint8_t *buffer); -void fpga_eeprom_write (uint16_t address, size_t length, uint8_t *buffer); #endif diff --git a/sw/controller/src/usb.c b/sw/controller/src/usb.c index 00443a1..202aa1f 100644 --- a/sw/controller/src/usb.c +++ b/sw/controller/src/usb.c @@ -180,36 +180,6 @@ void usb_process (void) { p.state = STATE_RESPONSE; break; - case 'e': - if (p.args[1] == 0) { - p.state = STATE_RESPONSE; - } else { - uint8_t data[8]; - int length = (p.args[1] > 8) ? 8 : p.args[1]; - fpga_eeprom_read(p.args[0], length, data); - for (int i = 0; i < length; i++) { - while (!usb_tx_byte(data[i])); - } - p.args[0] += length; - p.args[1] -= length; - } - break; - - case 'E': - if (p.args[1] == 0) { - p.state = STATE_RESPONSE; - } else { - uint8_t data[8]; - int length = (p.args[1] > 8) ? 8 : p.args[1]; - for (int i = 0; i < length; i++) { - while (!usb_rx_byte(&data[i])); - } - fpga_eeprom_write(p.args[0], length, data); - p.args[0] += length; - p.args[1] -= length; - } - break; - case 'm': case 'M': if (!((fpga_reg_get(REG_USB_DMA_SCR) & DMA_SCR_BUSY))) { diff --git a/sw/pc/sc64.py b/sw/pc/sc64.py index 1957618..f51d560 100644 --- a/sw/pc/sc64.py +++ b/sw/pc/sc64.py @@ -55,7 +55,8 @@ class SC64: __SC64_VERSION_V2 = 0x53437632 __BOOTLOADER_OFFSET = (64 + 14) * 1024 * 1024 - __SAVE_OFFSET = (64 * 1024 * 1024) - (256 * 1024) + __SAVE_OFFSET = (64 * 1024 * 1024) - (128 * 1024) + __EEPROM_OFFSET = (96 * 1024 * 1024) + 8192 __DDIPL_OFFSET = 0x3bc0000 # (64 - 16 - 4) * 1024 * 1024 __CHUNK_SIZE = 256 * 1024 @@ -222,19 +223,6 @@ class SC64: self.__set_progress_finish() - def __read_file_from_eeprom(self, file: str) -> None: - length = 2048 - with open(file, "wb") as f: - self.__set_progress_init(length, os.path.basename(f.name)) - self.__write_cmd("e", 0, length) - while (f.tell() < length): - chunk_size = min(self.__CHUNK_SIZE, length - f.tell()) - f.write(self.__read(chunk_size)) - self.__set_progress_value(f.tell()) - self.__read_cmd_status("e") - self.__set_progress_finish() - - def __write_file_to_sdram(self, file: str, offset: int, min_length: int = 0) -> None: with open(file, "rb") as f: length = os.fstat(f.fileno()).st_size @@ -250,22 +238,6 @@ class SC64: self.__set_progress_finish() - def __write_file_to_eeprom(self, file: str) -> None: - length = 2048 - with open(file, "rb") as f: - file_length = os.fstat(f.fileno()).st_size - # transfer_size = max(length, min_length) - self.__set_progress_init(file_length, os.path.basename(f.name)) - self.__write_cmd("E", 0, length) - while (f.tell() < file_length): - self.__write(f.read(min(self.__CHUNK_SIZE, file_length - f.tell()))) - self.__set_progress_value(f.tell()) - if (file_length != length): - self.__write_dummy(length - file_length) - self.__read_cmd_status("E") - self.__set_progress_finish() - - def upload_bootloader(self, file: str, min_length: int = 1028 * 1024) -> None: offset = self.__BOOTLOADER_OFFSET with open(file, "rb") as f: @@ -410,25 +382,22 @@ class SC64: def download_save(self, file: str) -> None: - self.__read_file_from_eeprom(file) - # length = self.__get_save_length() - # if (length > 0): - # self.__read_file_from_sdram(file, self.__SAVE_OFFSET, length) - - # else: - # raise SC64Exception("Can't read save data - no save type is set") + length = self.__get_save_length() + if (length > 0): + self.__read_file_from_sdram(file, self.__SAVE_OFFSET if length > 2048 else self.__EEPROM_OFFSET, length) + else: + raise SC64Exception("Can't read save data - no save type is set") def upload_save(self, file: str) -> None: - self.__write_file_to_eeprom(file) - # length = self.__get_save_length() - # save_length = os.path.getsize(file) - # if (length <= 0): - # raise SC64Exception("Can't write save data - no save type is set") - # elif (length != save_length): - # raise SC64Exception("Can't write save data - save file size is different than expected") - # else: - # self.__write_file_to_sdram(file, self.__SAVE_OFFSET) + length = self.__get_save_length() + save_length = os.path.getsize(file) + if (length <= 0): + raise SC64Exception("Can't write save data - no save type is set") + elif (length != save_length): + raise SC64Exception("Can't write save data - save file size is different than expected") + else: + self.__write_file_to_sdram(file, self.__SAVE_OFFSET if length > 2048 else self.__EEPROM_OFFSET) def set_dd_enable(self, enable: bool) -> None: