diff --git a/fw/SummerCart64.qsf b/fw/SummerCart64.qsf
index 718a60f..0af918b 100644
--- a/fw/SummerCart64.qsf
+++ b/fw/SummerCart64.qsf
@@ -19,7 +19,7 @@
 #
 # Quartus Prime
 # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 22:48:47  August 04, 2021
+# Date created = 20:28:54  August 10, 2021
 #
 # -------------------------------------------------------------------------- #
 #
@@ -46,15 +46,32 @@ set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
-#set_global_assignment -name VERILOG_FILE picorv32/picorv32.v
+set_global_assignment -name VERILOG_FILE btldr/btldr.sv
+set_global_assignment -name VERILOG_FILE picorv32/picorv32.v
+set_global_assignment -name QSYS_FILE rtl/intel/snp/intel_snp.qsys
+set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
+set_global_assignment -name SDC_FILE SummerCart64.sdc
+set_global_assignment -name SIGNALTAP_FILE stp.stp
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_gpio.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_i2c.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_ram.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_soc.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_uart.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_usb.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SummerCart64.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/old/usb_ftdi_fsi.sv
+set_global_assignment -name SOURCE_FILE sfp.spf
 
 # Pin & Location Assignments
 # ==========================
-set_location_assignment PIN_6 -to io_pmod[3]
-set_location_assignment PIN_7 -to io_pmod[4]
-set_location_assignment PIN_8 -to io_pmod[5]
-set_location_assignment PIN_10 -to io_pmod[6]
-set_location_assignment PIN_11 -to io_pmod[7]
+set_location_assignment PIN_6 -to o_usb_clk
+set_location_assignment PIN_7 -to io_usb_miosi[3]
+set_location_assignment PIN_8 -to io_usb_miosi[2]
+set_location_assignment PIN_10 -to io_usb_miosi[1]
+set_location_assignment PIN_11 -to io_usb_miosi[0]
 set_location_assignment PIN_12 -to o_ftdi_si
 set_location_assignment PIN_13 -to o_ftdi_clk
 set_location_assignment PIN_14 -to i_ftdi_so
@@ -67,6 +84,8 @@ set_location_assignment PIN_25 -to i_n64_nmi
 set_location_assignment PIN_26 -to i_clk
 set_location_assignment PIN_27 -to i_n64_reset
 set_location_assignment PIN_28 -to i_n64_si_clk
+set_location_assignment PIN_29 -to io_n64_cic_clk
+set_location_assignment PIN_30 -to io_n64_cic_dq
 set_location_assignment PIN_32 -to io_n64_pi_ad[7]
 set_location_assignment PIN_33 -to io_n64_pi_ad[8]
 set_location_assignment PIN_38 -to io_n64_pi_ad[6]
@@ -129,7 +148,8 @@ set_location_assignment PIN_114 -to o_sd_clk
 set_location_assignment PIN_118 -to io_sd_cmd
 set_location_assignment PIN_119 -to io_sd_dat[3]
 set_location_assignment PIN_120 -to io_sd_dat[2]
-set_location_assignment PIN_123 -to o_n64_int
+set_location_assignment PIN_123 -to o_n64_irq
+set_location_assignment PIN_127 -to io_avr_mosi
 set_location_assignment PIN_130 -to io_flash_dq[0]
 set_location_assignment PIN_131 -to o_flash_clk
 set_location_assignment PIN_132 -to io_flash_dq[3]
@@ -137,8 +157,8 @@ set_location_assignment PIN_134 -to o_flash_cs
 set_location_assignment PIN_135 -to io_flash_dq[1]
 set_location_assignment PIN_136 -to io_flash_dq[2]
 set_location_assignment PIN_138 -to io_pmod[0]
-set_location_assignment PIN_140 -to io_pmod[1]
-set_location_assignment PIN_141 -to io_pmod[2]
+set_location_assignment PIN_140 -to i_usb_miso
+set_location_assignment PIN_141 -to o_usb_cs
 
 # Classic Timing Assignments
 # ==========================
@@ -146,6 +166,10 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 
+# Compiler Assignments
+# ====================
+set_global_assignment -name OPTIMIZATION_MODE BALANCED
+
 # Analysis & Synthesis Assignments
 # ================================
 set_global_assignment -name FAMILY "MAX 10"
@@ -193,15 +217,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
 
-# start AUTO_INSERT_SLD_NODE_ENTITY(auto_signaltap_0)
-# ---------------------------------------------------
-
-	# Signal Tap Assignments
-	# ======================
-
-# end AUTO_INSERT_SLD_NODE_ENTITY(auto_signaltap_0)
-# -------------------------------------------------
-
 # --------------------------
 # start ENTITY(SummerCart64)
 
@@ -215,7 +230,12 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_write
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_n64_int
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_n64_irq
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_usb_cs
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_usb_miosi[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_usb_miosi[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_usb_miosi[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_usb_miosi[3]
 
 	# start DESIGN_PARTITION(Top)
 	# ---------------------------
@@ -231,55 +251,75 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 # end ENTITY(SummerCart64)
 # ------------------------
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_application_image.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_boot_rom.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_bootloader_image.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_bus_keeper.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_busswitch.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cfs.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu_alu.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu_bus.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu_control.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu_decompressor.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_cpu_regfile.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_debug_dm.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_debug_dtm.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_dmem.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_fifo.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_gpio.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_icache.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_imem.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_mtime.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_neoled.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_package.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_pwm.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_slink.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_spi.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_sysinfo.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_top.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_trng.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_twi.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_uart.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_wdt.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_wishbone.vhd
-# set_global_assignment -name VHDL_FILE neorv32/rtl/core/neorv32_xirq.vhd
-set_global_assignment -name OPTIMIZATION_MODE BALANCED
-set_global_assignment -name VERILOG_FILE btldr/btldr.sv
-set_global_assignment -name VERILOG_FILE picorv32/picorv32.v
-set_global_assignment -name QSYS_FILE rtl/intel/snp/intel_snp.qsys
-set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
-set_global_assignment -name SDC_FILE SummerCart64.sdc
-set_global_assignment -name SIGNALTAP_FILE stp.stp
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_i2c.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_led.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_ram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_soc.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/SummerCart64.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to i_n64_reset -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to i_n64_si_clk -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to i_n64_reset -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to i_n64_si_clk -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=42" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=65536" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=65536" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to i_clk -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to io_avr_mosi -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to io_n64_cic_clk -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to io_n64_cic_dq -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to io_avr_mosi -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to io_n64_cic_clk -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to io_n64_cic_dq -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=5" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=5" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=45" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 set_global_assignment -name SLD_FILE db/stp_auto_stripped.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fw/btldr/Makefile b/fw/btldr/Makefile
index ff1ff58..2faa367 100644
--- a/fw/btldr/Makefile
+++ b/fw/btldr/Makefile
@@ -1,31 +1,36 @@
 CROSS=riscv64-unknown-elf-
-CFLAGS=-mabi=ilp32 -march=rv32i -Wl,-Bstatic,--strip-debug -ffreestanding -nostdlib 
+FLAGS=\
+	-mabi=ilp32 \
+	-march=rv32i \
+	-std=c11 \
+	-Os \
+	-Wall \
+	-Wstrict-prototypes \
+	-fverbose-asm \
+	-ffunction-sections \
+	-fdata-sections \
+	-Tbtldr.ld \
+	-Wl,--gc-sections \
+	-ffreestanding \
+	-nostartfiles \
+	-nostdlib
 
-all: btldr.hex btldr.bin btldr.sv print_size
+all: btldr.bin btldr.sv print_size
 
-startup.o: startup.S
-	$(CROSS)gcc -x assembler-with-cpp -c $(CFLAGS) startup.s -o startup.o
-
-btldr.o: btldr.c
-	$(CROSS)gcc -c $(CFLAGS) -o btldr.o btldr.c
-
-btldr.elf: SC64_PicoRV32I.ld startup.o btldr.o
-	$(CROSS)gcc $(CFLAGS) -TSC64_PicoRV32I.ld startup.o btldr.o -o btldr.elf
-
-btldr.hex: btldr.elf
-	$(CROSS)objcopy -O ihex btldr.elf btldr.hex
+btldr.elf: btldr.ld btldr.c
+	$(CROSS)gcc $(FLAGS) btldr.c -o btldr.elf
 
 btldr.bin: btldr.elf
 	$(CROSS)objcopy -O binary btldr.elf btldr.bin
 
 btldr.sv: btldr.bin
-	python3 bin2v.py
+	python3 bin2sv.py btldr.bin btldr_template.sv btldr.sv
 
 print_size:
 	@echo 'Size of target .elf file:'
 	$(CROSS)size -B btldr.elf
 
 clean:
-	rm -f btldr.sv btldr.bin btldr.hex btldr.elf btldr.o startup.o
+	rm -f btldr.sv btldr.bin btldr.elf
 
 .PHONY: clean
diff --git a/fw/btldr/bin2sv.py b/fw/btldr/bin2sv.py
new file mode 100644
index 0000000..50db27a
--- /dev/null
+++ b/fw/btldr/bin2sv.py
@@ -0,0 +1,38 @@
+#!/usr/bin/env python3
+import struct
+import sys
+
+binary = None
+sv_template = None
+sv_code = None
+
+binary_name = sys.argv[1] or 'binary.bin'
+template_name = sys.argv[2] or 'binary_template.sv'
+code_name = sys.argv[3] or 'binary.sv'
+
+try:
+    binary = open(binary_name, mode='rb')
+    sv_template = open(template_name, mode='r')
+    sv_code = open(code_name, mode='w')
+
+    var_name = sv_template.readline().strip()
+
+    rom_formatted = ''
+    index = 0
+    for line in iter(lambda: binary.read(4), ''):
+        if (not line):
+            break
+        value = format(struct.unpack('<I', line)[0], '08x')
+        rom_formatted += f'\n            {index}: {var_name} = 32\'h{value};'
+        index += 1
+
+    sv_code.write(sv_template.read().format(rom_formatted=rom_formatted))
+
+except Exception as e:
+    print(f'Unable to convert the code: {e}', file=sys.stderr)
+    sys.exit(-1)
+
+finally:
+    if (binary): binary.close()
+    if (sv_template): sv_template.close()
+    if (sv_code): sv_code.close()
diff --git a/fw/btldr/bin2v.py b/fw/btldr/bin2v.py
deleted file mode 100644
index 477d5af..0000000
--- a/fw/btldr/bin2v.py
+++ /dev/null
@@ -1,48 +0,0 @@
-#!/usr/bin/env python3
-import struct
-
-with open('btldr.bin', mode='rb') as code:
-    with open('btldr.sv', mode='w') as rom:
-        rom_formatted = ''
-        index = 0
-
-        for line in iter(lambda: code.read(4), ''):
-            if (not line):
-                break
-            value = format(struct.unpack('<I', line)[0], '08x')
-            rom_formatted += f'            {index}: rom_data = 32\'h{value};\n'
-            index += 1
-
-
-        rom.write(f'''module cpu_bootloader (
-    if_system.sys system_if,
-    if_cpu_bus_out cpu_bus_if,
-    if_cpu_bus_in cpu_bootloader_if
-);
-
-    wire request;
-    reg ack;
-    reg [31:0] rom_data;
-    reg [31:0] q;
-
-    assign request = (cpu_bus_if.address[31:24] == 8'h01) && cpu_bus_if.req;
-    assign cpu_bootloader_if.ack = ack & request;
-    assign cpu_bootloader_if.rdata = cpu_bootloader_if.ack ? q : 32'd0;
-
-    always_comb begin
-        case (cpu_bus_if.address[9:2])
-{rom_formatted}
-            default: rom_data = 32'h0000_0000;
-        endcase
-    end
-
-    always_ff @(posedge system_if.clk) begin
-        ack <= 1'b0;
-        q <= rom_data;
-        if (request) begin
-            ack <= 1'b1;
-        end
-    end
-
-endmodule
-''')
diff --git a/fw/btldr/btldr.bin b/fw/btldr/btldr.bin
index ca97179..672186c 100644
Binary files a/fw/btldr/btldr.bin and b/fw/btldr/btldr.bin differ
diff --git a/fw/btldr/btldr.c b/fw/btldr/btldr.c
index 7d1408a..cf078c7 100644
--- a/fw/btldr/btldr.c
+++ b/fw/btldr/btldr.c
@@ -1,17 +1,17 @@
-#define LED     *((volatile unsigned int *) 0x80000000)
+#include "btldr.h"
 
-volatile int counter = 0;
+int reset_handler (void) {
+    io8_t pointer = &RAM;
+
+    while (!(UART_SR & UART_SR_TXE));
+    UART_TX = '>';
 
-int main (void) {
     while (1) {
-        if (counter++ == 0x000FFFFF) {
-            LED ^= 1;
-            counter = 0;
+        if (UART_SR & UART_SR_RXNE) {
+            *pointer++ = UART_RX;
+        }
+        if ((uint32_t)pointer == (24 * 1024)) {
+            __asm__("call 0");
         }
     }
 }
-
-void irq_handler(void) {
-    LED = 1;
-    while (1);
-}
diff --git a/fw/btldr/btldr.elf b/fw/btldr/btldr.elf
index 1652e76..670a0b7 100644
Binary files a/fw/btldr/btldr.elf and b/fw/btldr/btldr.elf differ
diff --git a/fw/btldr/btldr.h b/fw/btldr/btldr.h
new file mode 100644
index 0000000..573f1bb
--- /dev/null
+++ b/fw/btldr/btldr.h
@@ -0,0 +1,24 @@
+#ifndef BTLDR_H__
+#define BTLDR_H__
+
+
+#include <stdint.h>
+
+
+typedef volatile uint8_t *      io8_t;
+typedef volatile uint32_t *     io32_t;
+
+#define RAM                     (*((io8_t)  0x00000000))
+#define UART_SR                 (*((io8_t)  0xB0000000))
+#define UART_RX                 (*((io8_t)  0xB0000004))
+#define UART_TX                 (*((io8_t)  0xB0000008))
+#define GPIO                    (*((io32_t) 0xE0000000))
+#define GPIO_O                  (*((io8_t)  0xE0000000))
+#define GPIO_I                  (*((io8_t)  0xE0000001))
+#define GPIO_OE                 (*((io8_t)  0xE0000002))
+
+#define UART_SR_RXNE            (1 << 0)
+#define UART_SR_TXE             (1 << 1)
+
+
+#endif
diff --git a/fw/btldr/btldr.hex b/fw/btldr/btldr.hex
deleted file mode 100644
index 95dbde6..0000000
--- a/fw/btldr/btldr.hex
+++ /dev/null
@@ -1,23 +0,0 @@
-:020000040100F9
-:100000000B6000066F008001130000001300000069
-:10001000EF0040110B0000046F000000930000008F
-:10002000176100FF130101FD93010000130200009E
-:100030009302000013030000930300001304000068
-:100040009304000013050000930500001306000050
-:100050009306000013070000930700001308000038
-:10006000930800001309000093090000130A000020
-:10007000930A0000130B0000930B0000130C000008
-:10008000930C0000130D0000930D0000130E0000F0
-:10009000930E0000130F0000930F000017050000DF
-:1000A0001305450A930500001306000063DCC50034
-:1000B0008326050023A0D500130545009385450040
-:1000C000E3C8C5FE13050000930540006358B50062
-:1000D0002320050013054500E34CB5FEEF0080002A
-:1000E0006F000000130101FF2326810013040101AA
-:1000F00083270000938617002320D00037071000C5
-:100100001307F7FFE396E7FEB707008003A7070092
-:10011000B70700801347170023A0E7002320000043
-:100120006FF01FFD130101FF23268100130401015D
-:10013000B70700801307100023A0E7006F0000003E
-:0400000501000000F6
-:00000001FF
diff --git a/fw/btldr/SC64_PicoRV32I.ld b/fw/btldr/btldr.ld
similarity index 88%
rename from fw/btldr/SC64_PicoRV32I.ld
rename to fw/btldr/btldr.ld
index 77058f7..e3f03c3 100644
--- a/fw/btldr/SC64_PicoRV32I.ld
+++ b/fw/btldr/btldr.ld
@@ -1,9 +1,11 @@
 MEMORY
 {
     ram (rwx)   : org = 0x00000000, len = 24k
-    rom (rx)    : org = 0x01000000, len = 1k
+    rom (rx)    : org = 0xF0000000, len = 1k
 }
 
+__stack_pointer = ORIGIN(ram) + LENGTH(ram) - 16;
+
 ENTRY(reset_handler);
 
 SECTIONS
@@ -36,5 +38,3 @@ SECTIONS
 		__bss_end = .;
     } > ram AT > ram
 }
-
-__stack_pointer = ORIGIN(ram) + LENGTH(ram) - 16;
diff --git a/fw/btldr/btldr.o b/fw/btldr/btldr.o
deleted file mode 100644
index 2b7983e..0000000
Binary files a/fw/btldr/btldr.o and /dev/null differ
diff --git a/fw/btldr/btldr.sv b/fw/btldr/btldr.sv
index 445c557..60e92a5 100644
--- a/fw/btldr/btldr.sv
+++ b/fw/btldr/btldr.sv
@@ -5,107 +5,39 @@ module cpu_bootloader (
 );
 
     wire request;
-    reg ack;
-    reg [31:0] rom_data;
-    reg [31:0] q;
+    wire [31:0] rdata;
 
-    assign request = (cpu_bus_if.address[31:24] == 8'h01) && cpu_bus_if.req;
-    assign cpu_bootloader_if.ack = ack & request;
-    assign cpu_bootloader_if.rdata = cpu_bootloader_if.ack ? q : 32'd0;
+    cpu_bus_glue #(.ADDRESS(4'hF)) cpu_bus_glue_bootloader_inst (
+        .*,
+        .cpu_peripheral_if(cpu_bootloader_if),
+        .request(request),
+        .rdata(rdata)
+    );
 
     always_comb begin
-        case (cpu_bus_if.address[9:2])
-            0: rom_data = 32'h0600600b;
-            1: rom_data = 32'h0180006f;
-            2: rom_data = 32'h00000013;
-            3: rom_data = 32'h00000013;
-            4: rom_data = 32'h114000ef;
-            5: rom_data = 32'h0400000b;
-            6: rom_data = 32'h0000006f;
-            7: rom_data = 32'h00000093;
-            8: rom_data = 32'hff006117;
-            9: rom_data = 32'hfd010113;
-            10: rom_data = 32'h00000193;
-            11: rom_data = 32'h00000213;
-            12: rom_data = 32'h00000293;
-            13: rom_data = 32'h00000313;
-            14: rom_data = 32'h00000393;
-            15: rom_data = 32'h00000413;
-            16: rom_data = 32'h00000493;
-            17: rom_data = 32'h00000513;
-            18: rom_data = 32'h00000593;
-            19: rom_data = 32'h00000613;
-            20: rom_data = 32'h00000693;
-            21: rom_data = 32'h00000713;
-            22: rom_data = 32'h00000793;
-            23: rom_data = 32'h00000813;
-            24: rom_data = 32'h00000893;
-            25: rom_data = 32'h00000913;
-            26: rom_data = 32'h00000993;
-            27: rom_data = 32'h00000a13;
-            28: rom_data = 32'h00000a93;
-            29: rom_data = 32'h00000b13;
-            30: rom_data = 32'h00000b93;
-            31: rom_data = 32'h00000c13;
-            32: rom_data = 32'h00000c93;
-            33: rom_data = 32'h00000d13;
-            34: rom_data = 32'h00000d93;
-            35: rom_data = 32'h00000e13;
-            36: rom_data = 32'h00000e93;
-            37: rom_data = 32'h00000f13;
-            38: rom_data = 32'h00000f93;
-            39: rom_data = 32'h00000517;
-            40: rom_data = 32'h0a450513;
-            41: rom_data = 32'h00000593;
-            42: rom_data = 32'h00000613;
-            43: rom_data = 32'h00c5dc63;
-            44: rom_data = 32'h00052683;
-            45: rom_data = 32'h00d5a023;
-            46: rom_data = 32'h00450513;
-            47: rom_data = 32'h00458593;
-            48: rom_data = 32'hfec5c8e3;
-            49: rom_data = 32'h00000513;
-            50: rom_data = 32'h00400593;
-            51: rom_data = 32'h00b55863;
-            52: rom_data = 32'h00052023;
-            53: rom_data = 32'h00450513;
-            54: rom_data = 32'hfeb54ce3;
-            55: rom_data = 32'h008000ef;
-            56: rom_data = 32'h0000006f;
-            57: rom_data = 32'hff010113;
-            58: rom_data = 32'h00812623;
-            59: rom_data = 32'h01010413;
-            60: rom_data = 32'h00002783;
-            61: rom_data = 32'h00178693;
-            62: rom_data = 32'h00d02023;
-            63: rom_data = 32'h00100737;
-            64: rom_data = 32'hfff70713;
-            65: rom_data = 32'hfee796e3;
-            66: rom_data = 32'h800007b7;
-            67: rom_data = 32'h0007a703;
-            68: rom_data = 32'h800007b7;
-            69: rom_data = 32'h00174713;
-            70: rom_data = 32'h00e7a023;
-            71: rom_data = 32'h00002023;
-            72: rom_data = 32'hfd1ff06f;
-            73: rom_data = 32'hff010113;
-            74: rom_data = 32'h00812623;
-            75: rom_data = 32'h01010413;
-            76: rom_data = 32'h800007b7;
-            77: rom_data = 32'h00100713;
-            78: rom_data = 32'h00e7a023;
-            79: rom_data = 32'h0000006f;
-
-            default: rom_data = 32'h0000_0000;
+        case (cpu_bus_if.address[6:2])
+            0: rdata = 32'hb0000737;
+            1: rdata = 32'h00074783;
+            2: rdata = 32'h0027f793;
+            3: rdata = 32'hfe078ce3;
+            4: rdata = 32'h03e00793;
+            5: rdata = 32'h00f70423;
+            6: rdata = 32'hb00006b7;
+            7: rdata = 32'h00000793;
+            8: rdata = 32'h00006637;
+            9: rdata = 32'h0006c703;
+            10: rdata = 32'h00177713;
+            11: rdata = 32'h00070a63;
+            12: rdata = 32'h0046c703;
+            13: rdata = 32'h00178793;
+            14: rdata = 32'h0ff77713;
+            15: rdata = 32'hfee78fa3;
+            16: rdata = 32'hfec792e3;
+            17: rdata = 32'h10000097;
+            18: rdata = 32'hfbc080e7;
+            19: rdata = 32'hfd9ff06f;
+            default: rdata = 32'h0000_0000;
         endcase
     end
 
-    always_ff @(posedge system_if.clk) begin
-        ack <= 1'b0;
-        q <= rom_data;
-        if (request) begin
-            ack <= 1'b1;
-        end
-    end
-
 endmodule
diff --git a/fw/btldr/btldr_template.sv b/fw/btldr/btldr_template.sv
new file mode 100644
index 0000000..033b9da
--- /dev/null
+++ b/fw/btldr/btldr_template.sv
@@ -0,0 +1,24 @@
+rdata
+module cpu_bootloader (
+    if_system.sys system_if,
+    if_cpu_bus_out cpu_bus_if,
+    if_cpu_bus_in cpu_bootloader_if
+);
+
+    wire request;
+    wire [31:0] rdata;
+
+    cpu_bus_glue #(.ADDRESS(4'hF)) cpu_bus_glue_bootloader_inst (
+        .*,
+        .cpu_peripheral_if(cpu_bootloader_if),
+        .request(request),
+        .rdata(rdata)
+    );
+
+    always_comb begin
+        case (cpu_bus_if.address[6:2]){rom_formatted}
+            default: rdata = 32'h0000_0000;
+        endcase
+    end
+
+endmodule
diff --git a/fw/btldr/custom_ops.S b/fw/btldr/custom_ops.S
deleted file mode 100644
index 64e5b8b..0000000
--- a/fw/btldr/custom_ops.S
+++ /dev/null
@@ -1,94 +0,0 @@
-#define regnum_q0   0
-#define regnum_q1   1
-#define regnum_q2   2
-#define regnum_q3   3
-
-#define regnum_x0   0
-#define regnum_x1   1
-#define regnum_x2   2
-#define regnum_x3   3
-#define regnum_x4   4
-#define regnum_x5   5
-#define regnum_x6   6
-#define regnum_x7   7
-#define regnum_x8   8
-#define regnum_x9   9
-#define regnum_x10 10
-#define regnum_x11 11
-#define regnum_x12 12
-#define regnum_x13 13
-#define regnum_x14 14
-#define regnum_x15 15
-#define regnum_x16 16
-#define regnum_x17 17
-#define regnum_x18 18
-#define regnum_x19 19
-#define regnum_x20 20
-#define regnum_x21 21
-#define regnum_x22 22
-#define regnum_x23 23
-#define regnum_x24 24
-#define regnum_x25 25
-#define regnum_x26 26
-#define regnum_x27 27
-#define regnum_x28 28
-#define regnum_x29 29
-#define regnum_x30 30
-#define regnum_x31 31
-
-#define regnum_zero 0
-#define regnum_ra   1
-#define regnum_sp   2
-#define regnum_gp   3
-#define regnum_tp   4
-#define regnum_t0   5
-#define regnum_t1   6
-#define regnum_t2   7
-#define regnum_s0   8
-#define regnum_s1   9
-#define regnum_a0  10
-#define regnum_a1  11
-#define regnum_a2  12
-#define regnum_a3  13
-#define regnum_a4  14
-#define regnum_a5  15
-#define regnum_a6  16
-#define regnum_a7  17
-#define regnum_s2  18
-#define regnum_s3  19
-#define regnum_s4  20
-#define regnum_s5  21
-#define regnum_s6  22
-#define regnum_s7  23
-#define regnum_s8  24
-#define regnum_s9  25
-#define regnum_s10 26
-#define regnum_s11 27
-#define regnum_t3  28
-#define regnum_t4  29
-#define regnum_t5  30
-#define regnum_t6  31
-
-// x8 is s0 and also fp
-#define regnum_fp   8
-
-#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
-.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
-
-#define picorv32_getq_insn(_rd, _qs) \
-r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
-
-#define picorv32_setq_insn(_qd, _rs) \
-r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
-
-#define picorv32_retirq_insn() \
-r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
-
-#define picorv32_maskirq_insn(_rd, _rs) \
-r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
-
-#define picorv32_waitirq_insn(_rd) \
-r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
-
-#define picorv32_timer_insn(_rd, _rs) \
-r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
diff --git a/fw/btldr/startup.S b/fw/btldr/startup.S
deleted file mode 100644
index 8da03a8..0000000
--- a/fw/btldr/startup.S
+++ /dev/null
@@ -1,82 +0,0 @@
-#include "custom_ops.S"
-
-
-.global reset_handler
-
-.global irq_handler
-.weak irq_handler
-.set irq_handler, default_irq_handler
-
-
-.section .text
-reset_handler:
-    picorv32_maskirq_insn(zero, zero)
-    j start_handler
-
-.balign 16
-irq_handler:
-    call irq_handler
-    picorv32_retirq_insn()
-
-default_irq_handler:
-    j default_irq_handler
-
-start_handler:
-    li ra, 0
-    la sp, __stack_pointer
-    li gp, 0
-    li tp, 0
-    li t0, 0
-    li t1, 0
-    li t2, 0
-    li s0, 0
-    li s1, 0
-    li a0, 0
-    li a1, 0
-    li a2, 0
-    li a3, 0
-    li a4, 0
-    li a5, 0
-    li a6, 0
-    li a7, 0
-    li s2, 0
-    li s3, 0
-    li s4, 0
-    li s5, 0
-    li s6, 0
-    li s7, 0
-    li s8, 0
-    li s9, 0
-    li s10, 0
-    li s11, 0
-    li t3, 0
-    li t4, 0
-    li t5, 0
-    li t6, 0
-
-init_data:
-    la a0, __data_init_start
-    la a1, __data_start
-    la a2, __data_end
-    bge a1, a2, init_bss
-loop_init_data:
-    lw a3, 0(a0)
-    sw a3, 0(a1)
-    addi a0, a0, 4
-    addi a1, a1, 4
-    blt a1, a2, loop_init_data
-
-init_bss:
-    la a0, __bss_start
-    la a1, __bss_end
-    bge a0, a1, entry_point
-loop_init_bss:
-    sw zero, 0(a0)
-    addi a0, a0, 4
-    blt a0, a1, loop_init_bss
-
-entry_point:
-    call main
-
-loop:
-    j loop
diff --git a/fw/btldr/startup.o b/fw/btldr/startup.o
deleted file mode 100644
index d3741a7..0000000
Binary files a/fw/btldr/startup.o and /dev/null differ
diff --git a/fw/cntrllr/Makefile b/fw/cntrllr/Makefile
new file mode 100644
index 0000000..2bbb6c3
--- /dev/null
+++ b/fw/cntrllr/Makefile
@@ -0,0 +1,32 @@
+CROSS=riscv64-unknown-elf-
+FLAGS=\
+	-mabi=ilp32 \
+	-march=rv32i \
+	-std=c11 \
+	-Os \
+	-Wall \
+	-Wstrict-prototypes \
+	-fverbose-asm \
+	-ffunction-sections \
+	-fdata-sections \
+	-Wl,--gc-sections \
+	-ffreestanding \
+	-nostartfiles \
+	-nostdlib
+
+all: cntrllr.bin print_size
+
+cntrllr.elf: cntrllr.ld main.c rtc.c startup.S
+	$(CROSS)gcc $(FLAGS) -Tcntrllr.ld main.c rtc.c startup.S -o cntrllr.elf
+
+cntrllr.bin: cntrllr.elf
+	$(CROSS)objcopy -O binary --gap-fill 0xFF --pad-to 0x6000 cntrllr.elf cntrllr.bin
+
+print_size:
+	@echo 'Size of target .elf file:'
+	$(CROSS)size -B cntrllr.elf
+
+clean:
+	rm -f cntrllr.bin cntrllr.elf
+
+.PHONY: clean
diff --git a/fw/cntrllr/cntrllr.bin b/fw/cntrllr/cntrllr.bin
new file mode 100644
index 0000000..d10aebf
Binary files /dev/null and b/fw/cntrllr/cntrllr.bin differ
diff --git a/fw/cntrllr/cntrllr.elf b/fw/cntrllr/cntrllr.elf
new file mode 100644
index 0000000..13e48e8
Binary files /dev/null and b/fw/cntrllr/cntrllr.elf differ
diff --git a/fw/cntrllr/cntrllr.ld b/fw/cntrllr/cntrllr.ld
new file mode 100644
index 0000000..abf4e9c
--- /dev/null
+++ b/fw/cntrllr/cntrllr.ld
@@ -0,0 +1,23 @@
+MEMORY
+{
+    ram (rwx)   : org = 0x00000000, len = 24k
+}
+
+__stack_pointer = ORIGIN(ram) + LENGTH(ram) - 16;
+
+ENTRY(reset_handler)
+
+SECTIONS
+{
+    .memory :
+    {
+        . = ALIGN(4);
+        *(.reset);
+        . = ALIGN(4);
+        *(.text .text* .rodata .rodata* .srodata .srodata*);
+        . = ALIGN(4);
+        *(.bss .bss.* .sbss .sbss.*);
+        . = ALIGN(4);
+        *(.data .data.* .sdata .stada.*);
+    } > ram
+}
diff --git a/fw/cntrllr/main.c b/fw/cntrllr/main.c
new file mode 100644
index 0000000..be06bd9
--- /dev/null
+++ b/fw/cntrllr/main.c
@@ -0,0 +1,87 @@
+#include "sys.h"
+#include "rtc.h"
+
+
+volatile int counter = 0;
+
+
+void print (const char *text) {
+    while (*text != '\0') {
+        while (!(UART_SR & UART_SR_TXE) && (!(UART_SR & UART_SR_RXNE)));
+        UART_TX = *text++;
+    }
+}
+
+const char hex_char_map[16] = {
+    '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
+};
+
+void print_02hex (unsigned char number) {
+    char buffer[3];
+    buffer[0] = hex_char_map[number >> 4];
+    buffer[1] = hex_char_map[number & 0x0F];
+    buffer[2] = '\0';
+    print(buffer);
+}
+
+const char *weekday_names[7] = {
+    "Monday",
+    "Tuesday",
+    "Wednesday",
+    "Thursday",
+    "Friday",
+    "Saturday",
+    "Sunday"
+};
+
+void print_nice_date(uint8_t *date) {
+    print_02hex(date[4]);
+    print(".");
+    print_02hex(date[5]);
+    print(".20");
+    print_02hex(date[6]);
+    print(" (");
+    print(weekday_names[date[3] - 1]);
+    print(") ");
+    print_02hex(date[2]);
+    print(":");
+    print_02hex(date[1]);
+    print(":");
+    print_02hex(date[0]);
+}
+
+__NAKED__ int main (void) {
+    uint8_t rtc_data[7];
+    uint8_t rtc_new_data[7];
+    int index = 0;
+
+    GPIO_OE = (1 << 0);
+    GPIO_O = (1 << 0);
+
+    rtc_init();
+
+    while (1) {
+        GPIO_O = (1 << 0);
+
+        print("\033[2J\033[H\r\n --- Hello --- \r\n\r\n");
+        print(" RTC Data:\r\n\r\n ");
+
+        rtc_get_time(rtc_data);
+
+        print_nice_date(rtc_data);
+
+        print("\r\n");
+        GPIO_O = 0x00;
+
+        while (counter++ < 0x0003FFFF);
+        counter = 0;
+
+        if (UART_SR & UART_SR_RXNE) {
+            rtc_new_data[index++] = UART_RX;
+            if (index == 7) {
+                index = 0;
+                rtc_set_time(rtc_new_data);
+            }
+        }
+    }
+}
diff --git a/fw/cntrllr/rtc.c b/fw/cntrllr/rtc.c
new file mode 100644
index 0000000..f7350b7
--- /dev/null
+++ b/fw/cntrllr/rtc.c
@@ -0,0 +1,128 @@
+#include "sys.h"
+#include "rtc.h"
+
+
+static const uint8_t rtc_bit_mask[7] = {
+    0b01111111,
+    0b01111111,
+    0b00111111,
+    0b00000111,
+    0b00111111,
+    0b00011111,
+    0b11111111
+};
+
+
+static uint8_t i2c_is_busy (void) {
+    return (I2C_SR & I2C_SR_BUSY);
+}
+
+static void i2c_wait_busy (void) {
+    while (i2c_is_busy());
+}
+
+static uint8_t i2c_has_ack (void) {
+    return (I2C_SR & I2C_SR_ACK);
+}
+
+static void i2c_start (void) {
+    i2c_wait_busy();
+    I2C_SR = I2C_SR_START;
+}
+
+static void i2c_stop (void) {
+    i2c_wait_busy();
+    I2C_SR = I2C_SR_STOP;
+}
+
+static uint8_t i2c_write (uint8_t data) {
+    i2c_wait_busy();
+    I2C_SR = 0;
+    I2C_DR = data;
+    i2c_wait_busy();
+    return i2c_has_ack();
+}
+
+static void i2c_read (uint8_t *data, uint8_t cfg) {
+    i2c_wait_busy();
+    I2C_SR = cfg;
+    I2C_DR = 0xFF;
+    i2c_wait_busy();
+    *data = I2C_DR;
+}
+
+static uint8_t i2c_tx (uint8_t address, uint8_t *data, size_t length) {
+    uint8_t result = 0;
+
+    i2c_start();
+    result |= i2c_write(RTC_ADDR);
+    result |= i2c_write(address);
+    for (size_t i = 0; i < length; i++) {
+        result |= i2c_write(*data++);
+    }
+    i2c_stop();
+
+    return result;
+}
+
+static uint8_t i2c_rx (uint8_t address, uint8_t *data, size_t length) {
+    uint8_t result = 0;
+
+    i2c_start();
+    result |= i2c_write(RTC_ADDR);
+    result |= i2c_write(address);
+    i2c_start();
+    result |= i2c_write(RTC_ADDR | I2C_ADDR_READ);
+    for (size_t i = 0; i < length; i++) {
+        i2c_read(data++, (i == (length - 1)) ? 0 : I2C_SR_MACK);
+    }
+    i2c_stop();
+
+    return result;
+}
+
+static void rtc_sanitize_data (uint8_t *rtc_data) {
+    for (int i = 0; i < 7; i++) {
+        rtc_data[i] &= rtc_bit_mask[i];
+    }
+}
+
+uint8_t rtc_set_time (uint8_t *rtc_data) {
+    uint8_t result = 0;
+    uint8_t tmp;
+
+    rtc_sanitize_data(rtc_data);
+
+    rtc_data[RTC_RTCSEC] |= RTC_RTCSEC_ST;
+    rtc_data[RTC_RTCWKDAY] |= RTC_RTCWKDAY_VBAT;
+
+    result |= i2c_tx(RTC_RTCSEC, 0x00, 1);
+    result |= i2c_tx(RTC_RTCMIN, rtc_data + 1, 6);
+    result |= i2c_tx(RTC_RTCSEC, rtc_data, 1);
+
+    do {
+        result |= i2c_rx(RTC_RTCWKDAY, &tmp, 7);
+    } while ((!(tmp & RTC_RTCWKDAY_OSCRUN)) || !result);
+
+    return result;
+}
+
+uint8_t rtc_get_time (uint8_t *rtc_data) {
+    uint8_t result = i2c_rx(RTC_RTCSEC, rtc_data, 7);
+
+    rtc_sanitize_data(rtc_data);
+
+    return result;
+}
+
+void rtc_init (void) {
+    uint8_t result;
+    uint8_t rtc_data[7];
+
+    result = i2c_rx(RTC_RTCSEC, rtc_data, 1);
+
+    if ((!(rtc_data[0] & RTC_RTCSEC_ST)) && (!result)) {
+        rtc_get_time(rtc_data);
+        rtc_set_time(rtc_data);
+    }
+}
diff --git a/fw/cntrllr/rtc.h b/fw/cntrllr/rtc.h
new file mode 100644
index 0000000..c56f1dc
--- /dev/null
+++ b/fw/cntrllr/rtc.h
@@ -0,0 +1,23 @@
+#ifndef RTC_H__
+#define RTC_H__
+
+
+#include "sys.h"
+
+
+#define RTC_ADDR            (0xDE)
+
+#define RTC_RTCSEC          (0x00)
+#define RTC_RTCSEC_ST       (1 << 7)
+#define RTC_RTCMIN          (0x01)
+#define RTC_RTCWKDAY        (0x03)
+#define RTC_RTCWKDAY_OSCRUN (1 << 5)
+#define RTC_RTCWKDAY_VBAT   (1 << 3)
+
+
+uint8_t rtc_set_time (uint8_t *rtc_data);
+uint8_t rtc_get_time (uint8_t *rtc_data);
+void rtc_init (void);
+
+
+#endif
diff --git a/fw/cntrllr/startup.S b/fw/cntrllr/startup.S
new file mode 100644
index 0000000..929a092
--- /dev/null
+++ b/fw/cntrllr/startup.S
@@ -0,0 +1,5 @@
+.section .reset
+.global reset_handler
+reset_handler:
+    la sp, __stack_pointer
+    j main
diff --git a/fw/cntrllr/sys.h b/fw/cntrllr/sys.h
new file mode 100644
index 0000000..553bc5a
--- /dev/null
+++ b/fw/cntrllr/sys.h
@@ -0,0 +1,35 @@
+#ifndef SYS_H__
+#define SYS_H__
+
+
+#include <stddef.h>
+#include <stdint.h>
+
+
+#define __NAKED__               __attribute__((naked))
+
+typedef volatile uint8_t *      io8_t;
+typedef volatile uint32_t *     io32_t;
+
+#define I2C_SR                  (*((io8_t)  0xC0000000))
+#define I2C_DR                  (*((io8_t)  0xC0000004))
+#define UART_SR                 (*((io8_t)  0xD0000000))
+#define UART_RX                 (*((io8_t)  0xD0000004))
+#define UART_TX                 (*((io8_t)  0xD0000008))
+#define GPIO                    (*((io32_t) 0xE0000000))
+#define GPIO_O                  (*((io8_t)  0xE0000000))
+#define GPIO_I                  (*((io8_t)  0xE0000001))
+#define GPIO_OE                 (*((io8_t)  0xE0000002))
+
+#define I2C_SR_START            (1 << 0)
+#define I2C_SR_STOP             (1 << 1)
+#define I2C_SR_MACK             (1 << 2)
+#define I2C_SR_ACK              (1 << 3)
+#define I2C_SR_BUSY             (1 << 4)
+#define I2C_ADDR_READ           (1 << 0)
+
+#define UART_SR_RXNE            (1 << 0)
+#define UART_SR_TXE             (1 << 1)
+
+
+#endif
diff --git a/fw/cntrllr/time.dat b/fw/cntrllr/time.dat
new file mode 100644
index 0000000..beebfff
Binary files /dev/null and b/fw/cntrllr/time.dat differ
diff --git a/fw/rtl/SummerCart64.sv b/fw/rtl/SummerCart64.sv
index 9b0249a..a095b08 100644
--- a/fw/rtl/SummerCart64.sv
+++ b/fw/rtl/SummerCart64.sv
@@ -1,6 +1,11 @@
 module SummerCart64 (
     input i_clk,
 
+    output o_usb_clk,
+    output o_usb_cs,
+    input i_usb_miso,
+    inout [3:0] io_usb_miosi,
+
     output o_ftdi_clk,
     output o_ftdi_si,
     input i_ftdi_so,
@@ -8,7 +13,7 @@ module SummerCart64 (
 
     input i_n64_reset,
     input i_n64_nmi,
-    output o_n64_int,
+    output o_n64_irq,
 
     input i_n64_pi_alel,
     input i_n64_pi_aleh,
@@ -41,17 +46,35 @@ module SummerCart64 (
 
     output o_led,
 
-    inout [7:0] io_pmod
+    inout [0:0] io_pmod
 );
 
     if_system system_if (.in_clk(i_clk));
     system system_inst (.system_if(system_if));
 
-    if_cpu_soc cpu_soc_if ();
-    cpu_soc cpu_soc_inst (.system_if(system_if), .cpu_soc_if(cpu_soc_if));
+    wire [7:0] gpio_o;
+    wire [7:0] gpio_i;
+    wire [7:0] gpio_oe;
 
-    assign o_led = cpu_soc_if.peripherals.led;
-    assign io_rtc_scl = cpu_soc_if.peripherals.scl;
-    assign io_rtc_sda = cpu_soc_if.peripherals.sda;
+    assign o_led = gpio_oe[0] ? gpio_o[0] : 1'bZ;
+    assign o_n64_irq = gpio_oe[1] ? gpio_o[1] : 1'bZ;
+    assign gpio_i = {4'd0, i_n64_nmi, i_n64_reset, o_n64_irq, o_led};
+
+    cpu_soc cpu_soc_inst (
+        .*,
+        .gpio_o(gpio_o),
+        .gpio_i(gpio_i),
+        .gpio_oe(gpio_oe),
+        .usb_clk(o_usb_clk),
+        .usb_cs(o_usb_cs),
+        .usb_miso(i_usb_miso),
+        .usb_miosi(io_usb_miosi),
+        .ftdi_clk(o_ftdi_clk),
+        .ftdi_si(o_ftdi_si),
+        .ftdi_so(i_ftdi_so),
+        .ftdi_cts(i_ftdi_cts),
+        .scl(io_rtc_scl),
+        .sda(io_rtc_sda)
+    );
 
 endmodule
diff --git a/fw/rtl/cpu/cpu_bus.sv b/fw/rtl/cpu/cpu_bus.sv
index 4c0b750..10d508d 100644
--- a/fw/rtl/cpu/cpu_bus.sv
+++ b/fw/rtl/cpu/cpu_bus.sv
@@ -13,3 +13,29 @@ interface if_cpu_bus_in ();
     logic [31:0] rdata;
 
 endinterface
+
+module cpu_bus_glue #(
+    parameter [3:0] ADDRESS = 4'h0
+) (
+    if_system.sys system_if,
+    if_cpu_bus_out cpu_bus_if,
+    if_cpu_bus_in cpu_peripheral_if,
+
+    output request,
+    input [31:0] rdata
+);
+    reg ack;
+
+    assign request = (cpu_bus_if.address[31:28] == ADDRESS) && cpu_bus_if.req;
+    assign cpu_peripheral_if.ack = ack & request;
+    assign cpu_peripheral_if.rdata = cpu_peripheral_if.ack ? rdata : 32'd0;
+
+    always_ff @(posedge system_if.clk) begin
+        ack <= 1'b0;
+
+        if (!system_if.reset && request) begin
+            ack <= 1'b1;
+        end
+    end
+
+endmodule
diff --git a/fw/rtl/cpu/cpu_gpio.sv b/fw/rtl/cpu/cpu_gpio.sv
new file mode 100644
index 0000000..aeb3310
--- /dev/null
+++ b/fw/rtl/cpu/cpu_gpio.sv
@@ -0,0 +1,41 @@
+module cpu_gpio (
+    if_system.sys system_if,
+    if_cpu_bus_out cpu_bus_if,
+    if_cpu_bus_in cpu_gpio_if,
+
+    input [7:0] gpio_i,
+    output reg [7:0] gpio_o,
+    output reg [7:0] gpio_oe
+);
+
+    wire request;
+    wire [31:0] rdata;
+
+    cpu_bus_glue #(.ADDRESS(4'hE)) cpu_bus_glue_gpio_inst (
+        .*,
+        .cpu_peripheral_if(cpu_gpio_if),
+        .request(request),
+        .rdata(rdata)
+    );
+
+    reg [7:0] gpio_i_ff1, gpio_i_ff2;
+    reg [7:0] gpio_o_value;
+    reg [7:0] gpio_oe_value;
+
+    assign rdata = {8'd0, gpio_oe_value, gpio_i_ff2, gpio_o_value};
+
+    always_ff @(posedge system_if.clk) begin
+        {gpio_i_ff2, gpio_i_ff1} <= {gpio_i_ff1, gpio_i};
+        gpio_o <= gpio_o_value;
+        gpio_oe <= gpio_oe_value;
+
+        if (system_if.reset) begin
+            gpio_o_value <= 8'd0;
+            gpio_oe_value <= 8'd0;
+        end else if (request) begin
+            if (cpu_bus_if.wstrb[0]) gpio_o_value <= cpu_bus_if.wdata[7:0];
+            if (cpu_bus_if.wstrb[2]) gpio_oe_value <= cpu_bus_if.wdata[23:16];
+        end
+    end
+
+endmodule
diff --git a/fw/rtl/cpu/cpu_i2c.sv b/fw/rtl/cpu/cpu_i2c.sv
index 83213c0..b97e627 100644
--- a/fw/rtl/cpu/cpu_i2c.sv
+++ b/fw/rtl/cpu/cpu_i2c.sv
@@ -7,26 +7,152 @@ module cpu_i2c (
     inout sda
 );
 
-    // wire request;
-    // reg ack;
-    // // reg led_value;
+    wire request;
+    wire [31:0] rdata;
 
-    // assign request = (cpu_bus_if.address[31:3] == (32'h8001_0000 >> 3)) && cpu_bus_if.req;
-    // assign cpu_led_if.ack = ack & request;
-    // assign cpu_led_if.rdata = cpu_led_if.ack ? {32'd0} : 32'd0;
+    cpu_bus_glue #(.ADDRESS(4'hC)) cpu_bus_glue_i2c_inst (
+        .*,
+        .cpu_peripheral_if(cpu_i2c_if),
+        .request(request),
+        .rdata(rdata)
+    );
 
-    // always_ff @(posedge system_if.clk) begin
-    //     ack <= 1'b0;
-    //     // led <= led_value;
+    reg [1:0] state;
+    reg mack;
+    reg [8:0] trx_data;
 
-    //     if (system_if.reset) begin
-    //         // led_value <= 1'b0;
-    //     end else if (request) begin
-    //         ack <= 1'b1;
-    //         if (cpu_bus_if.wstrb[0]) begin
-    //             // led_value <= cpu_bus_if.wdata[0];
-    //         end
-    //     end
-    // end
+    always_comb begin
+        case (cpu_bus_if.address[2])
+            0: rdata = {27'd0, |state, ~trx_data[0], mack, 2'b00};
+            1: rdata = {23'd0, trx_data[0], trx_data[8:1]};
+            default: rdata = 32'd0;
+        endcase
+    end
+
+    always_ff @(posedge system_if.clk) begin
+        if (system_if.reset) begin
+            mack <= 1'b0;
+        end else if (request && cpu_bus_if.wstrb[0] && !cpu_bus_if.address[2]) begin
+            mack <= cpu_bus_if.wdata[2];
+        end
+    end
+
+    reg [5:0] clock_div;
+    reg [3:0] clock_phase_gen;
+
+    wire clock_tick = &clock_div;
+    wire [3:0] clock_phase = {4{clock_tick}} & clock_phase_gen;
+
+    always_ff @(posedge system_if.clk) begin
+        if (system_if.reset) begin
+            clock_div <= 6'd0;
+        end else begin
+            clock_div <= clock_div + 1'd1;
+        end
+
+        if (system_if.reset || state == 2'd0) begin
+            clock_phase_gen <= 4'b0001;
+        end else if (clock_tick) begin
+            clock_phase_gen <= {clock_phase_gen[2:0], clock_phase_gen[3]};
+        end
+    end
+
+    reg [3:0] bit_counter;
+
+    reg sda_i_ff1, sda_i_ff2;
+    reg scl_o;
+    reg sda_o;
+
+    assign scl = scl_o ? 1'bZ : 1'b0;
+    assign sda = sda_o ? 1'bZ : 1'b0;
+
+    always_ff @(posedge system_if.clk) begin
+        {sda_i_ff2, sda_i_ff1} <= {sda_i_ff1, sda};
+
+        if (system_if.reset) begin
+            state <= 2'd0;
+            scl_o <= 1'b1;
+            sda_o <= 1'b1;
+        end else begin
+            case (state)
+                2'd0: begin
+                    bit_counter <= 4'd0;
+
+                    if (request && cpu_bus_if.wstrb[0]) begin
+                        case (cpu_bus_if.address[2])
+                            0: begin
+                                if (cpu_bus_if.wdata[1]) state <= 2'd2;
+                                if (cpu_bus_if.wdata[0]) state <= 2'd1;
+                            end
+
+                            1: begin
+                                state <= 2'd3;
+                                trx_data <= {cpu_bus_if.wdata[7:0], ~mack};
+                            end
+                        endcase
+                    end
+                end
+
+                2'd1: begin
+                    if (clock_phase[0]) begin
+                        scl_o <= 1'b1;
+                        sda_o <= 1'b1;
+                    end
+
+                    if (clock_phase[1]) begin
+                        sda_o <= 1'b0;
+                    end
+
+                    if (clock_phase[3]) begin
+                        state <= 2'd0;
+                        scl_o <= 1'b0;
+                    end
+                end
+
+                2'd2: begin
+                    if (clock_phase[0]) begin
+                        scl_o <= 1'b0;
+                        sda_o <= 1'b0;
+                    end
+
+                    if (clock_phase[1]) begin
+                        scl_o <= 1'b1;
+                    end
+
+                    if (clock_phase[3]) begin
+                        state <= 2'd0;
+                        sda_o <= 1'b1;
+                    end
+                end
+
+                2'd3: begin
+                    if (clock_phase[0]) begin
+                        bit_counter <= bit_counter + 1'd1;
+                        scl_o <= 1'b0;
+                        sda_o <= trx_data[8];
+                    end
+
+                    if (clock_phase[1]) begin
+                        scl_o <= 1'b1;
+                    end
+
+                    if (clock_phase[3]) begin
+                        trx_data <= {trx_data[7:0], sda_i_ff2};
+                        scl_o <= 1'b0;
+                    end
+
+                    if (bit_counter == 4'b1010) begin
+                        state <= 2'd0;
+                    end
+                end
+
+                default: begin
+                    state <= 2'd0;
+                    scl_o <= 1'b1;
+                    sda_o <= 1'b1;
+                end
+            endcase
+        end
+    end
 
 endmodule
diff --git a/fw/rtl/cpu/cpu_led.sv b/fw/rtl/cpu/cpu_led.sv
deleted file mode 100644
index 31c26e1..0000000
--- a/fw/rtl/cpu/cpu_led.sv
+++ /dev/null
@@ -1,31 +0,0 @@
-module cpu_led (
-    if_system.sys system_if,
-    if_cpu_bus_out cpu_bus_if,
-    if_cpu_bus_in cpu_led_if,
-
-    output reg led
-);
-
-    wire request;
-    reg ack;
-    reg led_value;
-
-    assign request = (cpu_bus_if.address == 32'h8000_0000) && cpu_bus_if.req;
-    assign cpu_led_if.ack = ack & request;
-    assign cpu_led_if.rdata = cpu_led_if.ack ? {31'd0, led_value} : 32'd0;
-
-    always_ff @(posedge system_if.clk) begin
-        ack <= 1'b0;
-        led <= led_value;
-
-        if (system_if.reset) begin
-            led_value <= 1'b0;
-        end else if (request) begin
-            ack <= 1'b1;
-            if (cpu_bus_if.wstrb[0]) begin
-                led_value <= cpu_bus_if.wdata[0];
-            end
-        end
-    end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_ram.sv b/fw/rtl/cpu/cpu_ram.sv
index 038e9a0..ca41789 100644
--- a/fw/rtl/cpu/cpu_ram.sv
+++ b/fw/rtl/cpu/cpu_ram.sv
@@ -5,40 +5,39 @@ module cpu_ram (
 );
 
     wire request;
+    wire [31:0] rdata;
+
+    cpu_bus_glue #(.ADDRESS(4'h0)) cpu_bus_glue_ram_inst (
+        .*,
+        .cpu_peripheral_if(cpu_ram_if),
+        .request(request),
+        .rdata(rdata)
+    );
+
     wire bank;
-    reg ack;
-    reg [3:0][7:0] ram1 [0:4095];
-    reg [3:0][7:0] ram2 [0:2047];
-    reg [31:0] q1;
-    reg [31:0] q2;
+    reg [3:0][7:0] ram_1 [0:4095];
+    reg [3:0][7:0] ram_2 [0:2047];
+    reg [31:0] q_1, q_2;
     wire [31:0] q;
 
-    assign request = (cpu_bus_if.address[31:24] == 8'h00) && cpu_bus_if.req;
     assign bank = cpu_bus_if.address[14];
-    assign q = bank ? q2 : q1;
-    assign cpu_ram_if.ack = ack & request;
-    assign cpu_ram_if.rdata = cpu_ram_if.ack ? q : 32'd0;
+    assign rdata = bank ? q_2 : q_1;
 
     always_ff @(posedge system_if.clk) begin
-        ack <= 1'b0;
-        if (request) begin
-            ack <= 1'b1;
-        end
-
-        q1 <= ram1[cpu_bus_if.address[14:2]];
+        q_1 <= ram_1[cpu_bus_if.address[13:2]];
         if (request & !bank) begin
-            if (cpu_bus_if.wstrb[0]) ram1[cpu_bus_if.address[13:2]][0] <= cpu_bus_if.wdata[7:0];
-            if (cpu_bus_if.wstrb[1]) ram1[cpu_bus_if.address[13:2]][1] <= cpu_bus_if.wdata[15:8];
-            if (cpu_bus_if.wstrb[2]) ram1[cpu_bus_if.address[13:2]][2] <= cpu_bus_if.wdata[23:16];
-            if (cpu_bus_if.wstrb[3]) ram1[cpu_bus_if.address[13:2]][3] <= cpu_bus_if.wdata[31:24];
+            if (cpu_bus_if.wstrb[0]) ram_1[cpu_bus_if.address[13:2]][0] <= cpu_bus_if.wdata[7:0];
+            if (cpu_bus_if.wstrb[1]) ram_1[cpu_bus_if.address[13:2]][1] <= cpu_bus_if.wdata[15:8];
+            if (cpu_bus_if.wstrb[2]) ram_1[cpu_bus_if.address[13:2]][2] <= cpu_bus_if.wdata[23:16];
+            if (cpu_bus_if.wstrb[3]) ram_1[cpu_bus_if.address[13:2]][3] <= cpu_bus_if.wdata[31:24];
         end
 
-        q2 <= ram2[cpu_bus_if.address[12:2]];
+        q_2 <= ram_2[cpu_bus_if.address[12:2]];
         if (request & bank) begin
-            if (cpu_bus_if.wstrb[0]) ram2[cpu_bus_if.address[12:2]][0] <= cpu_bus_if.wdata[7:0];
-            if (cpu_bus_if.wstrb[1]) ram2[cpu_bus_if.address[12:2]][1] <= cpu_bus_if.wdata[15:8];
-            if (cpu_bus_if.wstrb[2]) ram2[cpu_bus_if.address[12:2]][2] <= cpu_bus_if.wdata[23:16];
-            if (cpu_bus_if.wstrb[3]) ram2[cpu_bus_if.address[12:2]][3] <= cpu_bus_if.wdata[31:24];
+            if (cpu_bus_if.wstrb[0]) ram_2[cpu_bus_if.address[12:2]][0] <= cpu_bus_if.wdata[7:0];
+            if (cpu_bus_if.wstrb[1]) ram_2[cpu_bus_if.address[12:2]][1] <= cpu_bus_if.wdata[15:8];
+            if (cpu_bus_if.wstrb[2]) ram_2[cpu_bus_if.address[12:2]][2] <= cpu_bus_if.wdata[23:16];
+            if (cpu_bus_if.wstrb[3]) ram_2[cpu_bus_if.address[12:2]][3] <= cpu_bus_if.wdata[31:24];
         end
     end
 
diff --git a/fw/rtl/cpu/cpu_soc.sv b/fw/rtl/cpu/cpu_soc.sv
index 389a3bb..cb08cfd 100644
--- a/fw/rtl/cpu/cpu_soc.sv
+++ b/fw/rtl/cpu/cpu_soc.sv
@@ -1,27 +1,22 @@
-interface if_cpu_soc ();
-
-    logic led;
-    logic scl;
-    logic sda;
-
-    modport peripherals (
-        input led,
-        inout scl,
-        inout sda
-    );
-
-    modport cpu (
-        output led,
-        inout scl,
-        inout sda
-    );
-
-endinterface
-
-
 module cpu_soc (
     if_system.sys system_if,
-    if_cpu_soc.cpu cpu_soc_if
+
+    input [7:0] gpio_i,
+    output [7:0] gpio_o,
+    output [7:0] gpio_oe,
+
+    output usb_clk,
+    output usb_cs,
+    input usb_miso,
+    inout [3:0] usb_miosi,
+
+    output ftdi_clk,
+    output ftdi_si,
+    input ftdi_so,
+    input ftdi_cts,
+
+    inout scl,
+    inout sda
 );
 
     if_cpu_bus_out cpu_bus_if ();
@@ -53,7 +48,7 @@ module cpu_soc (
         .REGS_INIT_ZERO(0),
         .MASKED_IRQ(32'h0000_0000),
         .LATCHED_IRQ(32'hFFFF_FFFF),
-        .PROGADDR_RESET(32'h0100_0000),
+        .PROGADDR_RESET(32'hF000_0000),
         .PROGADDR_IRQ(32'h0000_0010),
         .STACKADDR(32'hFFFF_FFFF)
     ) cpu_inst (
@@ -67,11 +62,6 @@ module cpu_soc (
         .mem_rdata(cpu_rdata)
     );
 
-    wire scl;
-    wire sda;
-
-    assign cpu_soc_if.scl = scl;
-    assign cpu_soc_if.sda = sda;
 
     if_cpu_bus_in cpu_ram_if ();
     cpu_ram cpu_ram_inst (.*);
@@ -79,23 +69,55 @@ module cpu_soc (
     if_cpu_bus_in cpu_bootloader_if ();
     cpu_bootloader cpu_bootloader_inst (.*);
 
-    if_cpu_bus_in cpu_led_if ();
-    cpu_led cpu_led_inst (.*, .led(cpu_soc_if.led));
+    if_cpu_bus_in cpu_gpio_if ();
+    cpu_gpio cpu_gpio_inst (
+        .*,
+        .gpio_i(gpio_i),
+        .gpio_o(gpio_o),
+        .gpio_oe(gpio_oe)
+    );
+
+    if_cpu_bus_in cpu_uart_if ();
+    cpu_uart cpu_uart_inst (
+        .*,
+        .ftdi_clk(ftdi_clk),
+        .ftdi_si(ftdi_si),
+        .ftdi_so(ftdi_so),
+        .ftdi_cts(ftdi_cts)
+    );
 
     if_cpu_bus_in cpu_i2c_if ();
-    cpu_i2c cpu_i2c_inst (.*, .scl(scl), .sda(sda));
+    cpu_i2c cpu_i2c_inst (
+        .*,
+        .scl(scl),
+        .sda(sda)
+    );
+
+    if_cpu_bus_in cpu_usb_if ();
+    cpu_usb cpu_usb_inst (
+        .*,
+        .usb_clk(usb_clk),
+        .usb_cs(usb_cs),
+        .usb_miso(usb_miso),
+        .usb_miosi(usb_miosi)
+    );
+
 
     assign cpu_ack = (
         cpu_ram_if.ack |
         cpu_bootloader_if.ack |
-        cpu_led_if.ack |
-        cpu_i2c_if.ack
+        cpu_gpio_if.ack |
+        cpu_uart_if.ack |
+        cpu_i2c_if.ack |
+        cpu_usb_if.ack
     );
     assign cpu_rdata = (
         cpu_ram_if.rdata |
         cpu_bootloader_if.rdata |
-        cpu_led_if.rdata |
-        cpu_i2c_if.rdata
+        cpu_gpio_if.rdata |
+        cpu_uart_if.rdata |
+        cpu_i2c_if.rdata |
+        cpu_usb_if.rdata
     );
 
 endmodule
diff --git a/fw/rtl/cpu/cpu_uart.sv b/fw/rtl/cpu/cpu_uart.sv
new file mode 100644
index 0000000..3f3d94c
--- /dev/null
+++ b/fw/rtl/cpu/cpu_uart.sv
@@ -0,0 +1,81 @@
+module cpu_uart (
+    if_system.sys system_if,
+    if_cpu_bus_out cpu_bus_if,
+    if_cpu_bus_in cpu_uart_if,
+
+    output ftdi_clk,
+    output ftdi_si,
+    input ftdi_so,
+    input ftdi_cts
+);
+
+    wire request;
+    wire [31:0] rdata;
+
+    cpu_bus_glue #(.ADDRESS(4'hD)) cpu_bus_glue_uart_inst (
+        .*,
+        .cpu_peripheral_if(cpu_uart_if),
+        .request(request),
+        .rdata(rdata)
+    );
+
+    reg rx_ready;    
+    wire tx_busy;
+    reg [7:0] rx_data;
+    reg [7:0] tx_data;
+
+    always_comb begin
+        case (cpu_bus_if.address[3:2])
+            0: rdata = {30'd0, ~tx_busy, ~rx_ready};
+            1: rdata = {24'd0, rx_data};
+            2: rdata = {24'd0, tx_data};
+            default: rdata = 32'd0;
+        endcase
+    end
+
+    wire rx_valid;
+    reg tx_valid;
+    wire [7:0] f_rx_data;
+
+    always_ff @(posedge system_if.clk) begin
+        tx_valid <= 1'b0;
+
+        if (rx_valid) begin
+            rx_ready <= 1'b0;
+            rx_data <= f_rx_data;
+        end
+
+        if (system_if.reset) begin
+            rx_ready <= 1'b1;
+        end else if (request) begin
+            if (cpu_bus_if.wstrb[0] && cpu_bus_if.address[3:2] == 2'd2 && !tx_busy) begin
+                tx_valid <= 1'b1;
+                tx_data <= cpu_bus_if.wdata[7:0];
+            end
+            if (cpu_bus_if.address[3:2] == 2'd1) begin
+                rx_ready <= 1'b1;
+            end
+        end
+    end
+
+    usb_ftdi_fsi usb_ftdi_fsi_inst (
+        .i_clk(system_if.clk),
+        .i_reset(system_if.reset),
+
+        .o_ftdi_clk(ftdi_clk),
+        .o_ftdi_si(ftdi_si),
+        .i_ftdi_so(ftdi_so),
+        .i_ftdi_cts(ftdi_cts),
+
+        .i_rx_ready(rx_ready),
+        .o_rx_valid(rx_valid),
+        // .o_rx_channel(1'bX),
+        .o_rx_data(f_rx_data),
+
+        .o_tx_busy(tx_busy),
+        .i_tx_valid(tx_valid),
+        .i_tx_channel(1'b1),
+        .i_tx_data(tx_data)
+    );
+
+endmodule
diff --git a/fw/rtl/cpu/cpu_usb.sv b/fw/rtl/cpu/cpu_usb.sv
new file mode 100644
index 0000000..bcc4524
--- /dev/null
+++ b/fw/rtl/cpu/cpu_usb.sv
@@ -0,0 +1,97 @@
+module cpu_usb (
+    if_system.sys system_if,
+    if_cpu_bus_out cpu_bus_if,
+    if_cpu_bus_in cpu_usb_if,
+
+    output usb_clk,
+    output usb_cs,
+    input usb_miso,
+    inout [3:0] usb_miosi
+);
+
+    wire request;
+    wire [31:0] rdata;
+
+    cpu_bus_glue #(.ADDRESS(4'hB)) cpu_bus_glue_usb_inst (
+        .*,
+        .cpu_peripheral_if(cpu_usb_if),
+        .request(request),
+        .rdata(rdata)
+    );
+
+    reg rx_ready;    
+    wire tx_busy;
+    reg [7:0] rx_data;
+    reg [7:0] tx_data;
+
+    always_comb begin
+        case (cpu_bus_if.address[3:2])
+            0: rdata = {30'd0, ~tx_busy, ~rx_ready};
+            1: rdata = {24'd0, rx_data};
+            2: rdata = {24'd0, tx_data};
+            default: rdata = 32'd0;
+        endcase
+    end
+
+    reg usb_request;
+    reg usb_write;
+    wire usb_busy;
+    wire usb_ack;
+    wire [7:0] usb_wdata;
+    wire [7:0] usb_rdata;
+    wire usb_rx_available;
+    wire usb_tx_available;
+
+    assign tx_busy = usb_busy || !usb_tx_available;
+    assign usb_wdata = tx_data;
+
+    // wire rx_valid;
+    // reg tx_valid;
+    // wire [7:0] f_rx_data;
+
+    always_ff @(posedge system_if.clk) begin
+        // tx_valid <= 1'b0;
+        usb_request <= 1'b0;
+
+        if (usb_ack) begin
+            rx_ready <= 1'b0;
+            rx_data <= usb_rdata;
+        end
+
+        if (system_if.reset) begin
+            rx_ready <= 1'b1;
+        end else if (request) begin
+            if (cpu_bus_if.wstrb[0] && cpu_bus_if.address[3:2] == 2'd2 && !tx_busy) begin
+                // tx_valid <= 1'b1;
+                usb_request <= 1'b1;
+                usb_write <= 1'b1;
+                tx_data <= cpu_bus_if.wdata[7:0];
+            end
+            if (cpu_bus_if.address[3:2] == 2'd1) begin
+                rx_ready <= 1'b1;
+            end
+        end else if (usb_rx_available && rx_ready) begin
+            usb_request <= 1'b1;
+            usb_write <= 1'b0;
+        end
+    end
+
+    usb_ft1248 usb_ft1248_inst (
+        .system_if(system_if),
+
+        .usb_clk(usb_clk),
+        .usb_cs(usb_cs),
+        .usb_miso(usb_miso),
+        .usb_miosi(usb_miosi),
+
+        .request(usb_request),
+        .write(usb_write),
+        .busy(usb_busy),
+        .ack(usb_ack),
+        .wdata(usb_wdata),
+        .rdata(usb_rdata),
+        .rx_available(usb_rx_available),
+        .tx_available(usb_tx_available)
+    );
+
+endmodule
diff --git a/fw/rtl/old/usb_ftdi_fsi.sv b/fw/rtl/old/usb_ftdi_fsi.sv
new file mode 100644
index 0000000..c2f1f82
--- /dev/null
+++ b/fw/rtl/old/usb_ftdi_fsi.sv
@@ -0,0 +1,116 @@
+module usb_ftdi_fsi (
+    input i_clk,
+    input i_reset,
+
+    output reg o_ftdi_clk,
+    output reg o_ftdi_si,
+    input i_ftdi_so,
+    input i_ftdi_cts,
+
+    input i_rx_ready,
+    output reg o_rx_valid,
+    output reg o_rx_channel,
+    output reg [7:0] o_rx_data,
+
+    output reg o_tx_busy,
+    input i_tx_valid,
+    input i_tx_channel,
+    input [7:0] i_tx_data
+);
+
+    // Output clock generation and control
+
+    always @(posedge i_clk) begin
+        if (i_reset || !i_rx_ready) begin
+            o_ftdi_clk <= 1'b1;
+        end else begin
+            o_ftdi_clk <= ~o_ftdi_clk;
+        end
+    end
+
+
+    // RX module
+
+    reg r_rx_in_progress;
+    reg [3:0] r_rx_bit_counter;
+    reg r_tx_start_bit;
+    reg r_rx_tx_contention;
+
+    always @(posedge i_clk) begin
+        o_rx_valid <= 1'b0;
+
+        if (i_reset) begin
+            r_rx_in_progress <= 1'b0;
+        end else begin
+            if (!o_ftdi_clk) begin
+                if (!r_rx_in_progress) begin
+                    r_rx_in_progress <= !i_ftdi_so;
+                    r_rx_bit_counter <= 4'd0;
+                    r_rx_tx_contention <= r_tx_start_bit;
+                end else begin
+                    r_rx_bit_counter <= r_rx_bit_counter + 4'd1;
+
+                    if (!r_rx_bit_counter[3]) begin
+                        o_rx_data <= {i_ftdi_so, o_rx_data[7:1]};
+                    end else begin
+                        r_rx_in_progress <= 1'b0;
+                        o_rx_valid <= !r_rx_tx_contention;
+                        o_rx_channel <= i_ftdi_so;
+                    end
+                end
+            end
+        end
+    end
+
+
+    // TX module
+
+    reg r_tx_pending;
+    reg [3:0] r_tx_bit_counter;
+    reg [7:0] r_tx_data;
+    reg r_tx_channel;
+
+    wire w_tx_request_op = i_tx_valid && !o_tx_busy;
+    wire w_tx_pending_op = !o_ftdi_clk || !i_ftdi_cts || !i_rx_ready || r_rx_in_progress;
+    wire w_tx_reset_output_op = o_ftdi_clk && !o_tx_busy;
+    wire w_tx_start_op = (w_tx_request_op || r_tx_pending) && !w_tx_pending_op;
+    wire w_tx_shift_op = o_ftdi_clk && o_tx_busy && !r_tx_pending;
+
+    always @(posedge i_clk) begin
+        r_tx_start_bit <= 1'b0;
+
+        if (i_reset) begin
+            o_ftdi_si <= 1'b1;
+            o_tx_busy <= 1'b0;
+            r_tx_pending <= 1'b0;
+        end else begin
+            if (w_tx_request_op) begin
+                o_tx_busy <= 1'b1;
+                r_tx_data <= i_tx_data;
+                r_tx_channel <= i_tx_channel;
+                r_tx_pending <= w_tx_pending_op;
+            end
+
+            if (w_tx_reset_output_op) begin
+                o_ftdi_si <= 1'b1;
+            end
+
+            if (w_tx_start_op) begin
+                o_ftdi_si <= 1'b0;
+                r_tx_start_bit <= 1'b1;
+                r_tx_pending <= 1'b0;
+                r_tx_bit_counter <= 4'd0;
+            end
+
+            if (w_tx_shift_op) begin
+                r_tx_bit_counter <= r_tx_bit_counter + 4'd1;
+                {r_tx_data[6:0], o_ftdi_si} <= r_tx_data;
+                if (r_tx_bit_counter[3]) begin
+                    o_ftdi_si <= r_tx_channel;
+                    o_tx_busy <= 1'b0;
+                end
+            end
+        end
+    end
+
+endmodule
diff --git a/fw/rtl/usb/usb_ft1248.sv b/fw/rtl/usb/usb_ft1248.sv
new file mode 100644
index 0000000..53715c5
--- /dev/null
+++ b/fw/rtl/usb/usb_ft1248.sv
@@ -0,0 +1,154 @@
+module usb_ft1248 (
+    if_system.sys system_if,
+
+    output usb_clk,
+    output usb_cs,
+    input usb_miso,
+    inout [3:0] usb_miosi,
+
+    input request,
+    input write,
+    output busy,
+    output reg ack,
+    input [7:0] wdata,
+    output reg [7:0] rdata,
+
+    output reg rx_available,
+    output reg tx_available
+);
+
+    typedef enum bit [2:0] {
+        S_IDLE = 3'b000,
+        S_COMMAND = 3'b100,
+        S_DATA = 3'b101,
+        S_END = 3'b110
+    } e_state;
+
+    typedef enum bit [7:0] {
+        C_WRITE = 8'h00,
+        C_READ = 8'h04
+    } e_command;
+
+    e_state state;
+
+    assign busy = state[2];
+
+    reg [3:0] clock_divider;
+    wire rising_edge;
+    wire falling_edge;
+
+    assign rising_edge = clock_divider[1];
+    assign falling_edge = clock_divider[3];
+
+    always_ff @(posedge system_if.clk) begin
+        if (system_if.reset || state == S_IDLE) begin
+            clock_divider <= 4'b0001;
+            usb_clk <= 1'b0;
+        end else begin
+            clock_divider <= {clock_divider[2:0], clock_divider[3]};
+            if (state != S_END) begin
+                if (rising_edge) usb_clk <= 1'b1;
+                if (falling_edge) usb_clk <= 1'b0;
+            end
+        end
+    end
+
+    reg miosi_ff_1, miosi_ff_2;
+    reg miso_ff_1, miso_ff_2;
+
+    reg mode;
+
+    reg [1:0] bit_counter;
+
+    reg output_enable;
+
+    reg [7:0] tx_data;
+    reg [3:0] miosi;
+
+    reg [7:0] command;
+
+
+    assign usb_miosi = output_enable ? miosi : 4'bZZZZ;
+
+    always_ff @(posedge system_if.clk) begin
+        {miosi_ff_2, miosi_ff_1} <= {miosi_ff_1, usb_miosi[0]};
+        {miso_ff_2, miso_ff_1} <= {miso_ff_1, usb_miso};
+        rx_available <= 1'b0;
+        tx_available <= 1'b0;
+        ack <= 1'b0;
+
+        if (system_if.reset) begin
+            state <= S_IDLE;
+            usb_cs <= 1'b1;
+            output_enable <= 1'b0;
+        end else begin
+            case (state)
+                S_IDLE: begin
+                    rx_available <= ~miso_ff_2;
+                    tx_available <= ~miosi_ff_2;
+                    bit_counter <= 1'b0;
+                    usb_cs <= 1'b1;
+                    output_enable <= 1'b0;
+                    if (request) begin
+                        mode <= write;
+                        if (rx_available || (write && tx_available)) begin
+                            state <= S_COMMAND;
+                            command <= write ? C_WRITE : C_READ;
+                            usb_cs <= 1'b0;
+                            rx_available <= 1'b0;
+                            tx_available <= 1'b0;
+                            tx_data <= {wdata[3:0], wdata[7:4]};
+                        end
+                    end
+                end
+
+                S_COMMAND: begin
+                    if (rising_edge) begin
+                        output_enable <= 1'b1;
+                        bit_counter <= bit_counter + 1'd1;
+                        {miosi, command} <= {command, 4'bXXXX};
+                        if (bit_counter == 2'd2) begin
+                            output_enable <= 1'b0;
+                        end
+                    end
+                    if (falling_edge && (bit_counter == 2'd3)) begin
+                        state <= S_DATA;
+                        bit_counter <= 2'd0;
+                    end
+                end
+
+                S_DATA: begin
+                    if (rising_edge) begin
+                        output_enable <= mode;
+                        bit_counter[0] <= ~bit_counter[0];
+                        {miosi, tx_data} <= {tx_data, 4'bXXXX};
+                    end
+                    if (falling_edge) begin
+                        rdata <= {usb_miosi, rdata[7:4]};
+                        if (!bit_counter[0]) begin
+                            state <= S_END;
+                            output_enable <= 1'b0;
+                            ack <= 1'b1;
+                        end
+                    end
+                end
+
+                S_END: begin
+                    if (rising_edge) begin
+                        bit_counter <= bit_counter + 1'd1;
+                        if (bit_counter == 2'd3) begin
+                            state <= S_IDLE;
+                        end
+                        usb_cs <= 1'b1;
+                    end
+                end
+
+                default: begin
+                    state <= S_IDLE;
+                end
+            endcase
+        end
+
+    end
+
+endmodule
diff --git a/fw/sfp.spf b/fw/sfp.spf
index 598c14a..3d30506 100644
--- a/fw/sfp.spf
+++ b/fw/sfp.spf
@@ -1,4 +1,4 @@
-<session jtag_chain="Arrow-USB-Blaster [AR5GOOMN]" jtag_device="@1: 10M08SA(.|ES)/10M08SC (0x031820DD)">
+<session jtag_chain="Arrow-USB-Blaster [AR5GOOMN]" jtag_device="@1: 10M08SA(.|ES)/10M08SC (0x031820DD)" sof_file="C:/Dev/SummerCollection/fw/output_files/SummerCart64.sof">
   <display_attributes is_max_probe_read_interval="1" is_write_immediate="1" probe_read_interval="1" probe_read_interval_units="s"/>
   <instance enable_logging="true" entity_name="SC64" is_auto_node="true" name="SC64">
     <node_ip_info instance_id="0" mfg_id="110" node_id="9" version="0"/>
diff --git a/fw/stp.stp b/fw/stp.stp
index 81f3f51..603c395 100644
--- a/fw/stp.stp
+++ b/fw/stp.stp
@@ -2,708 +2,215 @@
   <display_tree gui_logging_enabled="0">
     <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
   </display_tree>
-  <instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
+  <instance enabled="true" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
     <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
     <position_info>
       <single attribute="active tab" value="0"/>
-      <single attribute="data horizontal scroll position" value="0"/>
+      <single attribute="data horizontal scroll position" value="8184"/>
       <single attribute="data vertical scroll position" value="0"/>
       <single attribute="setup horizontal scroll position" value="0"/>
       <single attribute="setup vertical scroll position" value="0"/>
       <single attribute="zoom level denominator" value="1"/>
-      <single attribute="zoom level numerator" value="4096"/>
+      <single attribute="zoom level numerator" value="1024"/>
       <single attribute="zoom offset denominator" value="1"/>
-      <single attribute="zoom offset numerator" value="11"/>
+      <single attribute="zoom offset numerator" value="47"/>
+      <multi attribute="timebars" size="2" value="8204,8226"/>
     </position_info>
-    <signal_set global_temp="1" name="signal_set: 2021/08/05 16:09:12  #0">
-      <clock name="system:system_inst|system_if.clk" polarity="posedge" tap_mode="classic"/>
-      <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
+    <signal_set global_temp="1" name="signal_set: 2021/08/12 15:08:58  #0">
+      <clock name="i_clk" polarity="posedge" tap_mode="classic"/>
+      <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="65536" trigger_in_enable="no" trigger_out_enable="no"/>
       <top_entity/>
       <signal_vec>
         <trigger_input_vec>
-          <wire name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" tap_mode="classic"/>
+          <wire name="i_n64_reset" tap_mode="classic"/>
+          <wire name="i_n64_si_clk" tap_mode="classic"/>
+          <wire name="io_avr_mosi" tap_mode="classic"/>
+          <wire name="io_n64_cic_clk" tap_mode="classic"/>
+          <wire name="io_n64_cic_dq" tap_mode="classic"/>
         </trigger_input_vec>
         <data_input_vec>
-          <wire name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" tap_mode="classic"/>
+          <wire name="i_n64_reset" tap_mode="classic"/>
+          <wire name="i_n64_si_clk" tap_mode="classic"/>
+          <wire name="io_avr_mosi" tap_mode="classic"/>
+          <wire name="io_n64_cic_clk" tap_mode="classic"/>
+          <wire name="io_n64_cic_dq" tap_mode="classic"/>
         </data_input_vec>
         <storage_qualifier_input_vec>
-          <wire name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" tap_mode="classic"/>
-          <wire name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|cpu_bus_if.req" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[0]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[1]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[2]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[3]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[4]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[5]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[6]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[7]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|ack" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|bit_counter" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[0]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[1]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[2]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[3]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|output_enable" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[0]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[1]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[2]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[3]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[4]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[5]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[6]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[7]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|request" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rx_available" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[0]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[1]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[2]" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|tx_available" tap_mode="classic"/>
+          <wire name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|write" tap_mode="classic"/>
+          <wire name="i_n64_reset" tap_mode="classic"/>
+          <wire name="i_n64_si_clk" tap_mode="classic"/>
+          <wire name="i_usb_miso" tap_mode="classic"/>
+          <wire name="io_avr_mosi" tap_mode="classic"/>
+          <wire name="io_n64_cic_clk" tap_mode="classic"/>
+          <wire name="io_n64_cic_dq" tap_mode="classic"/>
+          <wire name="io_usb_miosi[0]" tap_mode="classic"/>
+          <wire name="io_usb_miosi[1]" tap_mode="classic"/>
+          <wire name="io_usb_miosi[2]" tap_mode="classic"/>
+          <wire name="io_usb_miosi[3]" tap_mode="classic"/>
+          <wire name="o_usb_cs" tap_mode="classic"/>
         </storage_qualifier_input_vec>
       </signal_vec>
       <presentation>
         <unified_setup_data_view>
-          <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
-          <node data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="66" type="unknown"/>
-          <node data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="65" type="unknown"/>
-          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="25" type="unknown"/>
-            <node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="24" type="unknown"/>
-            <node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="22" type="unknown"/>
-            <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="21" type="unknown"/>
-            <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="20" type="unknown"/>
-            <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="19" type="unknown"/>
-            <node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="18" type="unknown"/>
-            <node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="17" type="unknown"/>
-            <node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="16" type="unknown"/>
-            <node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="15" type="unknown"/>
-            <node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="14" type="unknown"/>
-            <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="13" type="unknown"/>
-            <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="11" type="unknown"/>
-            <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="10" type="unknown"/>
-            <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="9" type="unknown"/>
-            <node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="8" type="unknown"/>
-            <node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="7" type="unknown"/>
-            <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="6" type="unknown"/>
-            <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="5" type="unknown"/>
-            <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="4" type="unknown"/>
-            <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="3" type="unknown"/>
-            <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="2" type="unknown"/>
-            <node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="32" type="unknown"/>
-            <node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="31" type="unknown"/>
-            <node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="30" type="unknown"/>
-            <node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="29" type="unknown"/>
-            <node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="28" type="unknown"/>
-            <node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="27" type="unknown"/>
-            <node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="26" type="unknown"/>
-            <node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="23" type="unknown"/>
-            <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="12" type="unknown"/>
-            <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <node data_index="37" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="falling edge" name="o_usb_cs" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="37" type="unknown"/>
+          <node is_selected="false" level-0="alt_or" name="io_usb_miosi[3..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="bidir pin">
+            <node data_index="35" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="io_usb_miosi[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="35" type="unknown"/>
+            <node data_index="34" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="io_usb_miosi[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="34" type="unknown"/>
+            <node data_index="33" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="io_usb_miosi[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="33" type="unknown"/>
+            <node data_index="32" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="io_usb_miosi[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="32" type="unknown"/>
           </node>
-          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
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-            <node data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="56" type="unknown"/>
-            <node data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="54" type="unknown"/>
-            <node data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="53" type="unknown"/>
-            <node data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="52" type="unknown"/>
-            <node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="51" type="unknown"/>
-            <node data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="50" type="unknown"/>
-            <node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="49" type="unknown"/>
-            <node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="48" type="unknown"/>
-            <node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="47" type="unknown"/>
-            <node data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="46" type="unknown"/>
-            <node data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="45" type="unknown"/>
-            <node data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="43" type="unknown"/>
-            <node data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="42" type="unknown"/>
-            <node data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="41" type="unknown"/>
-            <node data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="40" type="unknown"/>
-            <node data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="39" type="unknown"/>
-            <node data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="38" type="unknown"/>
-            <node data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="37" type="unknown"/>
-            <node data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="36" type="unknown"/>
-            <node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="35" type="unknown"/>
-            <node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="34" type="unknown"/>
-            <node data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="64" type="unknown"/>
-            <node data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="63" type="unknown"/>
-            <node data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="62" type="unknown"/>
-            <node data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="61" type="unknown"/>
-            <node data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="60" type="unknown"/>
-            <node data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="59" type="unknown"/>
-            <node data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="58" type="unknown"/>
-            <node data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="55" type="unknown"/>
-            <node data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="44" type="unknown"/>
-            <node data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="33" type="unknown"/>
+          <node data_index="31" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="i_usb_miso" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="31" type="unknown"/>
+          <node data_index="15" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|output_enable" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/>
+          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <node data_index="28" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/>
+            <node data_index="27" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/>
+            <node data_index="26" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/>
           </node>
-          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <node data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="102" type="unknown"/>
-            <node data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="101" type="unknown"/>
-            <node data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="100" type="unknown"/>
-            <node data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="99" type="unknown"/>
+          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <node data_index="14" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/>
+            <node data_index="13" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/>
+            <node data_index="12" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/>
+            <node data_index="11" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/>
           </node>
-          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <node data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="91" type="unknown"/>
-            <node data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="90" type="unknown"/>
-            <node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="88" type="unknown"/>
-            <node data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="87" type="unknown"/>
-            <node data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="86" type="unknown"/>
-            <node data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="85" type="unknown"/>
-            <node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="84" type="unknown"/>
-            <node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="83" type="unknown"/>
-            <node data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="82" type="unknown"/>
-            <node data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="81" type="unknown"/>
-            <node data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="80" type="unknown"/>
-            <node data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="79" type="unknown"/>
-            <node data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="77" type="unknown"/>
-            <node data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="76" type="unknown"/>
-            <node data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="75" type="unknown"/>
-            <node data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="74" type="unknown"/>
-            <node data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="73" type="unknown"/>
-            <node data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="72" type="unknown"/>
-            <node data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="71" type="unknown"/>
-            <node data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="70" type="unknown"/>
-            <node data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="69" type="unknown"/>
-            <node data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="68" type="unknown"/>
-            <node data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="98" type="unknown"/>
-            <node data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="97" type="unknown"/>
-            <node data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="96" type="unknown"/>
-            <node data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="95" type="unknown"/>
-            <node data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="94" type="unknown"/>
-            <node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="93" type="unknown"/>
-            <node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="92" type="unknown"/>
-            <node data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="89" type="unknown"/>
-            <node data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="78" type="unknown"/>
-            <node data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="67" type="unknown"/>
+          <node data_index="10" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|bit_counter" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/>
+          <node data_index="24" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|request" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/>
+          <node data_index="25" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rx_available" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/>
+          <node data_index="29" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|tx_available" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/>
+          <node data_index="30" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/>
+          <node data_index="9" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|ack" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
+          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <node data_index="8" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
+            <node data_index="7" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
+            <node data_index="6" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
+            <node data_index="5" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <node data_index="4" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <node data_index="3" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <node data_index="2" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
+            <node data_index="1" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
           </node>
-          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <node data_index="1" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <node data_index="0" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|cpu_bus_if.req" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <node is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
+            <node data_index="23" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/>
+            <node data_index="22" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/>
+            <node data_index="21" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/>
+            <node data_index="20" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/>
+            <node data_index="19" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/>
+            <node data_index="18" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/>
+            <node data_index="17" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/>
+            <node data_index="16" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/>
           </node>
-          <node data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="103" type="unknown"/>
+          <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="i_n64_reset" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="io_n64_cic_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="3" type="unknown"/>
+          <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="io_n64_cic_dq" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="4" type="unknown"/>
+          <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="i_n64_si_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="io_avr_mosi" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="2" type="unknown"/>
         </unified_setup_data_view>
         <data_view>
-          <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
-          <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="66" type="unknown"/>
-          <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="65" type="unknown"/>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="25" type="unknown"/>
-            <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="24" type="unknown"/>
-            <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="22" type="unknown"/>
-            <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="21" type="unknown"/>
-            <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="20" type="unknown"/>
-            <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="19" type="unknown"/>
-            <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="18" type="unknown"/>
-            <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="17" type="unknown"/>
-            <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="16" type="unknown"/>
-            <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="15" type="unknown"/>
-            <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="14" type="unknown"/>
-            <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="13" type="unknown"/>
-            <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="11" type="unknown"/>
-            <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="10" type="unknown"/>
-            <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="9" type="unknown"/>
-            <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="8" type="unknown"/>
-            <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="7" type="unknown"/>
-            <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="6" type="unknown"/>
-            <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="5" type="unknown"/>
-            <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="4" type="unknown"/>
-            <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="3" type="unknown"/>
-            <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="2" type="unknown"/>
-            <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="32" type="unknown"/>
-            <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="31" type="unknown"/>
-            <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="30" type="unknown"/>
-            <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="29" type="unknown"/>
-            <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="28" type="unknown"/>
-            <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="27" type="unknown"/>
-            <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="26" type="unknown"/>
-            <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="23" type="unknown"/>
-            <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="12" type="unknown"/>
-            <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="1" type="unknown"/>
-          </bus>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="57" type="unknown"/>
-            <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="56" type="unknown"/>
-            <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="54" type="unknown"/>
-            <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="53" type="unknown"/>
-            <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="52" type="unknown"/>
-            <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="51" type="unknown"/>
-            <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="50" type="unknown"/>
-            <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="49" type="unknown"/>
-            <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="48" type="unknown"/>
-            <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="47" type="unknown"/>
-            <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="46" type="unknown"/>
-            <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="45" type="unknown"/>
-            <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="43" type="unknown"/>
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-            <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="41" type="unknown"/>
-            <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="40" type="unknown"/>
-            <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="39" type="unknown"/>
-            <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="38" type="unknown"/>
-            <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="37" type="unknown"/>
-            <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="36" type="unknown"/>
-            <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="35" type="unknown"/>
-            <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="34" type="unknown"/>
-            <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="64" type="unknown"/>
-            <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="63" type="unknown"/>
-            <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="62" type="unknown"/>
-            <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="61" type="unknown"/>
-            <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="60" type="unknown"/>
-            <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="59" type="unknown"/>
-            <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="58" type="unknown"/>
-            <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="55" type="unknown"/>
-            <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="44" type="unknown"/>
-            <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="33" type="unknown"/>
-          </bus>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="102" type="unknown"/>
-            <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="101" type="unknown"/>
-            <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="100" type="unknown"/>
-            <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="99" type="unknown"/>
-          </bus>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="91" type="unknown"/>
-            <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="90" type="unknown"/>
-            <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="88" type="unknown"/>
-            <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="87" type="unknown"/>
-            <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="86" type="unknown"/>
-            <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="85" type="unknown"/>
-            <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="84" type="unknown"/>
-            <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="83" type="unknown"/>
-            <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="82" type="unknown"/>
-            <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="81" type="unknown"/>
-            <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="80" type="unknown"/>
-            <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="79" type="unknown"/>
-            <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="77" type="unknown"/>
-            <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="76" type="unknown"/>
-            <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="75" type="unknown"/>
-            <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="74" type="unknown"/>
-            <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="73" type="unknown"/>
-            <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="72" type="unknown"/>
-            <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="71" type="unknown"/>
-            <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="70" type="unknown"/>
-            <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="69" type="unknown"/>
-            <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="68" type="unknown"/>
-            <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="98" type="unknown"/>
-            <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="97" type="unknown"/>
-            <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="96" type="unknown"/>
-            <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="95" type="unknown"/>
-            <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="94" type="unknown"/>
-            <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="93" type="unknown"/>
-            <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="92" type="unknown"/>
-            <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="89" type="unknown"/>
-            <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="78" type="unknown"/>
-            <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="67" type="unknown"/>
-          </bus>
-          <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="103" type="unknown"/>
+          <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="i_n64_reset" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="io_n64_cic_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="3" type="unknown"/>
+          <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="io_n64_cic_dq" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="4" type="unknown"/>
+          <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="i_n64_si_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="io_avr_mosi" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="2" type="unknown"/>
         </data_view>
         <setup_view>
-          <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_soc_if.led" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
-          <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="66" type="unknown"/>
-          <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_ready" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="65" type="unknown"/>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="25" type="unknown"/>
-            <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="24" type="unknown"/>
-            <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="22" type="unknown"/>
-            <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="21" type="unknown"/>
-            <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="20" type="unknown"/>
-            <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="19" type="unknown"/>
-            <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="18" type="unknown"/>
-            <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="17" type="unknown"/>
-            <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="16" type="unknown"/>
-            <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="15" type="unknown"/>
-            <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="14" type="unknown"/>
-            <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="13" type="unknown"/>
-            <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="11" type="unknown"/>
-            <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="10" type="unknown"/>
-            <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="9" type="unknown"/>
-            <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="8" type="unknown"/>
-            <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="7" type="unknown"/>
-            <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="6" type="unknown"/>
-            <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="5" type="unknown"/>
-            <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="4" type="unknown"/>
-            <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="3" type="unknown"/>
-            <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="2" type="unknown"/>
-            <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="32" type="unknown"/>
-            <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="31" type="unknown"/>
-            <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="30" type="unknown"/>
-            <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="29" type="unknown"/>
-            <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="28" type="unknown"/>
-            <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="27" type="unknown"/>
-            <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="26" type="unknown"/>
-            <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="23" type="unknown"/>
-            <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="12" type="unknown"/>
-            <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <net data_index="37" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="falling edge" name="o_usb_cs" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="37" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="io_usb_miosi[3..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="bidir pin">
+            <net data_index="35" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="io_usb_miosi[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="35" type="unknown"/>
+            <net data_index="34" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="io_usb_miosi[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="34" type="unknown"/>
+            <net data_index="33" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="io_usb_miosi[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="33" type="unknown"/>
+            <net data_index="32" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="io_usb_miosi[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="32" type="unknown"/>
           </bus>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="57" type="unknown"/>
-            <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="56" type="unknown"/>
-            <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="54" type="unknown"/>
-            <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="53" type="unknown"/>
-            <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="52" type="unknown"/>
-            <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="51" type="unknown"/>
-            <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="50" type="unknown"/>
-            <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="49" type="unknown"/>
-            <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="48" type="unknown"/>
-            <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="47" type="unknown"/>
-            <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="46" type="unknown"/>
-            <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="45" type="unknown"/>
-            <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="43" type="unknown"/>
-            <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="42" type="unknown"/>
-            <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="41" type="unknown"/>
-            <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="40" type="unknown"/>
-            <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="39" type="unknown"/>
-            <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="38" type="unknown"/>
-            <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="37" type="unknown"/>
-            <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="36" type="unknown"/>
-            <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="35" type="unknown"/>
-            <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="34" type="unknown"/>
-            <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="64" type="unknown"/>
-            <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="63" type="unknown"/>
-            <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="62" type="unknown"/>
-            <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="61" type="unknown"/>
-            <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="60" type="unknown"/>
-            <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="59" type="unknown"/>
-            <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="58" type="unknown"/>
-            <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="55" type="unknown"/>
-            <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="44" type="unknown"/>
-            <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_rdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="33" type="unknown"/>
+          <net data_index="31" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="i_usb_miso" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="31" type="unknown"/>
+          <net data_index="15" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|output_enable" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <net data_index="28" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/>
+            <net data_index="27" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/>
+            <net data_index="26" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/>
           </bus>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="102" type="unknown"/>
-            <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="101" type="unknown"/>
-            <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="100" type="unknown"/>
-            <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wstrb[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="99" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <net data_index="14" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/>
+            <net data_index="13" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/>
+            <net data_index="12" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/>
+            <net data_index="11" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|clock_divider[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/>
           </bus>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="91" type="unknown"/>
-            <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="90" type="unknown"/>
-            <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="88" type="unknown"/>
-            <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="87" type="unknown"/>
-            <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="86" type="unknown"/>
-            <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="85" type="unknown"/>
-            <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="84" type="unknown"/>
-            <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="83" type="unknown"/>
-            <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="82" type="unknown"/>
-            <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="81" type="unknown"/>
-            <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="80" type="unknown"/>
-            <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="79" type="unknown"/>
-            <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="77" type="unknown"/>
-            <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="76" type="unknown"/>
-            <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="75" type="unknown"/>
-            <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="74" type="unknown"/>
-            <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="73" type="unknown"/>
-            <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="72" type="unknown"/>
-            <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="71" type="unknown"/>
-            <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="70" type="unknown"/>
-            <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="69" type="unknown"/>
-            <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="68" type="unknown"/>
-            <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="98" type="unknown"/>
-            <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="97" type="unknown"/>
-            <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="96" type="unknown"/>
-            <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="95" type="unknown"/>
-            <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="94" type="unknown"/>
-            <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="93" type="unknown"/>
-            <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="92" type="unknown"/>
-            <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="89" type="unknown"/>
-            <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="78" type="unknown"/>
-            <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_wdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="67" type="unknown"/>
+          <net data_index="10" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|bit_counter" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/>
+          <net data_index="24" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|request" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/>
+          <net data_index="25" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rx_available" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/>
+          <net data_index="29" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|tx_available" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/>
+          <net data_index="30" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/>
+          <net data_index="9" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|ack" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <net data_index="8" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
+            <net data_index="7" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
+            <net data_index="6" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
+            <net data_index="5" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <net data_index="4" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <net data_index="3" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <net data_index="2" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
+            <net data_index="1" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|rx_data[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
           </bus>
-          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
-            <net data_index="1" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|intel_snp:intel_snp_inst|source[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <net data_index="0" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|cpu_bus_if.req" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
+            <net data_index="23" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/>
+            <net data_index="22" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/>
+            <net data_index="21" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/>
+            <net data_index="20" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/>
+            <net data_index="19" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/>
+            <net data_index="18" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/>
+            <net data_index="17" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/>
+            <net data_index="16" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="cpu_soc:cpu_soc_inst|cpu_usb:cpu_usb_inst|usb_ft1248:usb_ft1248_inst|rdata[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/>
           </bus>
-          <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="cpu_soc:cpu_soc_inst|picorv32:cpu_inst|resetn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="103" type="unknown"/>
+          <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="low" name="i_n64_reset" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="io_n64_cic_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="3" type="unknown"/>
+          <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="io_n64_cic_dq" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="4" type="unknown"/>
+          <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="i_n64_si_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="io_avr_mosi" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="2" type="unknown"/>
         </setup_view>
         <trigger_in_editor/>
         <trigger_out_editor/>
       </presentation>
-      <trigger CRC="8B574246" attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2021/08/05 17:55:26  #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1024" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
+      <trigger CRC="467B99D8" attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2021/08/12 15:08:58  #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="65536" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
         <power_up_trigger position="pre" storage_qualifier_disabled="no"/>
         <events use_custom_flow_control="no">
-          <level enabled="yes" name="condition1" type="basic">'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[0]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[10]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[11]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[12]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[13]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[14]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[15]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[16]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[17]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[18]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[19]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[1]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[20]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[21]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[22]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[23]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[24]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[25]' == high &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[26]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[27]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[28]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[29]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[2]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[30]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[31]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[3]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[4]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[5]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[6]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[7]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[8]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_addr[9]' == low &amp;&amp; 'cpu_soc:cpu_soc_inst|picorv32:cpu_inst|mem_valid' == rising edge
+          <level enabled="yes" name="condition1" type="basic">'i_n64_reset' == low &amp;&amp; 'io_n64_cic_dq' == rising edge
             <power_up enabled="yes">
             </power_up>
             <op_node/>
           </level>
         </events>
         <storage_qualifier_events>
-          <transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
-            <pwr_up_transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional>
+          <transitional>111111111111111111111111111111111111111111
+            <pwr_up_transitional>111111111111111111111111111111111111111111</pwr_up_transitional>
           </transitional>
           <storage_qualifier_level type="basic">
             <power_up>
@@ -722,8 +229,8 @@
           </storage_qualifier_level>
         </storage_qualifier_events>
         <log>
-          <data global_temp="1" name="log: Trig @ 2021/08/05 18:09:40 (0:0:1.3 elapsed)" power_up_mode="false" sample_depth="1023" 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         </log>
       </trigger>
     </signal_set>
@@ -738,7 +245,8 @@
     <single attribute="instance widget visible" value="1"/>
     <single attribute="jtag widget visible" value="1"/>
     <single attribute="lock mode" value="0"/>
-    <multi attribute="frame size" size="2" value="1675,673"/>
+    <multi attribute="column width" size="23" value="34,34,220,74,52,78,95,96,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
+    <multi attribute="frame size" size="2" value="1053,1378"/>
     <multi attribute="jtag widget size" size="2" value="348,135"/>
   </global_info>
 </session>
diff --git a/sw/bootloader/Makefile b/sw/bootloader/Makefile
index e5f47be..52e5383 100644
--- a/sw/bootloader/Makefile
+++ b/sw/bootloader/Makefile
@@ -16,7 +16,7 @@ HEADER_NAME = header
 
 PROG_NAME = SummerLoader64
 
-ROM_SIZE = 90k
+ROM_SIZE = 1k
 
 SOURCE_DIR = src
 BUILD_DIR = build
@@ -31,7 +31,7 @@ VPATH = $(SRC_DIRS)
 
 COMMONFLAGS = -march=vr4300 -mtune=vr4300
 ASFLAGS = $(COMMONFLAGS)
-CFLAGS = $(COMMONFLAGS) -std=gnu99 -Os -Wall -I$(ROOTDIR)/mips64-elf/include $(INC_DIRS)
+CFLAGS = $(COMMONFLAGS) -std=gnu11 -Os -Wall -I$(ROOTDIR)/mips64-elf/include $(INC_DIRS)
 LINK_FLAGS = -L$(ROOTDIR)/mips64-elf/lib -ldragon -lc -lm -ldragonsys -Tn64.ld -L./libsc64/lib -lsc64_libdragon
 N64_FLAGS = -l $(ROM_SIZE) -h $(HEADER_PATH)/$(HEADER_NAME) -o $(BUILD_DIR)/$(PROG_NAME).z64
 N64_FLAGS_PADDED = -l 1028k -h $(HEADER_PATH)/$(HEADER_NAME) -o $(BUILD_DIR)/$(PROG_NAME)_padded.z64
diff --git a/sw/bootloader/src/boot/boot.h b/sw/bootloader/src/boot/boot.h
index 430e08c..17a0911 100644
--- a/sw/bootloader/src/boot/boot.h
+++ b/sw/bootloader/src/boot/boot.h
@@ -12,9 +12,9 @@ struct cart_header_s {
     uint32_t release_addr;
     uint32_t crc_1;
     uint32_t crc_2;
-    uint32_t __unused_1[2];
+    uint32_t ___unused_1[2];
     char name[20];
-    uint32_t __unused_2;
+    uint32_t ___unused_2;
     uint32_t format;
     char id[2];
     char country_code;
@@ -33,7 +33,7 @@ struct os_boot_config_s {
     uint32_t version;
     uint32_t mem_size;
     uint8_t app_nmi_buffer[64];
-    uint32_t __unused[37];
+    uint32_t ___unused[37];
     uint32_t mem_size_6105;
 } __attribute__((packed, aligned(1)));
 
diff --git a/sw/bootloader/src/sc64/sc64_regs.h b/sw/bootloader/src/sc64/sc64_regs.h
index ab56e5a..21f4fdf 100644
--- a/sw/bootloader/src/sc64/sc64_regs.h
+++ b/sw/bootloader/src/sc64/sc64_regs.h
@@ -26,7 +26,7 @@ typedef struct sc64_cart_registers {
     __IO reg_t USB_DMA_LEN;                 // USB transfer length for DMA to PC
     __IO reg_t DDIPL_ADDR;                  // 64 Disk Drive IPL location in SDRAM
     __IO reg_t SRAM_ADDR;                   // SRAM save emulation location in SDRAM
-    __IO reg_t __unused[1015];
+    __IO reg_t ___unused[1015];
     __IO reg_t USB_FIFO[1024];              // USB data from PC read FIFO memory end
 } sc64_cart_registers_t;
 
@@ -117,7 +117,7 @@ typedef struct sc64_sd_registers_s {
     __IO reg_t DMA_SCR;                     // DMA status and configuration
     __IO reg_t DMA_ADDR;                    // DMA current address
     __IO reg_t DMA_LEN;                     // DMA remaining length
-    __IO reg_t __unused[120];
+    __IO reg_t ___unused[120];
     __IO reg_t FIFO[128];                   // SD data path FIFO buffer
 } sc64_sd_registers_t;