diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 0aa8995..4da4db4 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -22,7 +22,7 @@ jobs:
           submodules: true
 
       - name: Build script
-        run: ./docker_build.sh release
+        run: ./docker_build.sh release --force-clean
 
       - name: Upload artifact
         uses: actions/upload-artifact@v2
diff --git a/.gitmodules b/.gitmodules
index cebf992..e1371e8 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,4 +1,4 @@
-[submodule "fw/cpu/picorv32"]
+[submodule "fw/picorv32"]
 	path = fw/picorv32
 	url = https://github.com/cliffordwolf/picorv32.git
 	ignore = dirty
diff --git a/build.sh b/build.sh
index c8aa6c9..35ad2ba 100755
--- a/build.sh
+++ b/build.sh
@@ -19,6 +19,9 @@ BUILT_FPGA=false
 BUILT_UPDATE=false
 BUILT_RELEASE=false
 
+FORCE_CLEAN=false
+SKIP_FPGA_REBUILD=false
+
 build_cic () {
     if [ "$BUILT_CIC" = true ]; then return; fi
 
@@ -33,7 +36,10 @@ build_n64 () {
     if [ "$BUILT_N64" = true ]; then return; fi
 
     pushd sw/n64
-    make clean all
+    if [ "$FORCE_CLEAN" = true ]; then
+        make clean
+    fi
+    make all
     popd
 
     BUILT_N64=true
@@ -43,7 +49,10 @@ build_riscv () {
     if [ "$BUILT_RISCV" = true ]; then return; fi
 
     pushd sw/riscv
-    make clean all
+    if [ "$FORCE_CLEAN" = true ]; then
+        make clean
+    fi
+    make all
     popd
 
     BUILT_RISCV=true
@@ -56,7 +65,12 @@ build_fpga () {
     build_riscv
 
     pushd fw
-    quartus_sh --flow compile ./SummerCart64.qpf
+    if [ "$SKIP_FPGA_REBUILD" = true ] && [ -f output_files/SummerCart64.done ]; then
+        quartus_asm SummerCart64
+        quartus_cpf -c SummerCart64.cof
+    else
+        quartus_sh --flow compile ./SummerCart64.qpf
+    fi
     popd
 
     BUILT_FPGA=true
@@ -92,15 +106,19 @@ build_release () {
 
 print_usage () {
     echo "builder script for SummerCart64"
-    echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [--help]"
+    echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [-c] [-s] [--help]"
     echo "parameters:"
-    echo "  cic - assemble UltraCIC-III software"
-    echo "  n64 - compile N64 bootloader software"
-    echo "  riscv - compile cart governor software"
-    echo "  fpga - compile FPGA design (triggers 'n64' and 'riscv' build)"
-    echo "  update - convert programming .pof file to raw binary for user upgrade (triggers 'fpga' build)"
-    echo "  release - collect and zip files for release (triggers 'cic' and 'update' build)"
-    echo "  --help - print this guide"
+    echo "  cic       - assemble UltraCIC-III software"
+    echo "  n64       - compile N64 bootloader software"
+    echo "  riscv     - compile cart governor software"
+    echo "  fpga      - compile FPGA design (triggers 'n64' and 'riscv' build)"
+    echo "  update    - convert programming .pof file to raw binary for self-upgrade (triggers 'fpga' build)"
+    echo "  release   - collect and zip files for release (triggers 'cic' and 'update' build)"
+    echo "  -c | --force-clean"
+    echo "            - clean software compilation result directories before build"
+    echo "  -s | --skip-fpga-rebuild"
+    echo "            - do not recompile whole FPGA design if it's already done, just update software binaries"
+    echo "  --help    - print this guide"
 }
 
 if test $# -eq 0; then
@@ -137,6 +155,12 @@ while test $# -gt 0; do
         release)
             TRIGGER_RELEASE=true
             ;;
+        -c|--force-clean)
+            FORCE_CLEAN=true
+            ;;
+        -s|--skip-fpga-rebuild)
+            SKIP_FPGA_REBUILD=true
+            ;;
         --help)
             print_usage
             exit 0
diff --git a/fw/SummerCart64.qsf b/fw/SummerCart64.qsf
index b0b22b8..f0d8761 100644
--- a/fw/SummerCart64.qsf
+++ b/fw/SummerCart64.qsf
@@ -19,7 +19,7 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 23:52:20  November 09, 2021
+# Date created = 13:29:40  November 11, 2021
 #
 # -------------------------------------------------------------------------- #
 #
@@ -83,7 +83,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/config.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
-set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:scripts/post_flow.tcl"
+set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/post_module.tcl"
 
 # Pin & Location Assignments
 # ==========================
@@ -289,22 +289,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 	# -------------------------
 
 # end ENTITY(SummerCart64)
-# ------------------------
-
-# ------------------------------
-# start ENTITY(altera_gpio_lite)
-
-	# Project-Wide Assignments
-	# ========================
-
-# end ENTITY(altera_gpio_lite)
-# ----------------------------
-
-# -----------------------------
-# start ENTITY(intel_gpio_ddro)
-
-	# Project-Wide Assignments
-	# ========================
-
-# end ENTITY(intel_gpio_ddro)
-# ---------------------------
\ No newline at end of file
+# ------------------------
\ No newline at end of file
diff --git a/fw/scripts/post_flow.tcl b/fw/scripts/post_module.tcl
similarity index 74%
rename from fw/scripts/post_flow.tcl
rename to fw/scripts/post_module.tcl
index 9fa437e..ed19714 100644
--- a/fw/scripts/post_flow.tcl
+++ b/fw/scripts/post_module.tcl
@@ -1,6 +1,6 @@
 set flow [lindex $quartus(args) 0]
 
-if [string match "compile" $flow] {
+if [string match "quartus_asm" $flow] {
     post_message "Generating final programming file"
     qexec "quartus_cpf -c SummerCart64.cof"
 }