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https://github.com/Polprzewodnikowy/SummerCart64.git
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[SC64][SW] Removed IPL3 version bit spoofing
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@ -9,23 +9,22 @@ extern uint32_t ipl2 __attribute__((section(".data")));
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typedef struct {
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const uint32_t crc32;
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const uint8_t seed;
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const uint8_t version;
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} ipl3_crc32_t;
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static const ipl3_crc32_t ipl3_crc32[] = {
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{ .crc32 = 0x587BD543, .seed = 0xAC, .version = 0 }, // 5101
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{ .crc32 = 0x6170A4A1, .seed = 0x3F, .version = 1 }, // 6101
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{ .crc32 = 0x009E9EA3, .seed = 0x3F, .version = 1 }, // 7102
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{ .crc32 = 0x90BB6CB5, .seed = 0x3F, .version = 0 }, // x102
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{ .crc32 = 0x0B050EE0, .seed = 0x78, .version = 0 }, // x103
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{ .crc32 = 0x98BC2C86, .seed = 0x91, .version = 0 }, // x105
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{ .crc32 = 0xACC8580A, .seed = 0x85, .version = 0 }, // x106
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{ .crc32 = 0x0E018159, .seed = 0xDD, .version = 0 }, // 5167
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{ .crc32 = 0x10C68B18, .seed = 0xDD, .version = 0 }, // NDXJ0
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{ .crc32 = 0xBC605D0A, .seed = 0xDD, .version = 0 }, // NDDJ0
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{ .crc32 = 0x502C4466, .seed = 0xDD, .version = 0 }, // NDDJ1
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{ .crc32 = 0x0C965795, .seed = 0xDD, .version = 0 }, // NDDJ2
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{ .crc32 = 0x8FEBA21E, .seed = 0xDE, .version = 0 }, // NDDE0
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{ .crc32 = 0x587BD543, .seed = 0xAC }, // 5101
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{ .crc32 = 0x6170A4A1, .seed = 0x3F }, // 6101
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{ .crc32 = 0x009E9EA3, .seed = 0x3F }, // 7102
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{ .crc32 = 0x90BB6CB5, .seed = 0x3F }, // x102
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{ .crc32 = 0x0B050EE0, .seed = 0x78 }, // x103
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{ .crc32 = 0x98BC2C86, .seed = 0x91 }, // x105
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{ .crc32 = 0xACC8580A, .seed = 0x85 }, // x106
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{ .crc32 = 0x0E018159, .seed = 0xDD }, // 5167
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{ .crc32 = 0x10C68B18, .seed = 0xDD }, // NDXJ0
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{ .crc32 = 0xBC605D0A, .seed = 0xDD }, // NDDJ0
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{ .crc32 = 0x502C4466, .seed = 0xDD }, // NDDJ1
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{ .crc32 = 0x0C965795, .seed = 0xDD }, // NDDJ2
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{ .crc32 = 0x8FEBA21E, .seed = 0xDE }, // NDDE0
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};
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@ -64,7 +63,7 @@ static bool boot_get_tv_type (boot_info_t *info) {
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return true;
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}
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static bool boot_get_cic_seed_version (boot_info_t *info) {
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static bool boot_get_cic_seed (boot_info_t *info) {
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io32_t *base = boot_get_device_base(info);
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uint32_t ipl3[1008] __attribute__((aligned(8)));
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@ -76,7 +75,6 @@ static bool boot_get_cic_seed_version (boot_info_t *info) {
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for (int i = 0; i < sizeof(ipl3_crc32) / sizeof(ipl3_crc32_t); i++) {
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if (ipl3_crc32[i].crc32 == crc32) {
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info->cic_seed = ipl3_crc32[i].seed;
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info->version = ipl3_crc32[i].version;
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return true;
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}
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}
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@ -84,14 +82,13 @@ static bool boot_get_cic_seed_version (boot_info_t *info) {
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return false;
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}
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void boot (boot_info_t *info, bool detect_tv_type, bool detect_cic_seed_version) {
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void boot (boot_info_t *info, bool detect_tv_type, bool detect_cic_seed) {
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if (detect_tv_type && !boot_get_tv_type(info)) {
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info->tv_type = OS_INFO->tv_type;
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}
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if (detect_cic_seed_version && !boot_get_cic_seed_version(info)) {
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if (detect_cic_seed && !boot_get_cic_seed(info)) {
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info->cic_seed = 0x3F;
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info->version = 0;
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}
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OS_INFO->mem_size_6105 = OS_INFO->mem_size;
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@ -149,7 +146,7 @@ void boot (boot_info_t *info, bool detect_tv_type, bool detect_cic_seed_version)
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tv_type = (info->tv_type & 0x03);
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reset_type = (info->reset_type & 0x01);
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cic_seed = (info->cic_seed & 0xFF);
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version = (info->version & 0x01);
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version = 1;
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stack_pointer = (void *) UNCACHED(&SP_MEM->IMEM[1020]);
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asm volatile (
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@ -28,11 +28,10 @@ typedef struct {
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boot_reset_type_t reset_type;
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boot_tv_type_t tv_type;
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uint8_t cic_seed;
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uint8_t version;
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} boot_info_t;
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void boot (boot_info_t *info, bool detect_tv_type, bool detect_cic_seed_version);
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void boot (boot_info_t *info, bool detect_tv_type, bool detect_cic_seed);
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#endif
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@ -31,14 +31,13 @@ void main (void) {
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}
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bool detect_tv_type = (sc64_boot_info.tv_type == TV_TYPE_UNKNOWN);
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bool detect_cic_seed_version = (sc64_boot_info.cic_seed == CIC_SEED_UNKNOWN);
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bool detect_cic_seed = (sc64_boot_info.cic_seed == CIC_SEED_UNKNOWN);
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boot_info.reset_type = OS_INFO->reset_type;
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boot_info.tv_type = sc64_boot_info.tv_type;
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boot_info.cic_seed = sc64_boot_info.cic_seed & 0xFF;
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boot_info.version = (sc64_boot_info.cic_seed >> 8) & 0x01;
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boot_info.cic_seed = (sc64_boot_info.cic_seed & 0xFF);
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deinit();
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boot(&boot_info, detect_tv_type, detect_cic_seed_version);
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boot(&boot_info, detect_tv_type, detect_cic_seed);
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}
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@ -293,12 +293,11 @@ class SC64:
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SRAM_3X = 5
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class CICSeed(IntEnum):
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ALECK = 0xAC
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X101 = 0x13F
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X102 = 0x3F
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DEFAULT = 0x3F
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X103 = 0x78
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X105 = 0x91
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X106 = 0x85
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ALECK = 0xAC
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DD_JP = 0xDD
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DD_US = 0xDE
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AUTO = 0xFFFF
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@ -487,7 +486,7 @@ class SC64:
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def set_cic_seed(self, seed: int) -> None:
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if (seed != self.CICSeed.AUTO):
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if (seed < 0 or seed > 0x1FF):
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if (seed < 0 or seed > 0xFF):
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raise ValueError('CIC seed outside of allowed values')
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self.__set_config(self.__CfgId.CIC_SEED, seed)
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