mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
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mid stage
This commit is contained in:
Polprzewodnikowy
parent
68aab4b4a0
commit
62ef41799f
@ -19,7 +19,7 @@
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#
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# Quartus Prime
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# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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# Date created = 00:00:00 November 06, 2020
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# Date created = 23:45:19 July 29, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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@ -47,6 +47,7 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
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set_global_assignment -name SMART_RECOMPILE OFF
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set_global_assignment -name NUM_PARALLEL_PROCESSORS 16
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set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo_sd.qip
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set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo_usb.qip
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set_global_assignment -name QIP_FILE rtl/intel/gpio/gpio_ddro.qip
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set_global_assignment -name QIP_FILE rtl/intel/pll/pll.qip
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@ -54,6 +55,7 @@ set_global_assignment -name QIP_FILE rtl/intel/ram/ram_n64_eeprom.qip
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set_global_assignment -name QSYS_FILE rtl/intel/flash/onchip_flash.qsys
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set_global_assignment -name SDC_FILE constraints.sdc
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set_global_assignment -name SIGNALTAP_FILE output_files/signal_tap_logic_analyzer.stp
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set_global_assignment -name SLD_FILE db/signal_tap_logic_analyzer_auto_stripped.stp
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv -library gpio_ddro
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set_global_assignment -name VERILOG_FILE rtl/cart/cart_control.v
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set_global_assignment -name VERILOG_FILE rtl/cart/cart_led.v
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@ -76,7 +78,6 @@ set_global_assignment -name VERILOG_FILE rtl/top.v
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set_global_assignment -name VERILOG_FILE rtl/usb/usb_ftdi_fsi.v
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set_global_assignment -name VERILOG_FILE rtl/usb/usb_pc.v
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set_global_assignment -name VERILOG_INCLUDE_FILE rtl/constants.vh
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set_global_assignment -name SLD_FILE db/signal_tap_logic_analyzer_auto_stripped.stp
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# Pin & Location Assignments
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# ==========================
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@ -263,10 +264,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq
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set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to i_clk
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set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "pll:sys_pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]"
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set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "pll:sys_pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]"
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set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "sd_interface:sd_interface_inst|sd_clk:sd_clk_inst|o_sd_clk|q"
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# start DESIGN_PARTITION(Top)
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# ---------------------------
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@ -4,22 +4,11 @@ derive_pll_clocks -create_base_clocks
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set sys_clk {sys_pll|altpll_component|auto_generated|pll1|clk[0]}
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set sdram_pll_clk {sys_pll|altpll_component|auto_generated|pll1|clk[1]}
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set sd_reg_clk {sd_interface_inst|sd_clk_inst|o_sd_clk|q}
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create_generated_clock -name sdram_clk \
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-source [get_pins $sdram_pll_clk] \
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-master_clock $sdram_pll_clk \
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[get_ports {o_sdram_clk}]
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create_generated_clock -name sd_generated_clk \
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-source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] \
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-divide_by 2 \
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-master_clock $sys_clk \
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[get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|q}]
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create_generated_clock -name sd_clk \
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-source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|q}] \
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-master_clock [get_clocks {sd_generated_clk}] \
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[get_ports {o_sd_clk}]
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create_generated_clock -name sdram_clk -source [get_pins $sdram_pll_clk] [get_ports {o_sdram_clk}]
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create_generated_clock -name sd_reg_clk -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] -divide_by 2 [get_pins $sd_reg_clk]
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create_generated_clock -name sd_clk -source [get_pins $sd_reg_clk] [get_ports {o_sd_clk}]
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create_generated_clock -name flash_se_neg_reg \
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-source [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk}] \
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@ -51,11 +40,11 @@ set_false_path -from [get_ports {i_ftdi_so i_ftdi_cts}]
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# SD card timings
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set_output_delay -clock [get_clocks {sd_clk}] -max 7.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
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set_output_delay -clock [get_clocks {sd_clk}] -min -3.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
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set_output_delay -clock [get_clocks {sd_clk}] -max 6.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
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set_output_delay -clock [get_clocks {sd_clk}] -min -2.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
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set_input_delay -clock [get_clocks {sd_clk}] -max 15.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
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set_input_delay -clock [get_clocks {sd_clk}] -min 4.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
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set_input_delay -clock [get_clocks {sd_clk}] -max 14.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
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set_input_delay -clock [get_clocks {sd_clk}] -min 2.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
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set_multicycle_path -setup -start 1 -from [get_clocks $sys_clk] -to [get_clocks {sd_clk}]
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set_multicycle_path -hold -start 1 -from [get_clocks $sys_clk] -to [get_clocks {sd_clk}]
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4
fw/rtl/intel/fifo/fifo_sd.qip
Normal file
4
fw/rtl/intel/fifo/fifo_sd.qip
Normal file
@ -0,0 +1,4 @@
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set_global_assignment -name IP_TOOL_NAME "FIFO"
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set_global_assignment -name IP_TOOL_VERSION "20.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_sd.v"]
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169
fw/rtl/intel/fifo/fifo_sd.v
Normal file
169
fw/rtl/intel/fifo/fifo_sd.v
Normal file
@ -0,0 +1,169 @@
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// megafunction wizard: %FIFO%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: scfifo
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// ============================================================
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// File Name: fifo_sd.v
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// Megafunction Name(s):
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// scfifo
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2020 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and any partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details, at
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//https://fpgasoftware.intel.com/eula.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module fifo_sd (
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clock,
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data,
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rdreq,
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sclr,
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wrreq,
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empty,
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full,
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q,
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usedw);
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input clock;
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input [31:0] data;
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input rdreq;
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input sclr;
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input wrreq;
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output empty;
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output full;
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output [31:0] q;
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output [7:0] usedw;
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wire sub_wire0;
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wire sub_wire1;
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wire [31:0] sub_wire2;
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wire [7:0] sub_wire3;
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wire empty = sub_wire0;
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wire full = sub_wire1;
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wire [31:0] q = sub_wire2[31:0];
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wire [7:0] usedw = sub_wire3[7:0];
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scfifo scfifo_component (
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.clock (clock),
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.data (data),
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.rdreq (rdreq),
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.sclr (sclr),
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.wrreq (wrreq),
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.empty (sub_wire0),
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.full (sub_wire1),
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.q (sub_wire2),
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.usedw (sub_wire3),
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.aclr (),
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.almost_empty (),
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.almost_full (),
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.eccstatus ());
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defparam
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scfifo_component.add_ram_output_register = "ON",
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scfifo_component.intended_device_family = "MAX 10",
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scfifo_component.lpm_numwords = 256,
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scfifo_component.lpm_showahead = "ON",
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scfifo_component.lpm_type = "scfifo",
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scfifo_component.lpm_width = 32,
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scfifo_component.lpm_widthu = 8,
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scfifo_component.overflow_checking = "ON",
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scfifo_component.underflow_checking = "ON",
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scfifo_component.use_eab = "ON";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Depth NUMERIC "256"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
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// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: Optimize NUMERIC "1"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: UsedW NUMERIC "1"
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// Retrieval info: PRIVATE: Width NUMERIC "32"
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// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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// Retrieval info: PRIVATE: output_width NUMERIC "32"
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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// Retrieval info: PRIVATE: rsFull NUMERIC "0"
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// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
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// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: wsFull NUMERIC "1"
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// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
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// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
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// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: USE_EAB STRING "ON"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
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// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
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// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
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// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
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// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
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// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
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// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
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// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
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// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
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// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
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// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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@ -14,41 +14,32 @@ module sd_fifo (
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output [31:0] o_fifo_data
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);
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reg [31:0] r_fifo_mem [0:255];
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wire [7:0] w_fifo_items;
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reg [8:0] r_fifo_wrptr;
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reg [8:0] r_fifo_rdptr;
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assign o_fifo_items = {o_fifo_full, w_fifo_items};
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assign o_fifo_data = r_fifo_mem[r_fifo_rdptr[7:0]];
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wire w_empty = r_fifo_wrptr[8] == r_fifo_rdptr[8];
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wire w_full_or_empty = r_fifo_wrptr[7:0] == r_fifo_rdptr[7:0];
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assign o_fifo_empty = w_empty && w_full_or_empty;
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assign o_fifo_full = !w_empty && w_full_or_empty;
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assign o_fifo_items = r_fifo_wrptr - r_fifo_rdptr;
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fifo_sd fifo_sd_inst (
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.clock(i_clk),
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.sclr(i_reset || i_fifo_flush),
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.wrreq(i_fifo_push),
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.rdreq(i_fifo_pop),
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.empty(o_fifo_empty),
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.full(o_fifo_full),
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.usedw(w_fifo_items),
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.data(i_fifo_data),
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.q(o_fifo_data)
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);
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always @(posedge i_clk) begin
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if (i_reset) begin
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r_fifo_wrptr <= 9'd0;
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r_fifo_rdptr <= 9'd0;
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if (i_reset || i_fifo_flush) begin
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o_fifo_underrun <= 1'b0;
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o_fifo_overrun <= 1'b0;
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end else begin
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if (i_fifo_flush) begin
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r_fifo_wrptr <= 9'd0;
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r_fifo_rdptr <= 9'd0;
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o_fifo_underrun <= 1'b0;
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o_fifo_overrun <= 1'b0;
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if (o_fifo_empty && i_fifo_pop) begin
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o_fifo_underrun <= 1'b1;
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end
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if (i_fifo_push) begin
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o_fifo_overrun <= o_fifo_overrun ? 1'b1 : o_fifo_full;
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r_fifo_mem[r_fifo_wrptr[7:0]] <= i_fifo_data;
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r_fifo_wrptr <= r_fifo_wrptr + 1'd1;
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end
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if (i_fifo_pop) begin
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o_fifo_underrun <= o_fifo_underrun ? 1'b1 : o_fifo_empty;
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r_fifo_rdptr <= r_fifo_rdptr + 1'd1;
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if (o_fifo_full && i_fifo_push) begin
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o_fifo_overrun <= 1'b1;
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end
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end
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end
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