mid stage

fw/SummerCart64.qsf

@@ -19,7 +19,7 @@
 #
 # Quartus Prime
 # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 00:00:00  November 06, 2020
+# Date created = 23:45:19  July 29, 2020
 #
 # -------------------------------------------------------------------------- #
 #
@@ -47,6 +47,7 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
 set_global_assignment -name SMART_RECOMPILE OFF
 set_global_assignment -name NUM_PARALLEL_PROCESSORS 16
+set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo_sd.qip
 set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo_usb.qip
 set_global_assignment -name QIP_FILE rtl/intel/gpio/gpio_ddro.qip
 set_global_assignment -name QIP_FILE rtl/intel/pll/pll.qip
@@ -54,6 +55,7 @@ set_global_assignment -name QIP_FILE rtl/intel/ram/ram_n64_eeprom.qip
 set_global_assignment -name QSYS_FILE rtl/intel/flash/onchip_flash.qsys
 set_global_assignment -name SDC_FILE constraints.sdc
 set_global_assignment -name SIGNALTAP_FILE output_files/signal_tap_logic_analyzer.stp
+set_global_assignment -name SLD_FILE db/signal_tap_logic_analyzer_auto_stripped.stp
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv -library gpio_ddro
 set_global_assignment -name VERILOG_FILE rtl/cart/cart_control.v
 set_global_assignment -name VERILOG_FILE rtl/cart/cart_led.v
@@ -76,7 +78,6 @@ set_global_assignment -name VERILOG_FILE rtl/top.v
 set_global_assignment -name VERILOG_FILE rtl/usb/usb_ftdi_fsi.v
 set_global_assignment -name VERILOG_FILE rtl/usb/usb_pc.v
 set_global_assignment -name VERILOG_INCLUDE_FILE rtl/constants.vh
-set_global_assignment -name SLD_FILE db/signal_tap_logic_analyzer_auto_stripped.stp
 
 # Pin & Location Assignments
 # ==========================
@@ -263,10 +264,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq
-	set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to i_clk
-	set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "pll:sys_pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]"
-	set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "pll:sys_pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]"
-	set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "sd_interface:sd_interface_inst|sd_clk:sd_clk_inst|o_sd_clk|q"
 
 	# start DESIGN_PARTITION(Top)
 	# ---------------------------

fw/constraints.sdc

@@ -4,22 +4,11 @@ derive_pll_clocks -create_base_clocks
 
 set sys_clk {sys_pll|altpll_component|auto_generated|pll1|clk[0]}
 set sdram_pll_clk {sys_pll|altpll_component|auto_generated|pll1|clk[1]}
+set sd_reg_clk {sd_interface_inst|sd_clk_inst|o_sd_clk|q}
 
-create_generated_clock -name sdram_clk \
+create_generated_clock -name sdram_clk -source [get_pins $sdram_pll_clk] [get_ports {o_sdram_clk}]
-    -source [get_pins $sdram_pll_clk] \
+create_generated_clock -name sd_reg_clk -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] -divide_by 2 [get_pins $sd_reg_clk]
-    -master_clock $sdram_pll_clk \
+create_generated_clock -name sd_clk -source [get_pins $sd_reg_clk] [get_ports {o_sd_clk}]
-    [get_ports {o_sdram_clk}]
-
-create_generated_clock -name sd_generated_clk \
-    -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] \
-    -divide_by 2 \
-    -master_clock $sys_clk \
-    [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|q}]
-
-create_generated_clock -name sd_clk \
-    -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|q}] \
-    -master_clock [get_clocks {sd_generated_clk}] \
-    [get_ports {o_sd_clk}]
 
 create_generated_clock -name flash_se_neg_reg \
     -source [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk}] \
@@ -51,11 +40,11 @@ set_false_path -from [get_ports {i_ftdi_so i_ftdi_cts}]
 
 # SD card timings
 
-set_output_delay -clock [get_clocks {sd_clk}] -max 7.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
+set_output_delay -clock [get_clocks {sd_clk}] -max 6.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
-set_output_delay -clock [get_clocks {sd_clk}] -min -3.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
+set_output_delay -clock [get_clocks {sd_clk}] -min -2.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
 
-set_input_delay -clock [get_clocks {sd_clk}] -max 15.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
+set_input_delay -clock [get_clocks {sd_clk}] -max 14.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
-set_input_delay -clock [get_clocks {sd_clk}] -min 4.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
+set_input_delay -clock [get_clocks {sd_clk}] -min 2.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
 
 set_multicycle_path -setup -start 1 -from [get_clocks $sys_clk] -to [get_clocks {sd_clk}]
 set_multicycle_path -hold -start 1 -from [get_clocks $sys_clk] -to [get_clocks {sd_clk}]

fw/rtl/intel/fifo/fifo_sd.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_sd.v"]

fw/rtl/intel/fifo/fifo_sd.v

@@ -0,0 +1,169 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: fifo_sd.v
+// Megafunction Name(s):
+// 			scfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_sd (
+	clock,
+	data,
+	rdreq,
+	sclr,
+	wrreq,
+	empty,
+	full,
+	q,
+	usedw);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	  rdreq;
+	input	  sclr;
+	input	  wrreq;
+	output	  empty;
+	output	  full;
+	output	[31:0]  q;
+	output	[7:0]  usedw;
+
+	wire  sub_wire0;
+	wire  sub_wire1;
+	wire [31:0] sub_wire2;
+	wire [7:0] sub_wire3;
+	wire  empty = sub_wire0;
+	wire  full = sub_wire1;
+	wire [31:0] q = sub_wire2[31:0];
+	wire [7:0] usedw = sub_wire3[7:0];
+
+	scfifo	scfifo_component (
+				.clock (clock),
+				.data (data),
+				.rdreq (rdreq),
+				.sclr (sclr),
+				.wrreq (wrreq),
+				.empty (sub_wire0),
+				.full (sub_wire1),
+				.q (sub_wire2),
+				.usedw (sub_wire3),
+				.aclr (),
+				.almost_empty (),
+				.almost_full (),
+				.eccstatus ());
+	defparam
+		scfifo_component.add_ram_output_register = "ON",
+		scfifo_component.intended_device_family = "MAX 10",
+		scfifo_component.lpm_numwords = 256,
+		scfifo_component.lpm_showahead = "ON",
+		scfifo_component.lpm_type = "scfifo",
+		scfifo_component.lpm_width = 32,
+		scfifo_component.lpm_widthu = 8,
+		scfifo_component.overflow_checking = "ON",
+		scfifo_component.underflow_checking = "ON",
+		scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "32"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
+// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sd_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf

fw/rtl/sd/sd_fifo.v

@@ -14,41 +14,32 @@ module sd_fifo (
     output [31:0] o_fifo_data
 );
 
-    reg [31:0] r_fifo_mem [0:255];
+    wire [7:0] w_fifo_items;
 
-    reg [8:0] r_fifo_wrptr;
+    assign o_fifo_items = {o_fifo_full, w_fifo_items};
-    reg [8:0] r_fifo_rdptr;
 
-    assign o_fifo_data = r_fifo_mem[r_fifo_rdptr[7:0]];
+    fifo_sd fifo_sd_inst (
-
+        .clock(i_clk),
-    wire w_empty = r_fifo_wrptr[8] == r_fifo_rdptr[8];
+        .sclr(i_reset || i_fifo_flush),
-    wire w_full_or_empty = r_fifo_wrptr[7:0] == r_fifo_rdptr[7:0];
+        .wrreq(i_fifo_push),
-
+        .rdreq(i_fifo_pop),
-    assign o_fifo_empty = w_empty && w_full_or_empty;
+        .empty(o_fifo_empty),
-    assign o_fifo_full = !w_empty && w_full_or_empty;
+        .full(o_fifo_full),
-    assign o_fifo_items = r_fifo_wrptr - r_fifo_rdptr;
+        .usedw(w_fifo_items),
+        .data(i_fifo_data),
+        .q(o_fifo_data)
+    );
 
     always @(posedge i_clk) begin
-        if (i_reset) begin
+        if (i_reset || i_fifo_flush) begin
-            r_fifo_wrptr <= 9'd0;
-            r_fifo_rdptr <= 9'd0;
             o_fifo_underrun <= 1'b0;
             o_fifo_overrun <= 1'b0;
         end else begin
-            if (i_fifo_flush) begin
+            if (o_fifo_empty && i_fifo_pop) begin
-                r_fifo_wrptr <= 9'd0;
+                o_fifo_underrun <= 1'b1;
-                r_fifo_rdptr <= 9'd0;
-                o_fifo_underrun <= 1'b0;
-                o_fifo_overrun <= 1'b0;
             end
-            if (i_fifo_push) begin
+            if (o_fifo_full && i_fifo_push) begin
-                o_fifo_overrun <= o_fifo_overrun ? 1'b1 : o_fifo_full;
+                o_fifo_overrun <= 1'b1;
-                r_fifo_mem[r_fifo_wrptr[7:0]] <= i_fifo_data;
-                r_fifo_wrptr <= r_fifo_wrptr + 1'd1;
-            end
-            if (i_fifo_pop) begin
-                o_fifo_underrun <= o_fifo_underrun ? 1'b1 : o_fifo_empty;
-                r_fifo_rdptr <= r_fifo_rdptr + 1'd1;
             end
         end
     end