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moved picorv32

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Polprzewodnikowy 2021-11-09 23:12:29 +01:00
parent e06e6d34ff
commit 68c20c184b
3 changed files with 2 additions and 2 deletions
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2
.gitmodules vendored
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@ -1,5 +1,5 @@
[submodule "fw/cpu/picorv32"] [submodule "fw/cpu/picorv32"]
path = fw/cpu/picorv32 path = fw/picorv32
url = https://github.com/cliffordwolf/picorv32.git url = https://github.com/cliffordwolf/picorv32.git
ignore = dirty ignore = dirty
[submodule "sw/cic"] [submodule "sw/cic"]

2
fw/SummerCart64.qsf
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@ -51,7 +51,7 @@ set_global_assignment -name QIP_FILE rtl/intel/fifo/intel_fifo_8.qip
set_global_assignment -name QIP_FILE rtl/intel/gpio/intel_gpio_ddro.qip set_global_assignment -name QIP_FILE rtl/intel/gpio/intel_gpio_ddro.qip
set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
set_global_assignment -name SDC_FILE SummerCart64.sdc set_global_assignment -name SDC_FILE SummerCart64.sdc
set_global_assignment -name SYSTEMVERILOG_FILE cpu/picorv32/picorv32.v set_global_assignment -name SYSTEMVERILOG_FILE picorv32/picorv32.v
set_global_assignment -name SYSTEMVERILOG_FILE ../sw/riscv/build/cpu_bootloader.sv set_global_assignment -name SYSTEMVERILOG_FILE ../sw/riscv/build/cpu_bootloader.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_cfg.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_cfg.sv

0
fw/cpu/picorv32 → fw/picorv32
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