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cache stuff

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Polprzewodnikowy 2022-09-24 20:02:31 +02:00
parent db97dd31fb
commit 69dda55681
5 changed files with 18 additions and 9 deletions
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10
sw/bootloader/src/exception.S
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@ -175,13 +175,19 @@ exception_install:
add $t5, $t5, $t4 add $t5, $t5, $t4
2: 2:
lw $t6, 0($t3) lw $t6, 0($t3)
sw $t6, 0($t4)
cache HIT_INVALIDATE_I, 0($t4)
addiu $t3, 4 addiu $t3, 4
sw $t6, 0($t4)
addiu $t4, 4 addiu $t4, 4
bne $t4, $t5, 2b bne $t4, $t5, 2b
addiu $t1, VECTOR_SIZE addiu $t1, VECTOR_SIZE
bne $t1, $t2, 1b bne $t1, $t2, 1b
li $t0, VECTOR_LOCATION
li $t1, (VECTOR_SIZE * VECTOR_NUM)
add $t1, $t0, $t1
3:
cache HIT_INVALIDATE_I, 0($t0)
addiu $t0, CACHE_LINE_SIZE_I
bne $t0, $t1, 3b
jr $ra jr $ra

11
sw/bootloader/src/io.c
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@ -1,4 +1,5 @@
#include "io.h" #include "io.h"
#include "vr4300.h"
static void cache_operation (uint8_t operation, uint8_t line_size, void *address, size_t length) { static void cache_operation (uint8_t operation, uint8_t line_size, void *address, size_t length) {
@ -13,16 +14,16 @@ static void cache_operation (uint8_t operation, uint8_t line_size, void *address
} }
} }
void cache_data_hit_invalidate (void *address, size_t length) { void cache_data_hit_writeback_invalidate (void *address, size_t length) {
cache_operation(0x11, 16, address, length); cache_operation(HIT_WRITE_BACK_INVALIDATE_D, CACHE_LINE_SIZE_D, address, length);
} }
void cache_data_hit_writeback (void *address, size_t length) { void cache_data_hit_writeback (void *address, size_t length) {
cache_operation(0x19, 16, address, length); cache_operation(HIT_WRITE_BACK_D, CACHE_LINE_SIZE_D, address, length);
} }
void cache_inst_hit_invalidate (void *address, size_t length) { void cache_inst_hit_invalidate (void *address, size_t length) {
cache_operation(0x10, 32, address, length); cache_operation(HIT_INVALIDATE_I, CACHE_LINE_SIZE_I, address, length);
} }
uint32_t io_read (io32_t *address) { uint32_t io_read (io32_t *address) {
@ -50,11 +51,11 @@ void pi_io_write (io32_t *address, uint32_t value) {
} }
void pi_dma_read (io32_t *address, void *buffer, size_t length) { void pi_dma_read (io32_t *address, void *buffer, size_t length) {
cache_data_hit_writeback_invalidate(buffer, length);
io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address))); io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer))); io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
io_write(&PI->WDMA, length - 1); io_write(&PI->WDMA, length - 1);
while (pi_busy()); while (pi_busy());
cache_data_hit_invalidate(buffer, length);
} }
void pi_dma_write (io32_t *address, void *buffer, size_t length) { void pi_dma_write (io32_t *address, void *buffer, size_t length) {

2
sw/bootloader/src/io.h
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@ -286,7 +286,7 @@ void pi_dma_write (io32_t *address, void *buffer, size_t length);
uint32_t si_busy (void); uint32_t si_busy (void);
uint32_t si_io_read (io32_t *address); uint32_t si_io_read (io32_t *address);
void si_io_write (io32_t *address, uint32_t value); void si_io_write (io32_t *address, uint32_t value);
void cache_data_hit_invalidate (void *address, size_t length); void cache_data_hit_writeback_invalidate (void *address, size_t length);
void cache_data_hit_writeback (void *address, size_t length); void cache_data_hit_writeback (void *address, size_t length);
void cache_inst_hit_invalidate (void *address, size_t length); void cache_inst_hit_invalidate (void *address, size_t length);

1
sw/bootloader/src/startup.S
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@ -40,7 +40,6 @@ bss_init:
la $a1, _ebss la $a1, _ebss
1: 1:
sd $zero, 0($a0) sd $zero, 0($a0)
cache HIT_WRITE_BACK_D, 0($a0)
addiu $a0, 8 addiu $a0, 8
bltu $a0, $a1, 1b bltu $a0, $a1, 1b

3
sw/bootloader/src/vr4300.h
View File

@ -3,8 +3,11 @@
#define HIT_INVALIDATE_I ((4 << 2) | 0) #define HIT_INVALIDATE_I ((4 << 2) | 0)
#define HIT_WRITE_BACK_INVALIDATE_D ((5 << 2) | 1)
#define HIT_WRITE_BACK_D ((6 << 2) | 1) #define HIT_WRITE_BACK_D ((6 << 2) | 1)
#define CACHE_LINE_SIZE_I (32)
#define CACHE_LINE_SIZE_D (16)
#define C0_BADVADDR $8 #define C0_BADVADDR $8
#define C0_COUNT $9 #define C0_COUNT $9