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[SC64][SW][SB][SL] Added additional CICs, code formatting

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This commit is contained in:
Polprzewodnikowy 2020-10-08 21:50:46 +02:00
parent 527160731f
commit 7025f39fcc
4 changed files with 99 additions and 75 deletions
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22
sw/SummerBanger64/SummerBanger64.py
View File

@ -323,16 +323,18 @@ class SummerBanger64:
def set_cic_type(self, cic_type=0):
cic_lut = {
6101: 0x11,
6102: 0x12,
6103: 0x13,
6105: 0x14,
6106: 0x15,
7101: 0x02,
7102: 0x01,
7103: 0x03,
7105: 0x04,
7106: 0x05,
5101: 0x11,
6101: 0x12,
6102: 0x13,
6103: 0x14,
6105: 0x15,
6106: 0x16,
7101: 0x03,
7102: 0x02,
7103: 0x04,
7105: 0x05,
7106: 0x06,
8303: 0x07,
}
self.__write_word(self.__CIC_TYPE_ADDRESS, int(cic_lut.get(cic_type) or 0))

46
sw/SummerLoader64/src/boot.c
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@ -4,7 +4,7 @@
#include "crc32.h"
#include "n64_regs.h"
cart_header_t global_cart_header __attribute__((aligned(8)));
static cart_header_t global_cart_header __attribute__((aligned(8)));
cart_header_t *boot_load_cart_header(void) {
cart_header_t *cart_header_pointer = &global_cart_header;
@ -18,17 +18,21 @@ cart_header_t *boot_load_cart_header(void) {
cic_type_t boot_get_cic_type(cart_header_t *cart_header) {
switch (crc32_calculate(cart_header->boot_code, sizeof(cart_header->boot_code))) {
case BOOT_CRC32_5101:
return E_CIC_TYPE_5101;
case BOOT_CRC32_6101:
case BOOT_CRC32_7102:
return E_CIC_TYPE_6101;
return E_CIC_TYPE_X101;
case BOOT_CRC32_X102:
return E_CIC_TYPE_6102;
return E_CIC_TYPE_X102;
case BOOT_CRC32_X103:
return E_CIC_TYPE_6103;
return E_CIC_TYPE_X103;
case BOOT_CRC32_X105:
return E_CIC_TYPE_6105;
return E_CIC_TYPE_X105;
case BOOT_CRC32_X106:
return E_CIC_TYPE_6106;
return E_CIC_TYPE_X106;
case BOOT_CRC32_8303:
return E_CIC_TYPE_8303;
default:
return E_CIC_TYPE_UNKNOWN;
}
@ -67,13 +71,15 @@ void boot(cic_type_t cic_type, tv_type_t tv_type) {
volatile uint64_t gpr_regs[32];
const uint8_t cic_seeds[] = {
const uint32_t cic_seeds[] = {
BOOT_SEED_X102,
BOOT_SEED_5101,
BOOT_SEED_X101,
BOOT_SEED_X102,
BOOT_SEED_X103,
BOOT_SEED_X105,
BOOT_SEED_X106,
BOOT_SEED_8303,
};
while (!(SP->status & SP_STATUS_HALT));
@ -105,15 +111,11 @@ void boot(cic_type_t cic_type, tv_type_t tv_type) {
PI->status = PI_STATUS_CLEAR_INTERRUPT | PI_STATUS_RESET_CONTROLLER;
if (cic_type == E_CIC_TYPE_6105) {
OS_BOOT_CONFIG->mem_size_6105 = OS_BOOT_CONFIG->mem_size;
}
for (size_t i = 0; i < ARRAY_ITEMS(SP_MEM->imem); i++) {
SP_MEM->imem[i] = 0;
}
if (cic_type == E_CIC_TYPE_6105) {
if (cic_type == E_CIC_TYPE_X105) {
SP_MEM->imem[0] = 0x3C0DBFC0;
SP_MEM->imem[1] = os_tv_type == E_TV_TYPE_PAL ? 0xBDA807FC : 0x8DA807FC;
SP_MEM->imem[2] = 0x25AD07C0;
@ -124,18 +126,22 @@ void boot(cic_type_t cic_type, tv_type_t tv_type) {
SP_MEM->imem[7] = 0x3C0BB000;
}
if (cic_type == E_CIC_TYPE_X105) {
OS_BOOT_CONFIG->mem_size_6105 = OS_BOOT_CONFIG->mem_size;
}
for (size_t i = 0; i < ARRAY_ITEMS(gpr_regs); i++) {
gpr_regs[i] = 0;
}
gpr_regs[CPU_REG_T3] = (0xFFFFFFFFLL << 32) | ((uint32_t) &SP_MEM->dmem[16]);
gpr_regs[CPU_REG_T3] = CPU_ADDRESS_IN_REG(SP_MEM->dmem[16]);
gpr_regs[CPU_REG_S3] = OS_BOOT_ROM_TYPE_GAME_PAK;
gpr_regs[CPU_REG_S4] = os_tv_type;
gpr_regs[CPU_REG_S6] = cic_seeds[cic_type];
if (os_tv_type == E_TV_TYPE_PAL) {
gpr_regs[CPU_REG_S7] = 6;
}
gpr_regs[CPU_REG_SP] = (0xFFFFFFFFLL << 32) | ((uint32_t) &SP_MEM->imem[ARRAY_ITEMS(SP_MEM->imem) - 4]);
gpr_regs[CPU_REG_RA] = (0xFFFFFFFFLL << 32) | ((uint32_t) &SP_MEM->imem[(os_tv_type == E_TV_TYPE_PAL) ? 341 : 340]);
gpr_regs[CPU_REG_S5] = OS_BOOT_CONFIG->reset_type;
gpr_regs[CPU_REG_S6] = BOOT_SEED_IPL3(cic_seeds[cic_type]);
gpr_regs[CPU_REG_S7] = (os_tv_type == E_TV_TYPE_PAL) ? OS_BOOT_VERSION_PAL : OS_BOOT_VERSION_NTSC;
gpr_regs[CPU_REG_SP] = CPU_ADDRESS_IN_REG(SP_MEM->imem[ARRAY_ITEMS(SP_MEM->imem) - 4]);
gpr_regs[CPU_REG_RA] = CPU_ADDRESS_IN_REG(SP_MEM->imem[(os_tv_type == E_TV_TYPE_PAL) ? 341 : 340]);
__asm__ (
".set noat \n\t"
@ -203,7 +209,7 @@ void boot(cic_type_t cic_type, tv_type_t tv_type) {
"nop"
:
: [gpr_regs] "r" (gpr_regs)
: "t0"
: "t0", "ra"
);
while (1);

38
sw/SummerLoader64/src/boot.h
View File

@ -1,26 +1,34 @@
#ifndef BOOT_H__
#define BOOT_H__
#define BOOT_CRC32_5101 (0x587BD543)
#define BOOT_CRC32_6101 (0x6170A4A1)
#define BOOT_CRC32_7102 (0x009E9EA3)
#define BOOT_CRC32_X102 (0x90BB6CB5)
#define BOOT_CRC32_X103 (0x0B050EE0)
#define BOOT_CRC32_X105 (0x98BC2C86)
#define BOOT_CRC32_X106 (0xACC8580A)
#define BOOT_CRC32_8303 (0x0E018159)
#define BOOT_SEED_X101 (0x3F)
#define BOOT_SEED_X102 (0x3F)
#define BOOT_SEED_X103 (0x78)
#define BOOT_SEED_X105 (0x91)
#define BOOT_SEED_X106 (0x85)
#define BOOT_SEED_5101 (0x0000AC00)
#define BOOT_SEED_X101 (0x00043F3F)
#define BOOT_SEED_X102 (0x00003F3F)
#define BOOT_SEED_X103 (0x0000783F)
#define BOOT_SEED_X105 (0x0000913F)
#define BOOT_SEED_X106 (0x0000853F)
#define BOOT_SEED_8303 (0x0000DD00)
#define BOOT_SEED_IPL3(x) (((x) & 0x0000FF00) >> 8)
typedef enum cic_type_e {
E_CIC_TYPE_UNKNOWN,
E_CIC_TYPE_6101,
E_CIC_TYPE_6102,
E_CIC_TYPE_6103,
E_CIC_TYPE_6105,
E_CIC_TYPE_6106,
E_CIC_TYPE_5101,
E_CIC_TYPE_X101,
E_CIC_TYPE_X102,
E_CIC_TYPE_X103,
E_CIC_TYPE_X105,
E_CIC_TYPE_X106,
E_CIC_TYPE_8303,
E_CIC_TYPE_END,
} cic_type_t;
@ -65,8 +73,14 @@ struct os_boot_config_s {
typedef struct os_boot_config_s os_boot_config_t;
#define OS_BOOT_CONFIG_BASE (0xA0000300)
#define OS_BOOT_CONFIG ((os_boot_config_t *) OS_BOOT_CONFIG_BASE)
#define OS_BOOT_CONFIG_BASE (0xA0000300)
#define OS_BOOT_CONFIG ((os_boot_config_t *) OS_BOOT_CONFIG_BASE)
#define OS_BOOT_ROM_TYPE_GAME_PAK (0)
#define OS_BOOT_ROM_TYPE_DD (1)
#define OS_BOOT_VERSION_NTSC (0)
#define OS_BOOT_VERSION_PAL (6)
cart_header_t *boot_load_cart_header(void);
cic_type_t boot_get_cic_type(cart_header_t *cart_header);

68
sw/SummerLoader64/src/n64_regs.h
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@ -3,40 +3,42 @@
#include <inttypes.h>
#define ARRAY_ITEMS(x) (sizeof(x) / sizeof(x[0]))
#define ARRAY_ITEMS(x) (sizeof(x) / sizeof(x[0]))
#define CPU_REG_Z0 (0)
#define CPU_REG_AT (1)
#define CPU_REG_V0 (2)
#define CPU_REG_V1 (3)
#define CPU_REG_A0 (4)
#define CPU_REG_A1 (5)
#define CPU_REG_A2 (6)
#define CPU_REG_A3 (7)
#define CPU_REG_T0 (8)
#define CPU_REG_T1 (9)
#define CPU_REG_T2 (10)
#define CPU_REG_T3 (11)
#define CPU_REG_T4 (12)
#define CPU_REG_T5 (13)
#define CPU_REG_T6 (14)
#define CPU_REG_T7 (15)
#define CPU_REG_S0 (16)
#define CPU_REG_S1 (17)
#define CPU_REG_S2 (18)
#define CPU_REG_S3 (19)
#define CPU_REG_S4 (20)
#define CPU_REG_S5 (21)
#define CPU_REG_S6 (22)
#define CPU_REG_S7 (23)
#define CPU_REG_T8 (24)
#define CPU_REG_T9 (25)
#define CPU_REG_K0 (26)
#define CPU_REG_K1 (27)
#define CPU_REG_GP (28)
#define CPU_REG_SP (29)
#define CPU_REG_FP (30)
#define CPU_REG_RA (31)
#define CPU_ADDRESS_IN_REG(x) ((0xFFFFFFFFULL << 32) | ((uint32_t) (&(x))))
#define CPU_REG_Z0 (0)
#define CPU_REG_AT (1)
#define CPU_REG_V0 (2)
#define CPU_REG_V1 (3)
#define CPU_REG_A0 (4)
#define CPU_REG_A1 (5)
#define CPU_REG_A2 (6)
#define CPU_REG_A3 (7)
#define CPU_REG_T0 (8)
#define CPU_REG_T1 (9)
#define CPU_REG_T2 (10)
#define CPU_REG_T3 (11)
#define CPU_REG_T4 (12)
#define CPU_REG_T5 (13)
#define CPU_REG_T6 (14)
#define CPU_REG_T7 (15)
#define CPU_REG_S0 (16)
#define CPU_REG_S1 (17)
#define CPU_REG_S2 (18)
#define CPU_REG_S3 (19)
#define CPU_REG_S4 (20)
#define CPU_REG_S5 (21)
#define CPU_REG_S6 (22)
#define CPU_REG_S7 (23)
#define CPU_REG_T8 (24)
#define CPU_REG_T9 (25)
#define CPU_REG_K0 (26)
#define CPU_REG_K1 (27)
#define CPU_REG_GP (28)
#define CPU_REG_SP (29)
#define CPU_REG_FP (30)
#define CPU_REG_RA (31)
typedef struct SP_MEM_s {
volatile uint32_t dmem[1024];