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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-22 05:59:15 +01:00
faster sd menu loading
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parent
da99bc5619
commit
72fe795e56
@ -1,3 +1,4 @@
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#include <string.h>
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#include "ff.h"
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#include "diskio.h"
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#include "../io.h"
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@ -5,7 +6,9 @@
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#include "../error.h"
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#define FROM_BCD(x) ((((x >> 4) & 0x0F) * 10) + (x & 0x0F))
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#define SD_BLOCK_SIZE (512)
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#define BUFFER_BLOCKS_MAX (sizeof(SC64_BUFFERS->BUFFER) / SD_BLOCK_SIZE)
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#define FROM_BCD(x) ((((x >> 4) & 0x0F) * 10) + (x & 0x0F))
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static DSTATUS status = STA_NOINIT;
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@ -34,21 +37,24 @@ DRESULT disk_read (BYTE pdrv, BYTE *buff, LBA_t sector, UINT count) {
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}
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uint32_t *physical_address = (uint32_t *) (PHYSICAL(buff));
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if (physical_address < (uint32_t *) (N64_RAM_SIZE)) {
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uint8_t aligned_buffer[BUFFER_BLOCKS_MAX * SD_BLOCK_SIZE] __attribute__((aligned(8)));
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while (count > 0) {
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uint32_t block = ((count > 16) ? 16 : count);
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if (sc64_sd_read_sectors((uint32_t *) (SC64_BUFFERS->BUFFER), sector, block)) {
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uint32_t blocks = ((count > BUFFER_BLOCKS_MAX) ? BUFFER_BLOCKS_MAX : count);
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size_t length = (blocks * SD_BLOCK_SIZE);
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if (sc64_sd_read_sectors((uint32_t *) (SC64_BUFFERS->BUFFER), sector, blocks)) {
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return RES_ERROR;
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}
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for (uint32_t i = 0; i < (block * 512); i += 4) {
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// TODO: use dma
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uint32_t data = pi_io_read((uint32_t *) (&SC64_BUFFERS->BUFFER[i]));
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uint8_t *ptr = (uint8_t *) (&data);
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for (int j = 0; j < 4; j++) {
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*buff++ = *ptr++;
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}
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if (((uint32_t) (buff) % 8) == 0) {
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pi_dma_read((io32_t *) (SC64_BUFFERS->BUFFER), buff, length);
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cache_data_hit_invalidate(buff, length);
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} else {
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pi_dma_read((io32_t *) (SC64_BUFFERS->BUFFER), aligned_buffer, length);
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cache_data_hit_invalidate(aligned_buffer, length);
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memcpy(buff, aligned_buffer, length);
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}
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count -= block;
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sector += block;
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buff += length;
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sector += blocks;
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count -= blocks;
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}
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} else {
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if (sc64_sd_read_sectors(physical_address, sector, count)) {
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@ -25,6 +25,20 @@ void pi_io_write (io32_t *address, uint32_t value) {
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while (pi_busy());
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}
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void pi_dma_read (io32_t *address, void *buffer, size_t length) {
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io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
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io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
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io_write(&PI->WDMA, length - 1);
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while (pi_busy());
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}
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void pi_dma_write (io32_t *address, void *buffer, size_t length) {
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io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
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io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
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io_write(&PI->RDMA, length - 1);
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while (pi_busy());
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}
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uint32_t si_busy (void) {
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return (io_read(&SI->SR) & (SI_SR_IO_BUSY | SI_SR_DMA_BUSY));
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}
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@ -37,3 +51,23 @@ void si_io_write (io32_t *address, uint32_t value) {
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io_write(address, value);
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while (si_busy());
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}
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static void cache_operation (uint8_t operation, uint8_t line_size, void *address, size_t length) {
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uint32_t cache_address = (((uint32_t) (address)) & (~(line_size - 1)));
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while (cache_address < ((uint32_t) (address) + length)) {
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asm volatile (
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"cache %[operation], (%[cache_address]) \n" ::
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[operation] "i" (operation),
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[cache_address] "r" (cache_address)
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);
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cache_address += line_size;
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}
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}
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void cache_data_hit_invalidate (void *address, size_t length) {
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cache_operation (0x11, 16, address, length);
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}
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void cache_data_hit_writeback (void *address, size_t length) {
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cache_operation (0x19, 16, address, length);
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}
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@ -281,9 +281,13 @@ void io_write (io32_t *address, uint32_t value);
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uint32_t pi_busy (void);
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uint32_t pi_io_read (io32_t *address);
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void pi_io_write (io32_t *address, uint32_t value);
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void pi_dma_read (io32_t *address, void *buffer, size_t length);
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void pi_dma_write (io32_t *address, void *buffer, size_t length);
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uint32_t si_busy (void);
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uint32_t si_io_read (io32_t *address);
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void si_io_write (io32_t *address, uint32_t value);
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void cache_data_hit_invalidate (void *address, size_t length);
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void cache_data_hit_writeback (void *address, size_t length);
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#endif
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