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more cleanup

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This commit is contained in:
Polprzewodnikowy 2022-01-12 16:14:08 +01:00
parent 1be4836288
commit 733cc17ba7
19 changed files with 254 additions and 179 deletions
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11
docker_build.sh
View File

@ -1,14 +1,15 @@
#!/bin/bash
GIT_SHA=$(git rev-parse --short HEAD)
GIT_BRANCH=$(git rev-parse --abbrev-ref HEAD)
GIT_SHA=$(git rev-parse HEAD)
GIT_TAG=$(git describe --tags --exact-match 2> /dev/null)
if [ ! -z $GIT_TAG ]; then
__SC64_VERSION=$(printf "%.7q\ %.7q" $GIT_SHA $GIT_TAG)
else
__SC64_VERSION=$(printf "%.7q\ develop" $GIT_SHA)
if [ -z $GIT_TAG ]; then
GIT_TAG="develop"
fi
__SC64_VERSION=$(printf "[ %q | %q | %q ]" $GIT_BRANCH $GIT_TAG $GIT_SHA)
docker run \
--rm \
--user $(id -u):$(id -g) \

3
sw/n64/Makefile
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@ -15,6 +15,7 @@ BUILD_DIR = build
SRC_FILES = \
startup.S \
ipl2.S \
exception.S \
boot.c \
crc32.c \
@ -23,10 +24,10 @@ SRC_FILES = \
font.c \
init.c \
interrupt.c \
io.c \
main.c \
sc64.c \
storage.c \
sys.c \
syscalls.c \
fatfs/diskio.c \
fatfs/ff.c \

7
sw/n64/src/boot.c
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@ -1,6 +1,7 @@
#include "boot.h"
#include "crc32.h"
#include "sys.h"
#include "init.h"
#include "io.h"
extern uint32_t ipl2 __attribute__((section(".data")));
@ -131,6 +132,8 @@ void boot (boot_info_t *info) {
io_write(&ipl3_dst[i], pi_io_read(&ipl3_src[i]));
}
deinit();
register void (*entry_point)(void) asm ("t3");
register uint32_t boot_device asm ("s3");
register uint32_t tv_type asm ("s4");
@ -148,10 +151,8 @@ void boot (boot_info_t *info) {
stack_pointer = (void *) UNCACHED(&SP_MEM->IMEM[1020]);
asm volatile (
"mtc0 %[status], $12 \n"
"move $sp, %[stack_pointer] \n"
"jr %[entry_point] \n" ::
[status] "r" (C0_SR_CU1 | C0_SR_CU0 | C0_SR_FR),
[entry_point] "r" (entry_point),
[boot_device] "r" (boot_device),
[tv_type] "r" (tv_type),

1
sw/n64/src/error.c
View File

@ -1,4 +1,3 @@
#include "error.h"
#include "exception.h"

160
sw/n64/src/exception.S
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@ -1,62 +1,47 @@
#define VECTOR_LOCATION (0xA0000000UL)
#define VECTOR_SIZE (0x80)
#define VECTOR_NUM (4)
#include "regs.h"
#define HIT_INVALIDATE_I ((4 << 2) | 0)
#define TICKS_PER_SECOND (93750000UL / 2)
#define WATCHDOG_TIMEOUT (10)
#define WATCHDOG_TIMEOUT (10 * (93750000UL / 2))
#define C0_COUNT $9
#define C0_COMPARE $11
#define C0_STATUS $12
#define C0_CAUSE $13
#define C0_EPC $14
#define VECTOR_LOCATION (0xA0000000UL)
#define VECTOR_SIZE (0x80)
#define VECTOR_NUM (4)
#define INTERRUPT_ENABLE (1 << 0)
#define INTERRUPT_MASK_TIMER (1 << 15)
#define EXCEPTION_CODE_MASK (0x007C)
#define EXCEPTION_CODE_BIT (2)
#define INTERRUPT_PENDING_MASK (0xFF00)
#define INTERRUPT_PENDING_BIT (8)
#define INTERRUPT_PENDING_TIMER (1 << 7)
#define AT_OFFSET (8)
#define V0_OFFSET (16)
#define V1_OFFSET (24)
#define A0_OFFSET (32)
#define A1_OFFSET (40)
#define A2_OFFSET (48)
#define A3_OFFSET (56)
#define T0_OFFSET (64)
#define T1_OFFSET (72)
#define T2_OFFSET (80)
#define T3_OFFSET (88)
#define T4_OFFSET (96)
#define T5_OFFSET (104)
#define T6_OFFSET (112)
#define T7_OFFSET (120)
#define S0_OFFSET (128)
#define S1_OFFSET (136)
#define S2_OFFSET (144)
#define S3_OFFSET (152)
#define S4_OFFSET (160)
#define S5_OFFSET (168)
#define S6_OFFSET (176)
#define S7_OFFSET (184)
#define T8_OFFSET (192)
#define T9_OFFSET (200)
#define K0_OFFSET (208)
#define K1_OFFSET (216)
#define GP_OFFSET (224)
#define SP_OFFSET (232)
#define FP_OFFSET (240)
#define RA_OFFSET (248)
#define C0_STATUS_OFFSET (256)
#define C0_CAUSE_OFFSET (260)
#define C0_EPC_OFFSET (264)
#define SAVE_REGISTERS_SIZE (272)
#define AT_OFFSET (8)
#define V0_OFFSET (16)
#define V1_OFFSET (24)
#define A0_OFFSET (32)
#define A1_OFFSET (40)
#define A2_OFFSET (48)
#define A3_OFFSET (56)
#define T0_OFFSET (64)
#define T1_OFFSET (72)
#define T2_OFFSET (80)
#define T3_OFFSET (88)
#define T4_OFFSET (96)
#define T5_OFFSET (104)
#define T6_OFFSET (112)
#define T7_OFFSET (120)
#define S0_OFFSET (128)
#define S1_OFFSET (136)
#define S2_OFFSET (144)
#define S3_OFFSET (152)
#define S4_OFFSET (160)
#define S5_OFFSET (168)
#define S6_OFFSET (176)
#define S7_OFFSET (184)
#define T8_OFFSET (192)
#define T9_OFFSET (200)
#define K0_OFFSET (208)
#define K1_OFFSET (216)
#define GP_OFFSET (224)
#define SP_OFFSET (232)
#define FP_OFFSET (240)
#define RA_OFFSET (248)
#define C0_STATUS_OFFSET (256)
#define C0_CAUSE_OFFSET (260)
#define C0_EPC_OFFSET (264)
#define SAVE_REGISTERS_SIZE (272)
.section .text.exception_handler
@ -96,17 +81,17 @@ exception_handler:
move $sp, $k0
exception_is_fatal:
exception_check_type:
mfc0 $a0, C0_CAUSE
sw $a0, C0_CAUSE_OFFSET($k0)
move $a1, $a0
andi $a0, EXCEPTION_CODE_MASK
srl $a0, $a0, EXCEPTION_CODE_BIT
andi $a1, INTERRUPT_PENDING_MASK
srl $a1, $a1, INTERRUPT_PENDING_BIT
move $t0, $a1
andi $t0, INTERRUPT_PENDING_TIMER
bne $t0, $zero, exception_fatal
move $t0, $a0
andi $t0, C0_CR_IP7
andi $a0, C0_CR_EC_MASK
srl $a0, $a0, C0_CR_EC_BIT
andi $a1, C0_CR_IP_MASK
srl $a1, $a1, C0_CR_IP_BIT
# bne $t0, $zero, exception_fatal
beq $a0, $zero, exception_interrupt
exception_fatal:
@ -194,10 +179,47 @@ exception_install:
bne $t4, $t5, 2b
addiu $t1, VECTOR_SIZE
bne $t1, $t2, 1b
mtc0 $zero, C0_COUNT
li $t7, (WATCHDOG_TIMEOUT * TICKS_PER_SECOND)
mtc0 $t7, C0_COMPARE
mfc0 $t7, C0_STATUS
ori $t7, (INTERRUPT_MASK_TIMER | INTERRUPT_ENABLE)
mtc0 $t7, C0_STATUS
jr $ra
.section .text.exception_disable_interrupts
exception_disable_interrupts:
.global exception_disable_interrupts
mfc0 $t0, C0_STATUS
li $t1, ~(C0_SR_IE)
and $t0, $t0, $t1
mtc0 $t0, C0_STATUS
jr $ra
.section .text.exception_enable_interrupts
exception_enable_interrupts:
.global exception_enable_interrupts
mfc0 $t0, C0_STATUS
li $t1, C0_SR_IE
or $t0, $t0, $t1
mtc0 $t0, C0_STATUS
jr $ra
.section .text.exception_enable_watchdog
exception_enable_watchdog:
.global exception_enable_watchdog
mtc0 $zero, C0_COUNT
li $t1, WATCHDOG_TIMEOUT
mtc0 $t1, C0_COMPARE
mfc0 $t0, C0_STATUS
li $t1, C0_SR_IM7
or $t0, $t0, $t1
mtc0 $t0, C0_STATUS
jr $ra
.section .text.exception_disable_watchdog
exception_disable_watchdog:
.global exception_disable_watchdog
mfc0 $t0, C0_STATUS
li $t1, ~(C0_SR_IM7)
and $t0, $t0, $t1
mtc0 $t0, C0_STATUS
jr $ra

11
sw/n64/src/exception.c
View File

@ -2,7 +2,12 @@
#include <stdio.h>
#include "exception.h"
#include "font.h"
#include "sys.h"
#include "io.h"
#include "regs.h"
#define STR(x) #x
#define XSTR(s) STR(s)
typedef union {
@ -217,8 +222,8 @@ void exception_fatal_handler (uint32_t exception_code, uint32_t interrupt_mask,
exception_print(&x, &y, "s4: 0x%08lX, s5: 0x%08lX, s6: 0x%08lX, s7: 0x%08lX", e->s4.u32, e->s5.u32, e->s6.u32, e->s7.u32);
exception_print(&x, &y, "t8: 0x%08lX, t9: 0x%08lX, k0: 0x%08lX, k1: 0x%08lX", e->t8.u32, e->t9.u32, e->k0.u32, e->k1.u32);
exception_print(&x, &y, "gp: 0x%08lX, sp: 0x%08lX, fp: 0x%08lX, ra: 0x%08lX\n", e->gp.u32, e->sp.u32, e->fp.u32, e->ra.u32);
exception_print(&x, &y, "0x%08lX: 0x%08lX = [%4s]\n", (uint32_t) (&SC64->VERSION), sc64_version, (char *) (&sc64_version));
exception_print(&x, &y, "------------------------------------------------------------------------\n");
exception_print(&x, &y, "0x%08lX: 0x%08lX = [%4s]", (uint32_t) (&SC64->VERSION), sc64_version, (char *) (&sc64_version));
exception_print(&x, &y, "%s\n", XSTR(__SC64_VERSION));
if (exception_code == EXCEPTION_INTERRUPT) {
if (interrupt_mask & INTERRUPT_MASK_TIMER) {

13
sw/n64/src/exception.h
View File

@ -2,10 +2,17 @@
#define EXCEPTION_H__
#define EXCEPTION_TRIGGER(code) { asm volatile ("syscall %[c]\n" :: [c] "i" (code)); }
#define TRIGGER_CODE_ERROR (0)
#define TRIGGER_CODE_ASSERT (16)
#define TRIGGER_CODE_ERROR (0)
#define TRIGGER_CODE_ASSERT (16)
#define EXCEPTION_TRIGGER(code) { asm volatile ("syscall %[c]\n" :: [c] "i" (code)); }
void exception_install (void);
void exception_enable_interrupts (void);
void exception_disable_interrupts (void);
void exception_enable_watchdog (void);
void exception_disable_watchdog (void);
#endif

12
sw/n64/src/init.c
View File

@ -1,4 +1,5 @@
#include "sys.h"
#include "exception.h"
#include "io.h"
#include "sc64.h"
@ -6,5 +7,14 @@ void init (void) {
uint32_t pifram = si_io_read((io32_t *) (&PIFRAM[0x3C]));
si_io_write((io32_t *) (&PIFRAM[0x3C]), pifram | 0x08);
exception_install();
exception_enable_watchdog();
exception_enable_interrupts();
sc64_init();
}
void deinit (void) {
exception_disable_interrupts();
exception_disable_watchdog();
}

9
sw/n64/src/init.h Normal file
View File

@ -0,0 +1,9 @@
#ifndef INIT_H__
#define INIT_H__
void init (void);
void deinit (void);
#endif

2
sw/n64/src/interrupt.c
View File

@ -1,4 +1,4 @@
#include "sc64.h"
#include "io.h"
void exception_interrupt_handler (uint32_t exception_code, uint32_t interrupt_mask) {

2
sw/n64/src/sys.c → sw/n64/src/io.c
View File

@ -1,4 +1,4 @@
#include "sys.h"
#include "io.h"
uint32_t io_read (io32_t *address) {

45
sw/n64/src/sys.h → sw/n64/src/io.h
View File

@ -1,5 +1,5 @@
#ifndef SYS_H__
#define SYS_H__
#ifndef IO_H__
#define IO_H__
#include <stddef.h>
@ -15,47 +15,6 @@ typedef volatile uint32_t io32_t;
#define UNCACHED(address) ((typeof(address)) (((io32_t) (address)) | (0xA0000000UL)))
#define C0_SR_IE (1 << 0)
#define C0_SR_EXL (1 << 1)
#define C0_SR_EXR (1 << 2)
#define C0_SR_KSU0 (1 << 3)
#define C0_SR_KSU1 (1 << 4)
#define C0_SR_UX (1 << 5)
#define C0_SR_SX (1 << 6)
#define C0_SR_KX (1 << 7)
#define C0_SR_IM0 (1 << 8)
#define C0_SR_IM1 (1 << 9)
#define C0_SR_IM2 (1 << 10)
#define C0_SR_IM3 (1 << 11)
#define C0_SR_IM4 (1 << 12)
#define C0_SR_IM5 (1 << 13)
#define C0_SR_IM6 (1 << 14)
#define C0_SR_IM7 (1 << 15)
#define C0_SR_DS_DE (1 << 16)
#define C0_SR_DS_CE (1 << 17)
#define C0_SR_DS_CH (1 << 18)
#define C0_SR_DS_SR (1 << 20)
#define C0_SR_DS_TS (1 << 21)
#define C0_SR_DS_BEV (1 << 22)
#define C0_SR_DS_ITS (1 << 24)
#define C0_SR_RE (1 << 25)
#define C0_SR_FR (1 << 26)
#define C0_SR_RP (1 << 27)
#define C0_SR_CU0 (1 << 28)
#define C0_SR_CU1 (1 << 29)
#define C0_SR_CU2 (1 << 30)
#define C0_SR_CU3 (1 << 31)
#define C0_CR_IP0 (1 << 8)
#define C0_CR_IP1 (1 << 9)
#define C0_CR_IP2 (1 << 9)
#define C0_CR_IP3 (1 << 9)
#define C0_CR_IP4 (1 << 9)
#define C0_CR_IP5 (1 << 9)
#define C0_CR_IP6 (1 << 9)
#define C0_CR_IP7 (1 << 9)
#define C0_CR_BD (1 << 31)
typedef struct {
io32_t DMEM[1024];
io32_t IMEM[1024];

15
sw/n64/src/ipl2.S Normal file
View File

@ -0,0 +1,15 @@
.set noat
.set noreorder
.section .text.ipl2
ipl2:
.global ipl2
lui $t5, 0xBFC0
1:
lw $t0, 0x7FC($t5)
addiu $t5, $t5, 0x7C0
andi $t0, $t0, 0x80
bnel $t0, $zero, 1b
lui $t5, 0xBFC0
lw $t0, 0x24($t5)
lui $t3, 0xB000

10
sw/n64/src/main.c
View File

@ -13,10 +13,14 @@ void main (void) {
sc64_get_info(&sc64_info);
switch (sc64_info.boot_mode) {
case BOOT_MODE_MENU:
case BOOT_MODE_MENU_SD:
storage_run_menu(STORAGE_BACKEND_SD, &boot_info, &sc64_info);
break;
case BOOT_MODE_MENU_USB:
storage_run_menu(STORAGE_BACKEND_USB, &boot_info, &sc64_info);
break;
case BOOT_MODE_ROM:
boot_info.device_type = BOOT_DEVICE_TYPE_ROM;
break;
@ -25,10 +29,6 @@ void main (void) {
boot_info.device_type = BOOT_DEVICE_TYPE_DD;
break;
case BOOT_MODE_MENU_USB:
storage_run_menu(STORAGE_BACKEND_USB, &boot_info, &sc64_info);
break;
default:
error_display("Unknown boot mode selected [%d]", sc64_info.boot_mode);
break;

70
sw/n64/src/regs.h Normal file
View File

@ -0,0 +1,70 @@
#ifndef REGS_H__
#define REGS_H__
#define HIT_INVALIDATE_I ((4 << 2) | 0)
#define C0_COUNT $9
#define C0_COMPARE $11
#define C0_STATUS $12
#define C0_CAUSE $13
#define C0_EPC $14
#define C0_SR_IE (1 << 0)
#define C0_SR_EXL (1 << 1)
#define C0_SR_EXR (1 << 2)
#define C0_SR_KSU0 (1 << 3)
#define C0_SR_KSU1 (1 << 4)
#define C0_SR_UX (1 << 5)
#define C0_SR_SX (1 << 6)
#define C0_SR_KX (1 << 7)
#define C0_SR_IM0 (1 << 8)
#define C0_SR_IM1 (1 << 9)
#define C0_SR_IM2 (1 << 10)
#define C0_SR_IM3 (1 << 11)
#define C0_SR_IM4 (1 << 12)
#define C0_SR_IM5 (1 << 13)
#define C0_SR_IM6 (1 << 14)
#define C0_SR_IM7 (1 << 15)
#define C0_SR_DS_DE (1 << 16)
#define C0_SR_DS_CE (1 << 17)
#define C0_SR_DS_CH (1 << 18)
#define C0_SR_DS_SR (1 << 20)
#define C0_SR_DS_TS (1 << 21)
#define C0_SR_DS_BEV (1 << 22)
#define C0_SR_DS_ITS (1 << 24)
#define C0_SR_RE (1 << 25)
#define C0_SR_FR (1 << 26)
#define C0_SR_RP (1 << 27)
#define C0_SR_CU0 (1 << 28)
#define C0_SR_CU1 (1 << 29)
#define C0_SR_CU2 (1 << 30)
#define C0_SR_CU3 (1 << 31)
#define C0_CR_EC0 (1 << 2)
#define C0_CR_EC1 (1 << 3)
#define C0_CR_EC2 (1 << 4)
#define C0_CR_EC3 (1 << 5)
#define C0_CR_EC4 (1 << 6)
#define C0_CR_IP0 (1 << 8)
#define C0_CR_IP1 (1 << 9)
#define C0_CR_IP2 (1 << 10)
#define C0_CR_IP3 (1 << 11)
#define C0_CR_IP4 (1 << 12)
#define C0_CR_IP5 (1 << 13)
#define C0_CR_IP6 (1 << 14)
#define C0_CR_IP7 (1 << 15)
#define C0_CR_CE0 (1 << 28)
#define C0_CR_CE1 (1 << 29)
#define C0_CR_BD (1 << 31)
#define C0_CR_EC_MASK (C0_CR_EC4 | C0_CR_EC3 | C0_CR_EC2 | C0_CR_EC1 | C0_CR_EC0)
#define C0_CR_EC_BIT (2)
#define C0_CR_IP_MASK (C0_CR_IP7 | C0_CR_IP6 | C0_CR_IP5 | C0_CR_IP4 | C0_CR_IP3 | C0_CR_IP2 | C0_CR_IP1 | C0_CR_IP0)
#define C0_CR_IP_BIT (8)
#endif

12
sw/n64/src/sc64.h
View File

@ -5,7 +5,7 @@
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include "sys.h"
#include "io.h"
#define SC64_CMD_CONFIG ('C')
@ -67,11 +67,11 @@ typedef enum {
} tv_type_t;
typedef enum {
BOOT_MODE_MENU = 0,
BOOT_MODE_ROM = 1,
BOOT_MODE_DDIPL = 2,
BOOT_MODE_DIRECT = 3,
BOOT_MODE_MENU_USB = 4,
BOOT_MODE_MENU_SD = 0,
BOOT_MODE_MENU_USB = 1,
BOOT_MODE_ROM = 2,
BOOT_MODE_DDIPL = 3,
BOOT_MODE_DIRECT = 4,
} boot_mode_t;
typedef struct {

27
sw/n64/src/startup.S
View File

@ -1,8 +1,3 @@
#define STR(x) #x
#define XSTR(s) STR(s)
#define VERSION XSTR(__SC64_VERSION)
.section .text.rom_header
header_pi_config:
.word 0x80371240
@ -22,8 +17,7 @@ header_crc:
.org 0x20, 0x00
header_text_info:
.global header_text_info
.ascii "SummerLoader64 "
.ascii VERSION
.ascii "n64boot SummerCart64"
.org 0x40, 0x00
@ -39,9 +33,6 @@ entry_handler:
la $gp, _gp
la $sp, _sp
la $t0, exception_install
jalr $t0
la $t0, init
jalr $t0
@ -50,19 +41,3 @@ entry_handler:
loop:
j loop
.section .text.ipl2
ipl2:
.global ipl2
.set noat
.set noreorder
lui $t5, 0xBFC0
1:
lw $t0, 0x7FC($t5)
addiu $t5, $t5, 0x7C0
andi $t0, $t0, 0x80
bnel $t0, $zero, 1b
lui $t5, 0xBFC0
lw $t0, 0x24($t5)
lui $t3, 0xB000

12
sw/pc/sc64.py
View File

@ -275,10 +275,10 @@ class SC64:
return "Unknown"
return {
0: "Load menu from SD card",
1: "Load ROM from SDRAM through bootloader",
2: "Load DDIPL from SDRAM",
3: "Load ROM from SDRAM directly without bootloader",
4: "Load menu from USB",
1: "Load menu from USB",
2: "Load ROM from SDRAM",
3: "Load DDIPL from SDRAM",
4: "Load ROM from SDRAM directly without bootloader",
}[mode]
@ -723,7 +723,7 @@ class SC64ProgressBar:
if __name__ == "__main__":
parser = argparse.ArgumentParser(description="SummerCart64 one stop control center")
parser.add_argument("-b", metavar="boot_mode", default="1", required=False, help="set boot mode (0 - 3)")
parser.add_argument("-b", metavar="boot_mode", default="2", required=False, help="set boot mode (0 - 4)")
parser.add_argument("-t", metavar="tv_type", default="3", required=False, help="set TV type (0 - 2)")
parser.add_argument("-c", metavar="cic_seed", default="0xFFFF", required=False, help="set CIC seed")
parser.add_argument("-s", metavar="save_type", default="0", required=False, help="set save type (0 - 6)")
@ -780,7 +780,7 @@ if __name__ == "__main__":
os.remove(firmware_backup_file)
if (not is_read):
if (boot_mode != 1):
if (boot_mode != 2):
print(f"Setting boot mode to [{sc64.get_boot_mode_label(boot_mode)}]")
sc64.set_boot_mode(boot_mode)

11
sw/riscv/src/cfg.c
View File

@ -52,10 +52,11 @@ enum save_type {
};
enum boot_mode {
BOOT_MODE_MENU = 0,
BOOT_MODE_ROM = 1,
BOOT_MODE_DD = 2,
BOOT_MODE_DIRECT = 3,
BOOT_MODE_MENU_SD = 0,
BOOT_MODE_MENU_USB = 1,
BOOT_MODE_ROM = 2,
BOOT_MODE_DD = 3,
BOOT_MODE_DIRECT = 4,
};
@ -249,7 +250,7 @@ void cfg_init (void) {
p.cic_seed = 0xFFFF;
p.tv_type = 0x03;
p.boot_mode = BOOT_MODE_MENU;
p.boot_mode = BOOT_MODE_MENU_SD;
}