From 76ad09cf4a31fa9bdff101bf895111298348d802 Mon Sep 17 00:00:00 2001 From: Mateusz Faderewski Date: Thu, 24 Nov 2022 22:55:05 +0100 Subject: [PATCH] [SC64][FW] Added save write count register for SD save writeback --- fw/project/lcmxo2/sc64.ldf | 3 +++ fw/rtl/mcu/mcu_top.sv | 5 +++++ fw/rtl/n64/n64_pi.sv | 7 +++++++ fw/rtl/n64/n64_save_counter.sv | 24 ++++++++++++++++++++++++ fw/rtl/n64/n64_scb.sv | 16 ++++++++++++++++ fw/rtl/n64/n64_top.sv | 7 +++++++ sw/controller/src/flashram.c | 4 +++- sw/controller/src/fpga.h | 1 + 8 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 fw/rtl/n64/n64_save_counter.sv diff --git a/fw/project/lcmxo2/sc64.ldf b/fw/project/lcmxo2/sc64.ldf index d9473c2..9b99571 100644 --- a/fw/project/lcmxo2/sc64.ldf +++ b/fw/project/lcmxo2/sc64.ldf @@ -51,6 +51,9 @@ + + + diff --git a/fw/rtl/mcu/mcu_top.sv b/fw/rtl/mcu/mcu_top.sv index 76e9996..ddd1e7a 100644 --- a/fw/rtl/mcu/mcu_top.sv +++ b/fw/rtl/mcu/mcu_top.sv @@ -354,6 +354,7 @@ module mcu_top ( REG_DD_HEAD_TRACK, REG_DD_SECTOR_INFO, REG_DD_DRIVE_ID, + REG_SAVE_COUNT, REG_VENDOR_SCR, REG_VENDOR_DATA, REG_DEBUG_0, @@ -624,6 +625,10 @@ module mcu_top ( }; end + REG_SAVE_COUNT: begin + reg_rdata <= {16'd0, n64_scb.save_count}; + end + REG_VENDOR_SCR: begin reg_rdata <= vendor_scb.control_rdata; end diff --git a/fw/rtl/n64/n64_pi.sv b/fw/rtl/n64/n64_pi.sv index e15da47..5481532 100644 --- a/fw/rtl/n64/n64_pi.sv +++ b/fw/rtl/n64/n64_pi.sv @@ -144,6 +144,7 @@ module n64_pi ( const bit [31:0] BUFFER_OFFSET = 32'h0500_0000; logic [31:0] mem_offset; + logic sram_selected; always_ff @(posedge clk) begin if (reset || !pi_reset || end_op) begin @@ -154,6 +155,7 @@ module n64_pi ( if (reset) begin read_port <= PORT_NONE; write_port <= PORT_NONE; + sram_selected <= 1'b0; reg_bus.dd_select <= 1'b0; reg_bus.flashram_select <= 1'b0; reg_bus.cfg_select <= 1'b0; @@ -161,6 +163,7 @@ module n64_pi ( read_port <= PORT_NONE; write_port <= PORT_NONE; mem_offset <= 32'd0; + sram_selected <= 1'b0; reg_bus.dd_select <= 1'b0; reg_bus.flashram_select <= 1'b0; reg_bus.cfg_select <= 1'b0; @@ -200,6 +203,7 @@ module n64_pi ( read_port <= PORT_MEM; write_port <= PORT_MEM; mem_offset <= (-32'h0800_0000) - {n64_pi_dq_in[3:2], 18'd0} + {n64_pi_dq_in[3:2], 15'd0} + SAVE_OFFSET; + sram_selected <= 1'b1; n64_scb.pi_sdram_active <= 1'b1; end end @@ -208,6 +212,7 @@ module n64_pi ( read_port <= PORT_MEM; write_port <= PORT_MEM; mem_offset <= (-32'h0800_0000) + SAVE_OFFSET; + sram_selected <= 1'b1; n64_scb.pi_sdram_active <= 1'b1; end end @@ -409,6 +414,7 @@ module n64_pi ( always_ff @(posedge clk) begin write_fifo_read <= 1'b0; load_starting_address <= 1'b0; + n64_scb.sram_done <= 1'b0; if (reset || !pi_reset) begin mem_bus.request <= 1'b0; @@ -453,6 +459,7 @@ module n64_pi ( if (end_op) begin read_enabled <= 1'b0; + n64_scb.sram_done <= sram_selected && !first_write_op; end end end diff --git a/fw/rtl/n64/n64_save_counter.sv b/fw/rtl/n64/n64_save_counter.sv new file mode 100644 index 0000000..ee19a4a --- /dev/null +++ b/fw/rtl/n64/n64_save_counter.sv @@ -0,0 +1,24 @@ +module n64_save_counter ( + input clk, + input reset, + + n64_scb.save_counter n64_scb +); + + logic [15:0] counter; + + always_ff @(posedge clk) begin + if (reset) begin + counter <= 16'd0; + end else begin + if (n64_scb.eeprom_write || n64_scb.sram_done || n64_scb.flashram_done) begin + counter <= counter + 1'd1; + end + end + end + + always_ff @(posedge clk) begin + n64_scb.save_count <= counter; + end + +endmodule diff --git a/fw/rtl/n64/n64_scb.sv b/fw/rtl/n64/n64_scb.sv index c61f103..4e3c00d 100644 --- a/fw/rtl/n64/n64_scb.sv +++ b/fw/rtl/n64/n64_scb.sv @@ -30,6 +30,8 @@ interface n64_scb (); logic [5:0] flashram_address; logic [15:0] flashram_wdata; + logic sram_done; + logic eeprom_write; logic [10:0] eeprom_address; logic [7:0] eeprom_rdata; @@ -51,6 +53,8 @@ interface n64_scb (); logic [31:0] cfg_wdata [0:1]; logic [31:0] cfg_version; + logic [15:0] save_count; + logic pi_sdram_active; logic pi_flash_active; logic [35:0] pi_debug; @@ -92,6 +96,8 @@ interface n64_scb (); output cfg_wdata, output cfg_version, + input save_count, + input pi_debug ); @@ -109,6 +115,8 @@ interface n64_scb (); input dd_enabled, input ddipl_enabled, + output sram_done, + input flashram_read_mode, input cfg_unlock, @@ -189,6 +197,14 @@ interface n64_scb (); input cfg_version ); + modport save_counter ( + input eeprom_write, + input sram_done, + input flashram_done, + + output save_count + ); + modport arbiter ( input pi_sdram_active, input pi_flash_active diff --git a/fw/rtl/n64/n64_top.sv b/fw/rtl/n64/n64_top.sv index 0191115..2dbc6af 100644 --- a/fw/rtl/n64/n64_top.sv +++ b/fw/rtl/n64/n64_top.sv @@ -94,4 +94,11 @@ module n64_top ( .n64_si_dq(n64_si_dq) ); + n64_save_counter n64_save_counter_inst ( + .clk(clk), + .reset(reset), + + .n64_scb(n64_scb) + ); + endmodule diff --git a/sw/controller/src/flashram.c b/sw/controller/src/flashram.c index 21ccab4..24f5645 100644 --- a/sw/controller/src/flashram.c +++ b/sw/controller/src/flashram.c @@ -35,7 +35,9 @@ static enum operation flashram_operation_type (uint32_t scr) { void flashram_init (void) { - fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); + if (fpga_reg_get(REG_FLASHRAM_SCR) & FLASHRAM_SCR_PENDING) { + fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); + } } void flashram_process (void) { diff --git a/sw/controller/src/fpga.h b/sw/controller/src/fpga.h index 28a4979..37d22f3 100644 --- a/sw/controller/src/fpga.h +++ b/sw/controller/src/fpga.h @@ -50,6 +50,7 @@ typedef enum { REG_DD_HEAD_TRACK, REG_DD_SECTOR_INFO, REG_DD_DRIVE_ID, + REG_SAVE_COUNT, REG_VENDOR_SCR, REG_VENDOR_DATA, REG_DEBUG_0,