diff --git a/README.md b/README.md
index 0946fa5..2603b3c 100644
--- a/README.md
+++ b/README.md
@@ -55,8 +55,7 @@ Instructions below are mostly written for Windows users and point to Windows spe
 
 There are several issues with the project at the moment in order of importance. Keep in mind that core flashcart functionality is fully working:
 
-- No FlashRAM save emulation implementation.
-- No save write-back to SD card implementation.
+- No save write-back to SD card without console reset implementation.
 - No RTC implementation.
 
 
diff --git a/fw/SummerCart64.qsf b/fw/SummerCart64.qsf
index a8beb51..9229242 100644
--- a/fw/SummerCart64.qsf
+++ b/fw/SummerCart64.qsf
@@ -19,7 +19,7 @@
 #
 # Quartus Prime
 # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 15:52:44  February 27, 2021
+# Date created = 00:41:07  March 01, 2021
 #
 # -------------------------------------------------------------------------- #
 #
diff --git a/fw/rtl/flashram/flashram_controller.v b/fw/rtl/flashram/flashram_controller.v
index 0a199c3..0fa41ec 100644
--- a/fw/rtl/flashram/flashram_controller.v
+++ b/fw/rtl/flashram/flashram_controller.v
@@ -217,16 +217,16 @@ module flashram_controller (
 
     reg [15:0] r_items_left;
 
-    wire w_execute_done = !r_execute_start && (r_items_left == 16'd0) && r_flashram_state[STATE_EXECUTE];
-    wire w_read_phase_done = w_execute_done && !o_mem_write && i_mem_ack;
-    wire w_write_phase_done = w_execute_done && o_mem_write;
+    wire w_in_execution = !r_execute_start && r_flashram_state[STATE_EXECUTE];
+    wire w_read_phase_done =  w_in_execution && (r_write_buffer_address == 5'h1F) && !o_mem_write && i_mem_ack;
+    wire w_write_phase_done = w_in_execution && (r_items_left == 16'd0) && o_mem_write;
 
     wire w_mem_request_successful = o_mem_request && !i_mem_busy;
     wire w_address_reset = r_execute_start || w_read_phase_done;
     wire w_write_buffer_address_increment = o_mem_write ? w_mem_request_successful : i_mem_ack;
 
-    always @(posedge i_clk) begin
-        r_execute_done <= w_write_phase_done;
+    always @(*) begin
+        r_execute_done = w_write_phase_done;
     end
 
     always @(posedge i_clk) begin