From 80861989b1477a57d7feb9ab38f6aed1e03b26f5 Mon Sep 17 00:00:00 2001 From: Polprzewodnikowy Date: Sat, 28 Aug 2021 02:37:02 +0200 Subject: [PATCH] sram 768 working --- fw/cpu/controller/process.c | 86 ++++++++++++++++++------------------- fw/cpu/controller/sys.h | 3 +- fw/rtl/cpu/cpu_cfg.sv | 7 ++- fw/rtl/n64/n64_cfg.sv | 5 +-- fw/rtl/n64/n64_pi.sv | 44 +++++++++++++++---- fw/rtl/system/config.sv | 3 ++ 6 files changed, 91 insertions(+), 57 deletions(-) diff --git a/fw/cpu/controller/process.c b/fw/cpu/controller/process.c index b7623fe..85e02c5 100644 --- a/fw/cpu/controller/process.c +++ b/fw/cpu/controller/process.c @@ -182,49 +182,6 @@ void process_uart (void) { } } -void cfg_set_save_type (uint8_t type) { - CFG->SCR &= ~(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_EN); - - switch (type) { - case 0: { - break; - } - case 1: { - CFG->SAVE_OFFSET = SDRAM_SIZE - 512; - break; - } - case 2: { - CFG->SAVE_OFFSET = SDRAM_SIZE - 2048; - break; - } - case 3: { - CFG->SAVE_OFFSET = SDRAM_SIZE - (32 * 1024); - CFG->SCR |= CFG_SCR_SRAM_EN; - break; - } - case 4: { - CFG->SAVE_OFFSET = SDRAM_SIZE - (256 * 1024); - CFG->SCR |= CFG_SCR_FLASHRAM_EN; - break; - } - case 5: { - CFG->SAVE_OFFSET = SDRAM_SIZE - (3 * 32 * 1024); - CFG->SCR |= CFG_SCR_SRAM_EN; - break; - } - case 6: { - CFG->SAVE_OFFSET = 0x01618000; - CFG->SCR |= CFG_SCR_FLASHRAM_EN; - break; - } - default: { - return; - } - } - - save_type = type; -} - void cfg_update_config (uint32_t *args) { switch (args[0]) { case 0: { @@ -265,3 +222,46 @@ void cfg_update_config (uint32_t *args) { } } } + +void cfg_set_save_type (uint8_t type) { + CFG->SCR &= ~(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN); + + switch (type) { + case 0: { + break; + } + case 1: { + CFG->SAVE_OFFSET = SDRAM_SIZE - 512; + break; + } + case 2: { + CFG->SAVE_OFFSET = SDRAM_SIZE - 2048; + break; + } + case 3: { + CFG->SAVE_OFFSET = SDRAM_SIZE - (32 * 1024); + CFG->SCR |= CFG_SCR_SRAM_EN; + break; + } + case 4: { + CFG->SAVE_OFFSET = SDRAM_SIZE - (256 * 1024); + CFG->SCR |= CFG_SCR_FLASHRAM_EN; + break; + } + case 5: { + CFG->SAVE_OFFSET = SDRAM_SIZE - (3 * 32 * 1024); + CFG->SCR |= CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN; + break; + } + case 6: { + CFG->SAVE_OFFSET = 0x01618000; + CFG->SCR |= CFG_SCR_FLASHRAM_EN; + break; + } + default: { + return; + } + } + + save_type = type; +} diff --git a/fw/cpu/controller/sys.h b/fw/cpu/controller/sys.h index f79f80a..62ace8b 100644 --- a/fw/cpu/controller/sys.h +++ b/fw/cpu/controller/sys.h @@ -104,7 +104,8 @@ typedef volatile struct cfg_regs { #define CFG_SCR_SDRAM_WRITABLE (1 << 1) #define CFG_SCR_DD_EN (1 << 2) #define CFG_SCR_SRAM_EN (1 << 3) -#define CFG_SCR_FLASHRAM_EN (1 << 4) +#define CFG_SCR_SRAM_BANKED (1 << 4) +#define CFG_SCR_FLASHRAM_EN (1 << 5) #define CFG_SCR_CPU_BUSY (1 << 30) #define CFG_SCR_CPU_READY (1 << 31) diff --git a/fw/rtl/cpu/cpu_cfg.sv b/fw/rtl/cpu/cpu_cfg.sv index f5c9633..6668dd0 100644 --- a/fw/rtl/cpu/cpu_cfg.sv +++ b/fw/rtl/cpu/cpu_cfg.sv @@ -27,8 +27,9 @@ module cpu_cfg ( R_SCR: bus.rdata = { cfg.cpu_ready, cfg.cpu_busy, - 25'd0, + 24'd0, cfg.flashram_enabled, + cfg.sram_banked, cfg.sram_enabled, cfg.dd_enabled, cfg.sdram_writable, @@ -61,6 +62,7 @@ module cpu_cfg ( cfg.sdram_writable <= 1'b0; cfg.dd_enabled <= 1'b0; cfg.sram_enabled <= 1'b0; + cfg.sram_banked <= 1'b0; cfg.flashram_enabled <= 1'b0; cfg.dd_offset <= 26'h3BE_0000; cfg.save_offset <= 26'h3FE_0000; @@ -82,11 +84,12 @@ module cpu_cfg ( if (bus.wmask[0]) begin { cfg.flashram_enabled, + cfg.sram_banked, cfg.sram_enabled, cfg.dd_enabled, cfg.sdram_writable, cfg.sdram_switch - } <= bus.wdata[4:0]; + } <= bus.wdata[5:0]; end end diff --git a/fw/rtl/n64/n64_cfg.sv b/fw/rtl/n64/n64_cfg.sv index 3e4a8a3..08bf8be 100644 --- a/fw/rtl/n64/n64_cfg.sv +++ b/fw/rtl/n64/n64_cfg.sv @@ -25,7 +25,7 @@ module n64_cfg ( always_comb begin bus.rdata = 16'd0; if (bus.ack) begin - case (bus.address[4:1]) + case (bus.address[3:1]) R_SR: bus.rdata = {cfg.cpu_ready, cfg.cpu_busy, 14'd0}; R_COMMAND: bus.rdata = {8'd0, cfg.cmd}; R_DATA_0_H: bus.rdata = cfg.data[0][31:16]; @@ -34,7 +34,6 @@ module n64_cfg ( R_DATA_1_L: bus.rdata = cfg.data[1][15:0]; R_VERSION_H: bus.rdata = sc64::SC64_VER[31:16]; R_VERSION_L: bus.rdata = sc64::SC64_VER[15:0]; - default: bus.rdata = 16'd0; endcase end end @@ -55,7 +54,7 @@ module n64_cfg ( state <= S_WAIT; bus.ack <= 1'b1; if (bus.write) begin - case (bus.address[4:1]) + case (bus.address[3:1]) R_COMMAND: begin cfg.cmd <= bus.wdata[7:0]; cfg.cmd_request <= 1'b1; diff --git a/fw/rtl/n64/n64_pi.sv b/fw/rtl/n64/n64_pi.sv index 3f84d50..b5fb99c 100644 --- a/fw/rtl/n64/n64_pi.sv +++ b/fw/rtl/n64/n64_pi.sv @@ -169,7 +169,7 @@ module n64_pi ( if (sys.reset || sys.n64_hard_reset) begin wait_for_read_fifo <= 1'b0; wait_for_write_fifo <= 1'b0; - end else begin + end else if (n64_pi_address_valid) begin if (read_op || wait_for_read_fifo) begin if (read_fifo_empty) begin wait_for_read_fifo <= 1'b1; @@ -196,12 +196,14 @@ module n64_pi ( sc64::e_n64_id next_id; logic [31:0] next_offset; logic sram_selected; + logic cfg_selected; always_ff @(posedge sys.clk) begin if (aleh_op) begin n64_pi_address_valid <= 1'b0; next_offset <= 32'd0; sram_selected <= 1'b0; + cfg_selected <= 1'b0; if (cfg.dd_enabled) begin if (n64_pi_ad_input == 16'h0500) begin n64_pi_address_valid <= 1'b1; @@ -213,19 +215,32 @@ module n64_pi ( next_offset <= cfg.dd_offset + 32'h0A00_0000; end end - if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0802) begin - if (cfg.sram_enabled) begin - n64_pi_address_valid <= 1'b1; - next_id <= sc64::ID_N64_SDRAM; - next_offset <= cfg.save_offset + 32'h0800_0000; - sram_selected <= 1'b1; - end else if (cfg.flashram_enabled) begin + if (cfg.flashram_enabled) begin + if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0802) begin n64_pi_address_valid <= 1'b1; next_id <= sc64::ID_N64_FLASHRAM; if (cfg.flashram_read_mode) begin next_offset <= cfg.save_offset + 32'h0800_0000; end end + end else if (cfg.sram_enabled) begin + if (cfg.sram_banked) begin + if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0810) begin + if (n64_pi_ad_input[3:2] != 2'b11 && n64_pi_ad_input[1:0] == 2'b00) begin + n64_pi_address_valid <= 1'b1; + next_id <= sc64::ID_N64_SDRAM; + next_offset <= cfg.save_offset - {n64_pi_ad_input[3:2], 18'd0} + {n64_pi_ad_input[3:2], 15'd0} + 32'h0800_0000; + sram_selected <= 1'b1; + end + end + end else begin + if (n64_pi_ad_input == 16'h0800) begin + n64_pi_address_valid <= 1'b1; + next_id <= sc64::ID_N64_SDRAM; + next_offset <= cfg.save_offset + 32'h0800_0000; + sram_selected <= 1'b1; + end + end end if (n64_pi_ad_input >= 16'h1000 && n64_pi_ad_input < 16'h1400) begin n64_pi_address_valid <= 1'b1; @@ -234,6 +249,19 @@ module n64_pi ( if (n64_pi_ad_input == 16'h1FFF) begin n64_pi_address_valid <= 1'b1; next_id <= sc64::ID_N64_CFG; + cfg_selected <= 1'b1; + end + end + if (alel_op) begin + if (sram_selected) begin + if (n64_pi_ad_input[15]) begin + n64_pi_address_valid <= 1'b0; + end + end + if (cfg_selected) begin + if (|n64_pi_ad_input[15:4]) begin + n64_pi_address_valid <= 1'b0; + end end end end diff --git a/fw/rtl/system/config.sv b/fw/rtl/system/config.sv index e7fe67c..f89f49c 100644 --- a/fw/rtl/system/config.sv +++ b/fw/rtl/system/config.sv @@ -11,6 +11,7 @@ interface if_config (); logic sdram_writable; logic dd_enabled; logic sram_enabled; + logic sram_banked; logic flashram_enabled; logic flashram_read_mode; logic [25:0] dd_offset; @@ -21,6 +22,7 @@ interface if_config (); input sdram_writable, input dd_enabled, input sram_enabled, + input sram_banked, input flashram_enabled, input flashram_read_mode, input dd_offset, @@ -53,6 +55,7 @@ interface if_config (); output sdram_writable, output dd_enabled, output sram_enabled, + output sram_banked, output flashram_enabled, output dd_offset, output save_offset