[SC64][FW][SW] Updated project for Quartus Lite 21.1, reworked build script, minor fixes in USB and CFG modules (#11)

.github/workflows/main.yml

@@ -22,7 +22,7 @@ jobs:
           submodules: true
 
       - name: Build script
-        run: ./build_in_docker.sh
+        run: ./docker_build.sh release
 
       - name: Upload artifact
         uses: actions/upload-artifact@v2

.gitmodules

@@ -1,5 +1,5 @@
 [submodule "fw/cpu/picorv32"]
-	path = fw/cpu/picorv32
+	path = fw/picorv32
 	url = https://github.com/cliffordwolf/picorv32.git
 	ignore = dirty
 [submodule "sw/cic"]

build.sh

@@ -1,49 +1,159 @@
 #!/bin/bash
 
+set -e
 
 PACKAGE_FILE_NAME="SummerCart64"
+
 FILES=(
+    "./fw/output_files/SC64_firmware.pof"
     "./fw/output_files/SC64_update.bin"
-    "./fw/output_files/SC64_update.pof"
     "./hw/ftdi-template.xml"
     "./sw/cic/UltraCIC-III.hex"
     "./LICENSE"
 )
 
+BUILT_CIC=false
+BUILT_N64=false
+BUILT_RISCV=false
+BUILT_FPGA=false
+BUILT_UPDATE=false
+BUILT_RELEASE=false
 
-set -e
+build_cic () {
+    if [ "$BUILT_CIC" = true ]; then return; fi
 
+    pushd sw/cic
+    avra UltraCIC-III.asm -D attiny45
+    popd
 
-pushd sw/cic
+    BUILT_CIC=true
-echo "Building UltraCIC-III software"
+}
-avra UltraCIC-III.asm -D attiny45
-popd
 
+build_n64 () {
+    if [ "$BUILT_N64" = true ]; then return; fi
 
-pushd sw/n64
+    pushd sw/n64
-echo "Building N64 bootloader software"
+    make clean all
-make clean all
+    popd
-popd
 
+    BUILT_N64=true
+}
 
-pushd sw/riscv
+build_riscv () {
-echo "Building RISC-V controller software"
+    if [ "$BUILT_RISCV" = true ]; then return; fi
-make clean all
-popd
 
+    pushd sw/riscv
+    make clean all
+    popd
 
-pushd fw
+    BUILT_RISCV=true
-echo "Building FPGA firmware"
+}
-quartus_sh --flow compile ./SummerCart64.qpf
-quartus_cpf -c ./SummerCart64.cof
-cp output_files/SC64_firmware.pof output_files/SC64_update.pof
-cat output_files/sc64_firmware_ufm_auto.rpd output_files/sc64_firmware_cfm0_auto.rpd > output_files/SC64_update_LE.bin
-riscv32-unknown-elf-objcopy -I binary -O binary --reverse-bytes=4 output_files/SC64_update_LE.bin output_files/SC64_update.bin
-popd
 
+build_fpga () {
+    if [ "$BUILT_FPGA" = true ]; then return; fi
 
-echo "Zipping files"
+    build_n64
-if [[ -e "./${PACKAGE_FILE_NAME}.zip" ]]; then
+    build_riscv
-    rm -f "./${PACKAGE_FILE_NAME}.zip"
+
+    pushd fw
+    quartus_sh --flow compile ./SummerCart64.qpf
+    popd
+
+    BUILT_FPGA=true
+}
+
+build_update () {
+    if [ "$BUILT_UPDATE" = true ]; then return; fi
+
+    build_fpga
+
+    pushd fw/output_files
+    cat sc64_firmware_ufm_auto.rpd sc64_firmware_cfm0_auto.rpd > SC64_update_tmp.bin
+    objcopy -I binary -O binary --reverse-bytes=4 SC64_update_tmp.bin SC64_update.bin
+    rm SC64_update_tmp.bin
+    popd
+
+    BUILT_UPDATE=true
+}
+
+build_release () {
+    if [ "$BUILT_RELEASE" = true ]; then return; fi
+
+    build_cic
+    build_update
+
+    if [[ -e "./${PACKAGE_FILE_NAME}.zip" ]]; then
+        rm -f "./${PACKAGE_FILE_NAME}.zip"
+    fi
+    zip -r "./${PACKAGE_FILE_NAME}.zip" ${FILES[@]}
+
+    BUILT_RELEASE=true
+}
+
+print_usage () {
+    echo "builder script for SummerCart64"
+    echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [--help]"
+    echo "parameters:"
+    echo "  cic - assemble UltraCIC-III software"
+    echo "  n64 - compile N64 bootloader software"
+    echo "  riscv - compile cart governor software"
+    echo "  fpga - compile FPGA design (triggers 'n64' and 'riscv' build)"
+    echo "  update - convert programming .pof file to raw binary for user upgrade (triggers 'fpga' build)"
+    echo "  release - collect and zip files for release (triggers 'cic' and 'update' build)"
+    echo "  --help - print this guide"
+}
+
+if test $# -eq 0; then
+    echo "error: no parameters provided"
+    echo " "
+    print_usage
+    exit 1
 fi
-zip -r "./${PACKAGE_FILE_NAME}.zip" ${FILES[@]}
+
+TRIGGER_CIC=false
+TRIGGER_N64=false
+TRIGGER_RISCV=false
+TRIGGER_FPGA=false
+TRIGGER_UPDATE=false
+TRIGGER_RELEASE=false
+
+while test $# -gt 0; do
+    case "$1" in
+        cic)
+            TRIGGER_CIC=true
+            ;;
+        n64)
+            TRIGGER_N64=true
+            ;;
+        riscv)
+            TRIGGER_RISCV=true
+            ;;
+        fpga)
+            TRIGGER_FPGA=true
+            ;;
+        update)
+            TRIGGER_UPDATE=true
+            ;;
+        release)
+            TRIGGER_RELEASE=true
+            ;;
+        --help)
+            print_usage
+            exit 0
+            ;;
+        *)
+            echo "error: unknown parameter \"$1\""
+            echo " "
+            print_usage
+            exit 1
+            ;;
+    esac
+    shift
+done
+
+if [ "$TRIGGER_CIC" = true ]; then build_cic; fi
+if [ "$TRIGGER_N64" = true ]; then build_n64; fi
+if [ "$TRIGGER_RISCV" = true ]; then build_riscv; fi
+if [ "$TRIGGER_FPGA" = true ]; then build_fpga; fi
+if [ "$TRIGGER_UPDATE" = true ]; then build_update; fi
+if [ "$TRIGGER_RELEASE" = true ]; then build_release; fi

docker_build.sh

@@ -1,6 +1,7 @@
 #!/bin/bash
 
 docker run \
+    --rm \
     --mount type=bind,src="$(pwd)",target="/workdir" \
-    ghcr.io/polprzewodnikowy/sc64env:v1.0 \
+    ghcr.io/polprzewodnikowy/sc64env:v1.2 \
-    /bin/bash -c "./build.sh"
+    ./build.sh $@

fw/.gitignore

@@ -3,10 +3,11 @@
 /incremental_db
 /output_files
 **/.qsys_edit
-*.qws
-*.rpt
-*.txt
-*.sopcinfo
-**/*.elf
 **/*.bin
 **/*.dat
+**/*.elf
+*.qws
+*.rpt
+*.sopcinfo
+*.srf
+*.txt

fw/SummerCart64.qsf

@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Copyright (C) 2021  Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions 
 # and other software and tools, and any partner logic 
 # functions, and any output files from any of the foregoing 
@@ -18,8 +18,8 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 23:38:22  October 28, 2021
+# Date created = 23:52:20  November 09, 2021
 #
 # -------------------------------------------------------------------------- #
 #
@@ -30,7 +30,7 @@
 #    If this file doesn't exist, see file:
 #		assignment_defaults.qdf
 #
-# 2) Altera recommends that you do not modify this file. This
+# 2) Intel recommends that you do not modify this file. This
 #    file is updated automatically by the Quartus Prime software
 #    and any changes you make may be lost or overwritten.
 #
@@ -42,18 +42,16 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:53:32  AUGUST 01, 2021"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
-set_global_assignment -name QSYS_FILE rtl/intel/config/intel_config.qsys
 set_global_assignment -name QSYS_FILE rtl/intel/flash/intel_flash.qsys
-set_global_assignment -name QSYS_FILE rtl/intel/snp/intel_snp.qsys
 set_global_assignment -name QIP_FILE rtl/intel/fifo/intel_fifo_8.qip
 set_global_assignment -name QIP_FILE rtl/intel/gpio/intel_gpio_ddro.qip
 set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
 set_global_assignment -name SDC_FILE SummerCart64.sdc
-set_global_assignment -name SYSTEMVERILOG_FILE cpu/picorv32/picorv32.v
+set_global_assignment -name SYSTEMVERILOG_FILE picorv32/picorv32.v
 set_global_assignment -name SYSTEMVERILOG_FILE ../sw/riscv/build/cpu_bootloader.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_cfg.sv
@@ -85,6 +83,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/config.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
+set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:scripts/post_flow.tcl"
 
 # Pin & Location Assignments
 # ==========================
@@ -95,8 +94,6 @@ set_location_assignment PIN_10 -to io_usb_miosi[0]
 set_location_assignment PIN_11 -to io_usb_miosi[1]
 set_location_assignment PIN_12 -to i_uart_rxd
 set_location_assignment PIN_13 -to o_uart_txd
-set_location_assignment PIN_14 -to i_uart_cts
-set_location_assignment PIN_15 -to o_uart_rts
 set_location_assignment PIN_17 -to o_led
 set_location_assignment PIN_21 -to o_rtc_scl
 set_location_assignment PIN_22 -to io_rtc_sda
@@ -105,8 +102,6 @@ set_location_assignment PIN_25 -to i_n64_nmi
 set_location_assignment PIN_26 -to i_clk
 set_location_assignment PIN_27 -to i_n64_reset
 set_location_assignment PIN_28 -to i_n64_si_clk
-set_location_assignment PIN_29 -to io_n64_cic_clk
-set_location_assignment PIN_30 -to io_n64_cic_dq
 set_location_assignment PIN_32 -to io_n64_pi_ad[7]
 set_location_assignment PIN_33 -to io_n64_pi_ad[8]
 set_location_assignment PIN_38 -to io_n64_pi_ad[6]
@@ -170,13 +165,6 @@ set_location_assignment PIN_118 -to io_sd_cmd
 set_location_assignment PIN_119 -to io_sd_dat[3]
 set_location_assignment PIN_120 -to io_sd_dat[2]
 set_location_assignment PIN_123 -to o_n64_irq
-set_location_assignment PIN_127 -to io_avr_mosi
-set_location_assignment PIN_130 -to io_flash_dq[0]
-set_location_assignment PIN_131 -to o_flash_clk
-set_location_assignment PIN_132 -to io_flash_dq[3]
-set_location_assignment PIN_134 -to o_flash_cs
-set_location_assignment PIN_135 -to io_flash_dq[1]
-set_location_assignment PIN_136 -to io_flash_dq[2]
 set_location_assignment PIN_138 -to i_usb_pwren
 set_location_assignment PIN_140 -to o_usb_cs
 set_location_assignment PIN_141 -to i_usb_miso
@@ -240,7 +228,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 	# ==========================
 	set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[*]
 	set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_uart_rxd
-	set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_uart_cts
 	set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_rtc_sda
 	set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_n64_si_dq
 	set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_nmi
@@ -258,7 +245,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_clk
 	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[*]
 	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_uart_txd
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_uart_rts
 	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_rtc_scl
 	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_rtc_sda
 	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_n64_pi_ad[*]
@@ -278,7 +264,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[*]
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_nmi
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_uart_rxd
-	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_uart_cts
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset
 	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk

fw/SummerCart64.sdc

@@ -10,11 +10,6 @@ create_generated_clock -name sdram_clk -source [get_pins $sdram_pll_clk] [get_po
 # create_generated_clock -name sd_reg_clk -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] -divide_by 2 [get_pins $sd_reg_clk]
 # create_generated_clock -name sd_clk -source [get_pins $sd_reg_clk] [get_ports {o_sd_clk}]
 
-create_generated_clock -name config_clk \
-    -source [get_pins {cpu_soc_inst|cpu_cfg_inst|reconfig_clk|clk}] \
-    -divide_by 2 \
-    [get_pins {cpu_soc_inst|cpu_cfg_inst|reconfig_clk|q}]
-
 create_generated_clock -name flash_se_neg_reg \
     -source [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk}] \
     -divide_by 2 \
@@ -54,7 +49,7 @@ set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks
 # FT1248 timings
 
 set_false_path -to [get_ports {o_usb_clk io_usb_miosi[*] o_usb_cs}]
-set_false_path -from [get_ports {io_usb_miosi[*] i_usb_miso}]
+set_false_path -from [get_ports {io_usb_miosi[*] i_usb_miso i_usb_pwren}]
 
 
 # N64, PI and SI timings
@@ -76,17 +71,11 @@ set_false_path -to [get_ports {o_led}]
 
 # UART timings
 
-set_false_path -to [get_ports {o_uart_txd o_uart_rts}]
+set_false_path -to [get_ports {o_uart_txd}]
-set_false_path -from [get_ports {i_uart_rxd i_uart_cts}]
+set_false_path -from [get_ports {i_uart_rxd}]
 
 
 # I2C timings
 
 set_false_path -to [get_ports {o_rtc_scl io_rtc_sda}]
 set_false_path -from [get_ports {io_rtc_sda}]
-
-
-# JTAG timings
-
-# set_false_path -to [get_ports {altera_reserved_tdo}]
-# set_false_path -from [get_ports {altera_reserved_tdi altera_reserved_tms}]

fw/build.sh

@@ -1,13 +0,0 @@
-#!/bin/bash
-
-docker run \
-    --mount type=bind,src="$(pwd)/..",target="/workdir" \
-    ghcr.io/polprzewodnikowy/sc64env:v1.0 \
-    /bin/bash -c " \
-        cd fw && \
-        quartus_sh --flow compile ./SummerCart64.qpf && \
-        quartus_cpf -c ./SummerCart64.cof && \
-        cp output_files/SC64_firmware.pof output_files/SC64_update.pof && \
-        cat output_files/sc64_firmware_ufm_auto.rpd output_files/sc64_firmware_cfm0_auto.rpd > output_files/SC64_update_LE.bin && \
-        riscv32-unknown-elf-objcopy -I binary -O binary --reverse-bytes=4 output_files/SC64_update_LE.bin output_files/SC64_update.bin
-    "

fw/rtl/SummerCart64.sv

@@ -34,8 +34,6 @@ module SummerCart64 (
 
     input i_uart_rxd,
     output o_uart_txd,
-    input i_uart_cts,
-    output o_uart_rts,
 
     output o_sd_clk,
     inout io_sd_cmd,
@@ -127,8 +125,6 @@ module SummerCart64 (
 
         .uart_rxd(i_uart_rxd),
         .uart_txd(o_uart_txd),
-        .uart_cts(i_uart_cts),
-        .uart_rts(o_uart_rts),
 
         .sd_clk(o_sd_clk),
         .sd_cmd(io_sd_cmd),
@@ -141,7 +137,7 @@ module SummerCart64 (
     end
 
     always_ff @(posedge sys.clk) begin
-        gpio_i <= {4'b0000, i_n64_nmi, i_n64_reset, o_n64_irq, o_led};
+        gpio_i <= {4'b0000, i_n64_nmi, i_n64_reset, gpio_o[1:0]};
     end
 
 endmodule

fw/rtl/cpu/cpu_cfg.sv

@@ -51,7 +51,7 @@ module cpu_cfg (
                 R_DATA_0: bus.rdata = cfg.data[0];
                 R_DATA_1: bus.rdata = cfg.data[1];
                 R_VERSION: bus.rdata = sc64::SC64_VER;
-                R_RECONFIGURE: bus.rdata = {31'd0, trigger_reconfiguration};
+                R_RECONFIGURE: bus.rdata = RECONFIGURE_MAGIC;
                 default: bus.rdata = 32'd0;
             endcase
         end
@@ -134,40 +134,31 @@ module cpu_cfg (
         end
     end
 
-    logic reconfig_clk;
+    logic [1:0] ru_clk;
-    logic reconfig_write;
+    logic ru_rconfig;
-    logic [31:0] reconfig_rdata;
+    logic ru_regout;
-    logic reconfig_write_done;
-
-    const logic [31:0] TRIGGER_RECONFIGURATION = 32'h00000001;
 
     always_ff @(posedge sys.clk) begin
         if (sys.reset) begin
-            reconfig_clk <= 1'b0;
+            ru_clk <= 2'd0;
-            reconfig_write <= 1'b0;
+            ru_rconfig <= 1'b0;
-            reconfig_write_done <= 1'b0;
         end else begin
-            reconfig_clk <= ~reconfig_clk;
+            ru_clk <= ru_clk + 1'd1;
 
-            if (!reconfig_clk) begin
+            if (ru_clk == 2'd1) begin
-                reconfig_write <= 1'b0;
+                ru_rconfig <= trigger_reconfiguration;
-
-                if (trigger_reconfiguration && !reconfig_write_done) begin
-                    reconfig_write <= 1'b1;
-                    reconfig_write_done <= 1'b1;
-                end
             end
         end
     end
 
-    intel_config intel_config_inst (
+    fiftyfivenm_rublock fiftyfivenm_rublock_inst (
-        .clk(reconfig_clk),
+        .clk(ru_clk[1]),
-        .nreset(~sys.reset),
+        .shiftnld(1'b0),
-        .avmm_rcv_address(3'd0),
+        .captnupdt(1'b0),
-        .avmm_rcv_read(1'b0),
+        .regin(1'b0),
-        .avmm_rcv_writedata(TRIGGER_RECONFIGURATION),
+        .rsttimer(1'b0),
-        .avmm_rcv_write(reconfig_write),
+        .rconfig(ru_rconfig),
-        .avmm_rcv_readdata(reconfig_rdata)
+        .regout(ru_regout)
     );
 
 endmodule

fw/rtl/cpu/cpu_soc.sv

@@ -22,8 +22,6 @@ module cpu_soc (
 
     input uart_rxd,
     output uart_txd,
-    input uart_cts,
-    output uart_rts,
 
     output sd_clk,
     inout sd_cmd,
@@ -77,9 +75,7 @@ module cpu_soc (
         .sys(sys),
         .bus(bus.at[sc64::ID_CPU_UART].device),
         .uart_rxd(uart_rxd),
-        .uart_txd(uart_txd),
+        .uart_txd(uart_txd)
-        .uart_cts(uart_cts),
-        .uart_rts(uart_rts)
     );
 
     cpu_dma cpu_dma_inst (
@@ -118,4 +114,8 @@ module cpu_soc (
         .flash(flash)
     );
 
+    assign sd_clk = 1'bZ;
+    assign sd_cmd = 1'bZ;
+    assign sd_dat = 4'bZZZZ;
+
 endmodule

fw/rtl/cpu/cpu_uart.sv

@@ -3,9 +3,7 @@ module cpu_uart (
     if_cpu_bus bus,
 
     input uart_rxd,
-    output uart_txd,
+    output uart_txd
-    input uart_cts,
-    output uart_rts
 );
 
     localparam BAUD_GEN_VALUE = int'(sc64::CLOCK_FREQUENCY / sc64::UART_BAUD_RATE) - 1'd1;

fw/rtl/cpu/cpu_usb.sv

@@ -23,6 +23,8 @@ module cpu_usb (
     logic cpu_rx_read;
     logic cpu_tx_write;
 
+    logic usb_enabled;
+
     always_comb begin
         dma.rx_empty = rx_empty;
         rx_read = cpu_rx_read || dma.rx_read;
@@ -44,7 +46,7 @@ module cpu_usb (
         bus.rdata = 32'd0;
         if (bus.ack) begin
             case (bus.address[2:2])
-                0: bus.rdata = {30'd0, ~tx_full, ~rx_empty};
+                0: bus.rdata = {26'd0, usb_pwren, usb_enabled, 2'b00, ~tx_full, ~rx_empty};
                 1: bus.rdata = {24'd0, rx_rdata};
                 default: bus.rdata = 32'd0;
             endcase
@@ -58,33 +60,38 @@ module cpu_usb (
         tx_flush <= 1'b0;
         cpu_tx_write <= 1'b0;
 
-        if (bus.request) begin
+        if (sys.reset) begin
-            case (bus.address[2:2])
+            usb_enabled <= 1'b0;
-                2'd0: begin
+        end else begin
-                    if (bus.wmask[0]) begin
+            if (bus.request) begin
-                        {tx_flush, rx_flush} <= bus.wdata[3:2];
+                case (bus.address[2:2])
+                    2'd0: begin
+                        if (bus.wmask[0]) begin
+                            {usb_enabled, tx_flush, rx_flush} <= bus.wdata[4:2];
+                        end
                     end
-                end
 
-                2'd1: begin
+                    2'd1: begin
-                    if (bus.wmask[0]) begin
+                        if (bus.wmask[0]) begin
-                        cpu_tx_write <= 1'b1;
+                            cpu_tx_write <= 1'b1;
-                    end else begin
+                        end else begin
-                        cpu_rx_read <= 1'b1;
+                            cpu_rx_read <= 1'b1;
+                        end
                     end
-                end
+                endcase
-            endcase
+            end
         end
     end
 
     usb_ft1248 usb_ft1248_inst (
         .sys(sys),
 
+        .usb_enabled(usb_enabled),
+
         .usb_clk(usb_clk),
         .usb_cs(usb_cs),
         .usb_miso(usb_miso),
         .usb_miosi(usb_miosi),
-        .usb_pwren(usb_pwren),
 
         .rx_flush(rx_flush),
         .rx_empty(rx_empty),

fw/rtl/intel/config/intel_config.qsys

@@ -1,67 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element dual_boot_0
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10M08SCE144C8G" />
- <parameter name="deviceFamily" value="MAX 10" />
- <parameter name="deviceSpeedGrade" value="8" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="avalon" internal="dual_boot_0.avalon" type="avalon" dir="end">
-  <port name="avmm_rcv_address" internal="avmm_rcv_address" />
-  <port name="avmm_rcv_read" internal="avmm_rcv_read" />
-  <port name="avmm_rcv_writedata" internal="avmm_rcv_writedata" />
-  <port name="avmm_rcv_write" internal="avmm_rcv_write" />
-  <port name="avmm_rcv_readdata" internal="avmm_rcv_readdata" />
- </interface>
- <interface name="clk" internal="dual_boot_0.clk" type="clock" dir="end">
-  <port name="clk" internal="clk" />
- </interface>
- <interface name="nreset" internal="dual_boot_0.nreset" type="reset" dir="end">
-  <port name="nreset" internal="nreset" />
- </interface>
- <module
-   name="dual_boot_0"
-   kind="altera_dual_boot"
-   version="20.1"
-   enabled="1"
-   autoexport="1">
-  <parameter name="CLOCK_FREQUENCY" value="50.0" />
-  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
-</system>

fw/rtl/intel/fifo/intel_fifo_8.qip

@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "FIFO"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_fifo_8.v"]

fw/rtl/intel/fifo/intel_fifo_8.v

@@ -9,16 +9,16 @@
 // 			scfifo
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -99,7 +99,7 @@ endmodule
 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
 // Retrieval info: PRIVATE: Clock NUMERIC "0"
 // Retrieval info: PRIVATE: Depth NUMERIC "1024"
 // Retrieval info: PRIVATE: Empty NUMERIC "1"
@@ -160,4 +160,3 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_inst.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf

fw/rtl/intel/flash/intel_flash.qsys

@@ -6,18 +6,18 @@
    version="1.0"
    description=""
    tags="INTERNAL_COMPONENT=true"
-   categories="System" />
+   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
+ <parameter name="bonusData"><![CDATA[bonusData 
-{
+{
-   element onchip_flash_0
+   element onchip_flash_0
-   {
+   {
-      datum _sortIndex
+      datum _sortIndex
-      {
+      {
-         value = "0";
+         value = "0";
-         type = "int";
+         type = "int";
-      }
+      }
-   }
+   }
-}
+}
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
  <parameter name="device" value="10M08SCE144C8G" />
@@ -64,7 +64,7 @@
  <module
    name="onchip_flash_0"
    kind="altera_onchip_flash"
-   version="20.1"
+   version="21.1"
    enabled="1"
    autoexport="1">
   <parameter name="AUTO_CLOCK_RATE" value="0" />

fw/rtl/intel/gpio/intel_gpio_ddro.qip

@@ -1,5 +1,5 @@
 set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_NAME "altera_gpio_lite"
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_VERSION "21.1"
 set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "intel_gpio_ddro" -name MISC_FILE [file join $::quartus(qip_path) "intel_gpio_ddro.cmp"]
 set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -11,14 +11,14 @@ set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name
 set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_VERSION "MjEuMQ=="
 set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_VERSION "MjEuMQ=="
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::b3V0cHV0::RGF0YSBkaXJlY3Rpb24="
@@ -73,5 +73,5 @@ set_global_assignment -library "intel_gpio_ddro" -name VERILOG_FILE [file join $
 set_global_assignment -library "intel_gpio_ddro" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_gpio_ddro/altera_gpio_lite.sv"]
 
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_NAME "altera_gpio_lite"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_VERSION "21.1"
 set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_ENV "mwpim"

fw/rtl/intel/gpio/intel_gpio_ddro.v

@@ -1,8 +1,8 @@
-// megafunction wizard: %GPIO Lite Intel FPGA IP v20.1%
+// megafunction wizard: %GPIO Lite Intel FPGA IP v21.1%
 // GENERATION: XML
 // intel_gpio_ddro.v
 
-// Generated using ACDS version 20.1 720
+// Generated using ACDS version 21.1 842
 
 `timescale 1 ps / 1 ps
 module intel_gpio_ddro (
@@ -89,7 +89,7 @@ endmodule
 //	their respective licensors.  No other licenses, including any licenses
 //	needed under any third party's intellectual property, are provided herein.
 //-->
-// Retrieval info: <instance entity-name="altera_gpio_lite" version="20.1" >
+// Retrieval info: <instance entity-name="altera_gpio_lite" version="21.1" >
 // Retrieval info: 	<generic name="DEVICE_FAMILY" value="MAX 10" />
 // Retrieval info: 	<generic name="PIN_TYPE" value="output" />
 // Retrieval info: 	<generic name="SIZE" value="1" />

fw/rtl/intel/gpio/intel_gpio_ddro/altera_gpio_lite.sv

@@ -1,4 +1,4 @@
-// (C) 2001-2020 Intel Corporation. All rights reserved.
+// (C) 2001-2021 Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions and other 
 // software and tools, and its AMPP partner logic functions, and any output 
 // files from any of the foregoing (including device programming or simulation 

fw/rtl/intel/pll/intel_pll.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_pll.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "intel_pll.ppf"]

fw/rtl/intel/pll/intel_pll.v

@@ -9,16 +9,16 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -337,5 +337,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll_inst.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

fw/rtl/intel/snp/intel_snp.qsys

@@ -1,76 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element in_system_sources_probes_0
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10M08SCE144C8G" />
- <parameter name="deviceFamily" value="MAX 10" />
- <parameter name="deviceSpeedGrade" value="8" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="probes" internal="in_system_sources_probes_0.probes" />
- <interface
-   name="source_clk"
-   internal="in_system_sources_probes_0.source_clk"
-   type="clock"
-   dir="end">
-  <port name="source_clk" internal="source_clk" />
- </interface>
- <interface
-   name="sources"
-   internal="in_system_sources_probes_0.sources"
-   type="conduit"
-   dir="end">
-  <port name="source" internal="source" />
- </interface>
- <module
-   name="in_system_sources_probes_0"
-   kind="altera_in_system_sources_probes"
-   version="20.1"
-   enabled="1"
-   autoexport="1">
-  <parameter name="create_source_clock" value="true" />
-  <parameter name="create_source_clock_enable" value="false" />
-  <parameter name="device_family" value="MAX 10" />
-  <parameter name="gui_use_auto_index" value="true" />
-  <parameter name="instance_id" value="SC64" />
-  <parameter name="probe_width" value="0" />
-  <parameter name="sld_instance_index" value="0" />
-  <parameter name="source_initial_value" value="0" />
-  <parameter name="source_width" value="1" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
-</system>

fw/rtl/system/sc64.sv

@@ -37,6 +37,4 @@ package sc64;
 
     parameter int UART_BAUD_RATE    = 32'd1_000_000;
 
-    parameter bit DEBUG_ENABLED     = 1'b0;
-
 endpackage

fw/rtl/system/system.sv

@@ -38,7 +38,6 @@ endinterface
 module system (if_system.internal sys);
 
     logic locked;
-    logic external_reset;
     logic [1:0] n64_reset_ff;
     logic [1:0] n64_nmi_ff;
 
@@ -49,22 +48,13 @@ module system (if_system.internal sys);
         .locked(locked)
     );
 
-    generate
-        if (sc64::DEBUG_ENABLED) begin
-            intel_snp intel_snp_inst (
-                .source(external_reset),
-                .source_clk(sys.clk)
-            );
-        end
-    endgenerate
-
     always_ff @(posedge sys.clk) begin
         n64_reset_ff <= {n64_reset_ff[0], sys.n64_reset};
         n64_nmi_ff <= {n64_nmi_ff[0], sys.n64_nmi};
     end
 
     always_comb begin
-        sys.reset = ~locked | external_reset;
+        sys.reset = ~locked;
         sys.n64_hard_reset = ~n64_reset_ff[1];
         sys.n64_soft_reset = ~n64_nmi_ff[1];
     end

fw/rtl/usb/usb_ft1248.sv

@@ -1,11 +1,12 @@
 module usb_ft1248 (
     if_system.sys sys,
 
+    input usb_enabled,
+
     output usb_clk,
     output usb_cs,
     input usb_miso,
     inout [3:0] usb_miosi,
-    input usb_pwren,
 
     input rx_flush,
     output rx_empty,
@@ -30,7 +31,7 @@ module usb_ft1248 (
 
     intel_fifo_8 fifo_8_rx_inst (
         .clock(sys.clk),
-        .sclr(rx_flush),
+        .sclr(rx_flush || !usb_enabled),
 
         .empty(rx_empty),
         .rdreq(rx_read),
@@ -43,7 +44,7 @@ module usb_ft1248 (
 
     intel_fifo_8 fifo_8_tx_inst (
         .clock(sys.clk),
-        .sclr(tx_flush),
+        .sclr(tx_flush || !usb_enabled),
 
         .empty(tx_empty),
         .rdreq(tx_read),
@@ -88,7 +89,6 @@ module usb_ft1248 (
     logic usb_miosi_output_enable;
     logic usb_miosi_output_enable_data;
     logic usb_miso_input;
-    logic usb_pwren_input;
 
     logic is_cmd_write;
     logic [1:0] nibble_counter;
@@ -111,7 +111,6 @@ module usb_ft1248 (
         usb_miosi_output_enable <= usb_miosi_output_enable_data;
         
         usb_miso_input <= usb_miso;
-        usb_pwren_input <= usb_pwren;
 
         tx_buffer <= tx_rdata;
     end
@@ -157,7 +156,7 @@ module usb_ft1248 (
             nibble_counter <= nibble_counter + 1'd1;
         end
 
-        if (sys.reset) begin
+        if (sys.reset || !usb_enabled) begin
             state <= S_TRY_RX;
         end else begin
             case (state)

fw/scripts/post_flow.tcl

@@ -0,0 +1,6 @@
+set flow [lindex $quartus(args) 0]
+
+if [string match "compile" $flow] {
+    post_message "Generating final programming file"
+    qexec "quartus_cpf -c SummerCart64.cof"
+}

sw/n64/build.sh

@@ -1,6 +0,0 @@
-#!/bin/bash
-
-docker run \
-    --mount type=bind,src="$(pwd)",target="/workdir" \
-    ghcr.io/polprzewodnikowy/sc64env:v1.0 \
-    /bin/bash -c "make clean all"

sw/pc/.gitignore

@@ -1,10 +1,12 @@
+/backup
+/saves
+*.bak
+*.bin
 *.dat
-*.srm
+*.data
 *.eep
 *.fla
 *.n64
-*.z64
+*.srm
 *.v64
-*.data
+*.z64
-*.bak
-*.bin

sw/pc/update.py

@@ -11,7 +11,7 @@ class SC64:
 
 
     def __init__(self, port):
-        self.__serial = serial.Serial(port)
+        self.__serial = serial.Serial(port, timeout=10.0, write_timeout=10.0)
 
 
     def __query_config(self, query, arg=0):
@@ -35,12 +35,12 @@ class SC64:
     def reconfigure(self):
         magic = self.__query_config(self.__CFG_ID_RECONFIGURE)
         self.__change_config(self.__CFG_ID_RECONFIGURE, magic, ignore_response=True)
-        time.sleep(1)
+        time.sleep(0.2)
 
 
     def read_flash(self, file):
         size = self.__query_config(self.__CFG_ID_FLASH_OPERATION)
-        print('Flash size: {:08X}'.format(size))
+        print(f'Flash size: {(size / 1024.0):1.1f} kB')
         self.__serial.write(b'CMDR')
         self.__serial.write((0).to_bytes(4, byteorder='big'))
         self.__serial.write((size).to_bytes(4, byteorder='big'))

sw/riscv/build.sh

@@ -1,6 +0,0 @@
-#!/bin/bash
-
-docker run \
-    --mount type=bind,src="$(pwd)",target="/workdir" \
-    ghcr.io/polprzewodnikowy/sc64env:v1.0 \
-    /bin/bash -c "USER_FLAGS=\"-DDEBUG\" make clean all"

sw/riscv/src/cfg.c

@@ -139,8 +139,8 @@ void cfg_update (uint32_t *args) {
             flash_program(args[1]);
             break;
         case CFG_ID_RECONFIGURE:
-            if (args[1] == CFG_RECONFIGURE_MAGIC) {
+            if (args[1] == CFG->RECONFIGURE) {
-                CFG->RECONFIGURE = CFG_RECONFIGURE_MAGIC;
+                CFG->RECONFIGURE = args[1];
                 __asm__ volatile (
                     "ebreak \n"
                 );
@@ -185,7 +185,7 @@ void cfg_query (uint32_t *args) {
             args[1] = flash_read(args[1]);
             break;
         case CFG_ID_RECONFIGURE:
-            args[1] = CFG_RECONFIGURE_MAGIC;
+            args[1] = CFG->RECONFIGURE;
             break;
     }
 }

sw/riscv/src/sys.h

@@ -59,6 +59,8 @@ typedef volatile struct usb_regs {
 #define USB_SCR_TXE                 (1 << 1)
 #define USB_SCR_FLUSH_RX            (1 << 2)
 #define USB_SCR_FLUSH_TX            (1 << 3)
+#define USB_SCR_ENABLED             (1 << 4)
+#define USB_SCR_PWREN               (1 << 5)
 
 
 typedef volatile struct uart_regs {
@@ -115,8 +117,6 @@ typedef volatile struct cfg_regs {
 #define CFG_SCR_CPU_BUSY            (1 << 30)
 #define CFG_SCR_CPU_READY           (1 << 31)
 
-#define CFG_RECONFIGURE_MAGIC       (0x52535446)
-
 
 #define SDRAM_BASE                  (0x80000000UL)
 #define SDRAM                       (*((io32_t *) SDRAM_BASE))

sw/riscv/src/usb.c

@@ -181,7 +181,7 @@ static bool rx_cmd (uint32_t *data) {
 
 
 void usb_init (void) {
-    USB->SCR = USB_SCR_FLUSH_TX | USB_SCR_FLUSH_RX;
+    USB->SCR = USB_SCR_ENABLED | USB_SCR_FLUSH_TX | USB_SCR_FLUSH_RX;
 
     p.state = STATE_IDLE;
     p.debug_rx_busy = false;