From 89e84f10fb3cb703ee500ff22ebfcbe651219dc3 Mon Sep 17 00:00:00 2001 From: Polprzewodnikowy Date: Mon, 7 Feb 2022 22:24:37 +0100 Subject: [PATCH] pretend we have 128 MB sdram --- fw/SummerCart64.qsf | 12 +-- fw/rtl/cpu/cpu_cfg.sv | 55 ++---------- fw/rtl/cpu/cpu_ram.sv | 12 +-- fw/rtl/n64/n64_bus.sv | 5 -- fw/rtl/n64/n64_cfg.sv | 83 ++++++------------- fw/rtl/n64/n64_pi.sv | 65 ++++----------- fw/rtl/system/config.sv | 19 +---- fw/rtl/usb/usb_ft1248.sv | 20 ++--- .../intel/generated}/intel_flash.qsys | 0 .../intel/generated}/intel_gpio_ddro.qip | 0 .../intel/generated}/intel_gpio_ddro.v | 0 .../intel_gpio_ddro/altera_gpio_lite.sv | 0 .../intel/generated}/intel_pll.ppf | 0 .../intel/generated}/intel_pll.qip | 0 .../intel/generated}/intel_pll.v | 0 fw/rtl/vendor/{ => intel}/vendor_flash.sv | 0 .../vendor/{ => intel}/vendor_reconfigure.sv | 0 sw/pc/sc64.py | 4 +- sw/riscv/SC64.ld | 2 +- sw/riscv/src/cfg.c | 35 +------- sw/riscv/src/dd.c | 11 +-- sw/riscv/src/dd.h | 1 - sw/riscv/src/flashram.c | 4 +- sw/riscv/src/flashram.h | 3 - sw/riscv/src/isv.c | 43 ++++++---- sw/riscv/src/joybus.c | 3 +- sw/riscv/src/joybus.h | 3 - sw/riscv/src/sys.h | 11 ++- 28 files changed, 122 insertions(+), 269 deletions(-) rename fw/rtl/{intel/flash => vendor/intel/generated}/intel_flash.qsys (100%) rename fw/rtl/{intel/gpio => vendor/intel/generated}/intel_gpio_ddro.qip (100%) rename fw/rtl/{intel/gpio => vendor/intel/generated}/intel_gpio_ddro.v (100%) rename fw/rtl/{intel/gpio => vendor/intel/generated}/intel_gpio_ddro/altera_gpio_lite.sv (100%) rename fw/rtl/{intel/pll => vendor/intel/generated}/intel_pll.ppf (100%) rename fw/rtl/{intel/pll => vendor/intel/generated}/intel_pll.qip (100%) rename fw/rtl/{intel/pll => vendor/intel/generated}/intel_pll.v (100%) rename fw/rtl/vendor/{ => intel}/vendor_flash.sv (100%) rename fw/rtl/vendor/{ => intel}/vendor_reconfigure.sv (100%) diff --git a/fw/SummerCart64.qsf b/fw/SummerCart64.qsf index 0c36a00..d137f48 100644 --- a/fw/SummerCart64.qsf +++ b/fw/SummerCart64.qsf @@ -47,10 +47,10 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/post_module.tcl" -set_global_assignment -name QSYS_FILE rtl/intel/flash/intel_flash.qsys +set_global_assignment -name QSYS_FILE rtl/vendor/intel/generated/intel_flash.qsys set_global_assignment -name QIP_FILE rtl/intel/fifo/intel_fifo_8.qip -set_global_assignment -name QIP_FILE rtl/intel/gpio/intel_gpio_ddro.qip -set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip +set_global_assignment -name QIP_FILE rtl/vendor/intel/generated/intel_gpio_ddro.qip +set_global_assignment -name QIP_FILE rtl/vendor/intel/generated/intel_pll.qip set_global_assignment -name SDC_FILE SummerCart64.sdc set_global_assignment -name SYSTEMVERILOG_FILE picorv32/picorv32.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv @@ -83,8 +83,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/config.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/vendor/vendor_flash.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/vendor/vendor_reconfigure.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/vendor/intel/vendor_flash.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/vendor/intel/vendor_reconfigure.sv # Pin & Location Assignments # ========================== @@ -205,7 +205,7 @@ set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.0-V LVTTL" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" # Assembler Assignments # ===================== diff --git a/fw/rtl/cpu/cpu_cfg.sv b/fw/rtl/cpu/cpu_cfg.sv index 5468996..a587216 100644 --- a/fw/rtl/cpu/cpu_cfg.sv +++ b/fw/rtl/cpu/cpu_cfg.sv @@ -5,21 +5,16 @@ module cpu_cfg ( ); logic skip_bootloader; + logic enable_writes_on_reset; logic trigger_reconfiguration; - logic [15:0] isv_current_rd_ptr; - typedef enum bit [3:0] { + typedef enum bit [2:0] { R_SCR, - R_DDIPL_OFFSET, - R_SAVE_OFFSET, R_COMMAND, R_DATA_0, R_DATA_1, R_VERSION, - R_RECONFIGURE, - R_ISV_OFFSET, - R_ISV_RD_PTR, - R_FLASH + R_RECONFIGURE } e_reg_id; const logic [31:0] RECONFIGURE_MAGIC = 32'h52535446; @@ -34,7 +29,7 @@ module cpu_cfg ( always_comb begin bus.rdata = 32'd0; if (bus.ack) begin - case (bus.address[5:2]) + case (bus.address[4:2]) R_SCR: bus.rdata = { cfg.cpu_ready, cfg.cpu_busy, @@ -44,7 +39,7 @@ module cpu_cfg ( cfg.flash_erase_busy, 1'd0, 16'd0, - cfg.isv_enabled, + enable_writes_on_reset, skip_bootloader, cfg.flashram_enabled, cfg.sram_banked, @@ -53,15 +48,11 @@ module cpu_cfg ( cfg.sdram_writable, cfg.sdram_switch }; - R_DDIPL_OFFSET: bus.rdata = {6'd0, cfg.ddipl_offset}; - R_SAVE_OFFSET: bus.rdata = {6'd0, cfg.save_offset}; R_COMMAND: bus.rdata = {24'd0, cfg.cmd}; R_DATA_0: bus.rdata = cfg.data[0]; R_DATA_1: bus.rdata = cfg.data[1]; R_VERSION: bus.rdata = sc64::SC64_VER; R_RECONFIGURE: bus.rdata = RECONFIGURE_MAGIC; - R_ISV_OFFSET: bus.rdata = {6'd0, cfg.isv_offset}; - R_ISV_RD_PTR: bus.rdata = {isv_current_rd_ptr, cfg.isv_rd_ptr}; default: bus.rdata = 32'd0; endcase end @@ -91,17 +82,13 @@ module cpu_cfg ( cfg.sram_enabled <= 1'b0; cfg.sram_banked <= 1'b0; cfg.flashram_enabled <= 1'b0; - cfg.isv_enabled <= 1'b0; - cfg.ddipl_offset <= 26'h3BE_0000; - cfg.save_offset <= 26'h3FE_0000; - cfg.isv_offset <= 26'h3FF_0000; skip_bootloader <= 1'b0; + enable_writes_on_reset <= 1'b0; trigger_reconfiguration <= 1'b0; end else begin if (sys.n64_soft_reset) begin cfg.sdram_switch <= skip_bootloader; - cfg.sdram_writable <= 1'b0; - isv_current_rd_ptr <= 16'd0; + cfg.sdram_writable <= enable_writes_on_reset; end if (cfg.cmd_request) begin @@ -109,7 +96,7 @@ module cpu_cfg ( end if (bus.request) begin - case (bus.address[5:2]) + case (bus.address[4:2]) R_SCR: begin if (bus.wmask[3]) begin { @@ -123,7 +110,7 @@ module cpu_cfg ( end if (bus.wmask[0]) begin { - cfg.isv_enabled, + enable_writes_on_reset, skip_bootloader, cfg.flashram_enabled, cfg.sram_banked, @@ -135,35 +122,11 @@ module cpu_cfg ( end end - R_DDIPL_OFFSET: begin - if (&bus.wmask) begin - cfg.ddipl_offset <= bus.wdata[25:0]; - end - end - - R_SAVE_OFFSET: begin - if (&bus.wmask) begin - cfg.save_offset <= bus.wdata[25:0]; - end - end - R_RECONFIGURE: begin if (&bus.wmask && bus.wdata == RECONFIGURE_MAGIC) begin trigger_reconfiguration <= 1'b1; end end - - R_ISV_OFFSET: begin - if (&bus.wmask) begin - cfg.isv_offset <= bus.wdata[25:0]; - end - end - - R_ISV_RD_PTR: begin - if (&bus.wmask[3:2]) begin - isv_current_rd_ptr <= bus.wdata[31:16]; - end - end endcase end end diff --git a/fw/rtl/cpu/cpu_ram.sv b/fw/rtl/cpu/cpu_ram.sv index 3e8cb90..30dff79 100644 --- a/fw/rtl/cpu/cpu_ram.sv +++ b/fw/rtl/cpu/cpu_ram.sv @@ -3,7 +3,7 @@ module cpu_ram ( if_cpu_bus bus ); - logic [3:0][7:0] ram [0:8191]; + logic [3:0][7:0] ram [0:4095]; logic [31:0] q; always_ff @(posedge sys.clk) begin @@ -21,12 +21,12 @@ module cpu_ram ( end always_ff @(posedge sys.clk) begin - q <= ram[bus.address[14:2]]; + q <= ram[bus.address[13:2]]; if (bus.request) begin - if (bus.wmask[0]) ram[bus.address[14:2]][0] <= bus.wdata[7:0]; - if (bus.wmask[1]) ram[bus.address[14:2]][1] <= bus.wdata[15:8]; - if (bus.wmask[2]) ram[bus.address[14:2]][2] <= bus.wdata[23:16]; - if (bus.wmask[3]) ram[bus.address[14:2]][3] <= bus.wdata[31:24]; + if (bus.wmask[0]) ram[bus.address[13:2]][0] <= bus.wdata[7:0]; + if (bus.wmask[1]) ram[bus.address[13:2]][1] <= bus.wdata[15:8]; + if (bus.wmask[2]) ram[bus.address[13:2]][2] <= bus.wdata[23:16]; + if (bus.wmask[3]) ram[bus.address[13:2]][3] <= bus.wdata[31:24]; end end diff --git a/fw/rtl/n64/n64_bus.sv b/fw/rtl/n64/n64_bus.sv index b09700d..d85be7f 100644 --- a/fw/rtl/n64/n64_bus.sv +++ b/fw/rtl/n64/n64_bus.sv @@ -9,7 +9,6 @@ interface if_n64_bus (); logic [31:0] address; logic [15:0] wdata; logic [15:0] rdata; - logic n64_active; logic [31:0] real_address; logic read_op; logic write_op; @@ -39,7 +38,6 @@ interface if_n64_bus (); output address, output wdata, input rdata, - output n64_active, output real_address, output read_op, output write_op @@ -49,11 +47,9 @@ interface if_n64_bus (); generate for (n = 0; n < NUM_DEVICES; n++) begin : at logic device_request; - logic device_n64_active; always_comb begin device_request = request && id == sc64::e_n64_id'(n); - device_n64_active = n64_active && id == sc64::e_n64_id'(n); end modport device ( @@ -63,7 +59,6 @@ interface if_n64_bus (); input .address(address), input .wdata(wdata), output .rdata(device_rdata[n]), - input .n64_active(device_n64_active), input .real_address(real_address), input .read_op(read_op), input .write_op(write_op) diff --git a/fw/rtl/n64/n64_cfg.sv b/fw/rtl/n64/n64_cfg.sv index 0c8443c..8f7dc3f 100644 --- a/fw/rtl/n64/n64_cfg.sv +++ b/fw/rtl/n64/n64_cfg.sv @@ -15,12 +15,6 @@ module n64_cfg ( R_VERSION_L } e_reg_id; - typedef enum bit [3:0] { - R_ISV_ID_H = 4'h0, - R_ISV_ID_L = 4'h1, - R_ISV_RD_PTR = 4'hB - } e_reg_isv_id; - typedef enum bit [0:0] { S_IDLE, S_WAIT @@ -28,37 +22,26 @@ module n64_cfg ( e_state state; - logic [31:0] isv_id; - always_comb begin bus.rdata = 16'd0; if (bus.ack) begin - if (bus.address[15:14] == 2'b00) begin - case (bus.address[3:1]) - R_SR: bus.rdata = { - cfg.cpu_ready, - cfg.cpu_busy, - 1'b0, - cfg.cmd_error, - 12'd0 - }; - R_COMMAND: bus.rdata = {8'd0, cfg.cmd}; - R_DATA_0_H: bus.rdata = cfg.data[0][31:16]; - R_DATA_0_L: bus.rdata = cfg.data[0][15:0]; - R_DATA_1_H: bus.rdata = cfg.data[1][31:16]; - R_DATA_1_L: bus.rdata = cfg.data[1][15:0]; - R_VERSION_H: bus.rdata = sc64::SC64_VER[31:16]; - R_VERSION_L: bus.rdata = sc64::SC64_VER[15:0]; - default: bus.rdata = 16'd0; - endcase - end else if (bus.address[15:14] == 2'b11) begin - case (bus.address[4:1]) - R_ISV_ID_H: bus.rdata = isv_id[31:16]; - R_ISV_ID_L: bus.rdata = isv_id[15:0]; - R_ISV_RD_PTR: bus.rdata = cfg.isv_rd_ptr; - default: bus.rdata = 16'd0; - endcase - end + case (bus.address[3:1]) + R_SR: bus.rdata = { + cfg.cpu_ready, + cfg.cpu_busy, + 1'b0, + cfg.cmd_error, + 12'd0 + }; + R_COMMAND: bus.rdata = {8'd0, cfg.cmd}; + R_DATA_0_H: bus.rdata = cfg.data[0][31:16]; + R_DATA_0_L: bus.rdata = cfg.data[0][15:0]; + R_DATA_1_H: bus.rdata = cfg.data[1][31:16]; + R_DATA_1_L: bus.rdata = cfg.data[1][15:0]; + R_VERSION_H: bus.rdata = sc64::SC64_VER[31:16]; + R_VERSION_L: bus.rdata = sc64::SC64_VER[15:0]; + default: bus.rdata = 16'd0; + endcase end end @@ -69,10 +52,6 @@ module n64_cfg ( if (cfg.data_write[0]) cfg.data[0] <= cfg.wdata; if (cfg.data_write[1]) cfg.data[1] <= cfg.wdata; - if (sys.n64_soft_reset) begin - cfg.isv_rd_ptr <= 16'd0; - end - if (sys.reset) begin state <= S_IDLE; end else begin @@ -82,24 +61,16 @@ module n64_cfg ( state <= S_WAIT; bus.ack <= 1'b1; if (bus.write) begin - if (bus.address[15:14] == 2'b00) begin - case (bus.address[3:1]) - R_COMMAND: begin - cfg.cmd <= bus.wdata[7:0]; - cfg.cmd_request <= 1'b1; - end - R_DATA_0_H: cfg.data[0][31:16] <= bus.wdata; - R_DATA_0_L: cfg.data[0][15:0] <= bus.wdata; - R_DATA_1_H: cfg.data[1][31:16] <= bus.wdata; - R_DATA_1_L: cfg.data[1][15:0] <= bus.wdata; - endcase - end else if (bus.address[15:14] == 2'b11) begin - case (bus.address[4:1]) - R_ISV_ID_H: isv_id[31:16] <= bus.wdata; - R_ISV_ID_L: isv_id[15:0] <= bus.wdata; - R_ISV_RD_PTR: cfg.isv_rd_ptr <= bus.wdata; - endcase - end + case (bus.address[3:1]) + R_COMMAND: begin + cfg.cmd <= bus.wdata[7:0]; + cfg.cmd_request <= 1'b1; + end + R_DATA_0_H: cfg.data[0][31:16] <= bus.wdata; + R_DATA_0_L: cfg.data[0][15:0] <= bus.wdata; + R_DATA_1_H: cfg.data[1][31:16] <= bus.wdata; + R_DATA_1_L: cfg.data[1][15:0] <= bus.wdata; + endcase end end end diff --git a/fw/rtl/n64/n64_pi.sv b/fw/rtl/n64/n64_pi.sv index 8732cb2..517cf77 100644 --- a/fw/rtl/n64/n64_pi.sv +++ b/fw/rtl/n64/n64_pi.sv @@ -191,7 +191,6 @@ module n64_pi ( end always_comb begin - bus.n64_active = !pi_reset && pi_mode != PI_MODE_IDLE; bus.read_op = read_op; bus.write_op = write_op; end @@ -211,31 +210,30 @@ module n64_pi ( // Address decoding - logic load_next; + const bit [31:0] DDIPL_OFFSET = 32'h0780_0000; + const bit [31:0] BUFFERS_OFFSET = 32'h07C0_0000; + const bit [31:0] SAVE_OFFSET = 32'h07EE_0000; + sc64::e_n64_id next_id; logic [31:0] next_offset; logic sram_selected; - logic isv_selected; always_ff @(posedge sys.clk) begin - load_next <= 1'b0; - if (aleh_op) begin n64_pi_address_valid <= 1'b0; next_id <= sc64::__ID_N64_END; next_offset <= 32'd0; sram_selected <= 1'b0; - isv_selected <= 1'b0; if (cfg.dd_enabled) begin if (n64_pi_ad_input == 16'h0500) begin n64_pi_address_valid <= 1'b1; next_id <= sc64::ID_N64_DD; - next_offset <= cfg.ddipl_offset - 32'h0500_0000; + next_offset <= (-32'h0500_0000); end if (n64_pi_ad_input >= 16'h0600 && n64_pi_ad_input < 16'h0640) begin n64_pi_address_valid <= 1'b1; next_id <= sc64::ID_N64_SDRAM; - next_offset <= cfg.ddipl_offset - 32'h0600_0000; + next_offset <= (-32'h0600_0000) + DDIPL_OFFSET; end end if (cfg.flashram_enabled) begin @@ -243,7 +241,7 @@ module n64_pi ( n64_pi_address_valid <= 1'b1; next_id <= sc64::ID_N64_FLASHRAM; if (cfg.flashram_read_mode) begin - next_offset <= cfg.save_offset - 32'h0800_0000; + next_offset <= (-32'h0800_0000) + SAVE_OFFSET; end end end else if (cfg.sram_enabled) begin @@ -252,7 +250,7 @@ module n64_pi ( if (n64_pi_ad_input[3:2] != 2'b11 && n64_pi_ad_input[1:0] == 2'b00) begin n64_pi_address_valid <= 1'b1; next_id <= sc64::ID_N64_SDRAM; - next_offset <= cfg.save_offset - {n64_pi_ad_input[3:2], 18'd0} + {n64_pi_ad_input[3:2], 15'd0} - 32'h0800_0000; + next_offset <= (-32'h0800_0000) - {n64_pi_ad_input[3:2], 18'd0} + {n64_pi_ad_input[3:2], 15'd0} + SAVE_OFFSET; sram_selected <= 1'b1; end end @@ -260,47 +258,26 @@ module n64_pi ( if (n64_pi_ad_input == 16'h0800) begin n64_pi_address_valid <= 1'b1; next_id <= sc64::ID_N64_SDRAM; - next_offset <= cfg.save_offset - 32'h0800_0000; + next_offset <= (-32'h0800_0000) + SAVE_OFFSET; sram_selected <= 1'b1; end end end - if (n64_pi_ad_input >= 16'h1000 && n64_pi_ad_input < 16'h1400) begin + if (n64_pi_ad_input >= 16'h1000 && n64_pi_ad_input < 16'h1800) begin n64_pi_address_valid <= 1'b1; next_id <= cfg.sdram_switch ? sc64::ID_N64_SDRAM : sc64::ID_N64_BOOTLOADER; next_offset <= (-32'h1000_0000); - if (cfg.isv_enabled) begin - if (n64_pi_ad_input == 16'h13FF) begin - next_id <= sc64::ID_N64_SDRAM; - next_offset <= cfg.isv_offset - 32'h13FF_0000; - isv_selected <= 1'b1; - end - end + end + if (n64_pi_ad_input >= 16'h1F80 && n64_pi_ad_input < 16'h1FC0) begin + n64_pi_address_valid <= 1'b1; + next_id <= sc64::ID_N64_SDRAM; + next_offset <= (-32'h1F80_0000) + BUFFERS_OFFSET; end if (n64_pi_ad_input == 16'h1FFF) begin n64_pi_address_valid <= 1'b1; next_id <= sc64::ID_N64_CFG; end end - if (alel_op) begin - if (next_id == sc64::ID_N64_DD) begin - if (|n64_pi_ad_input[15:11]) begin - n64_pi_address_valid <= 1'b0; - end - end - if (sram_selected) begin - if (n64_pi_ad_input[15]) begin - n64_pi_address_valid <= 1'b0; - end - end - if (isv_selected) begin - if (n64_pi_ad_input < 16'h0020) begin - next_offset <= (-32'h13FF_0000) + 32'h0000_C000; - next_id <= sc64::ID_N64_CFG; - end - end - load_next <= 1'b1; - end end @@ -322,13 +299,13 @@ module n64_pi ( read_fifo_flush <= 1'b1; write_fifo_flush <= 1'b1; end else begin - write_fifo_flush <= starting_id == sc64::ID_N64_SDRAM && !cfg.sdram_writable && !sram_selected && !isv_selected; + write_fifo_flush <= starting_id == sc64::ID_N64_SDRAM && !cfg.sdram_writable && !sram_selected; if (aleh_op) begin starting_address[31:16] <= n64_pi_ad_input; end - if (load_next) begin + if (alel_op) begin read_fifo_flush <= 1'b1; can_read <= 1'b1; first_write_op <= 1'b1; @@ -352,9 +329,6 @@ module n64_pi ( if (load_starting_address) begin bus.id <= starting_id; bus.address <= starting_address + next_offset; - if (starting_id == sc64::ID_N64_FLASHRAM) begin - bus.address <= starting_address; - end load_starting_address <= 1'b0; end bus.wdata <= write_fifo_rdata; @@ -363,11 +337,8 @@ module n64_pi ( bus.request <= 1'b1; bus.write <= 1'b0; if (load_starting_address) begin - bus.id <= starting_id; + bus.id <= (starting_id == sc64::ID_N64_FLASHRAM && cfg.flashram_read_mode) ? sc64::ID_N64_SDRAM : starting_id; bus.address <= starting_address + next_offset; - if (starting_id == sc64::ID_N64_FLASHRAM && cfg.flashram_read_mode) begin - bus.id <= sc64::ID_N64_SDRAM; - end load_starting_address <= 1'b0; end end diff --git a/fw/rtl/system/config.sv b/fw/rtl/system/config.sv index 00fb1b4..01652c8 100644 --- a/fw/rtl/system/config.sv +++ b/fw/rtl/system/config.sv @@ -15,11 +15,6 @@ interface if_config (); logic sram_banked; logic flashram_enabled; logic flashram_read_mode; - logic isv_enabled; - logic [25:0] ddipl_offset; - logic [25:0] save_offset; - logic [25:0] isv_offset; - logic [15:0] isv_rd_ptr; logic flash_erase_start; logic flash_erase_busy; logic flash_wp_enable; @@ -32,11 +27,7 @@ interface if_config (); input sram_enabled, input sram_banked, input flashram_enabled, - input flashram_read_mode, - input isv_enabled, - input ddipl_offset, - input save_offset, - input isv_offset + input flashram_read_mode ); modport flashram ( @@ -58,8 +49,7 @@ interface if_config (); output cmd, output data, input data_write, - input wdata, - output isv_rd_ptr + input wdata ); modport cpu ( @@ -77,11 +67,6 @@ interface if_config (); output sram_enabled, output sram_banked, output flashram_enabled, - output isv_enabled, - output ddipl_offset, - output save_offset, - output isv_offset, - input isv_rd_ptr, output flash_erase_start, input flash_erase_busy, output flash_wp_enable, diff --git a/fw/rtl/usb/usb_ft1248.sv b/fw/rtl/usb/usb_ft1248.sv index c746c5b..9a86de8 100644 --- a/fw/rtl/usb/usb_ft1248.sv +++ b/fw/rtl/usb/usb_ft1248.sv @@ -133,8 +133,8 @@ module usb_ft1248 ( end else begin if (reset_ack) begin reset_pending <= 1'b0; - write_modem_status_pending <= 1'b1; reset_reply <= 1'b1; + write_modem_status_pending <= 1'b1; end if (write_buffer_flush) begin @@ -152,8 +152,8 @@ module usb_ft1248 ( reset_pending <= 1'b1; end if (last_reset_status && !ft_miosi_in[0]) begin - write_modem_status_pending <= 1'b1; reset_reply <= 1'b0; + write_modem_status_pending <= 1'b1; end end if (cmd == CMD_WRITE_MODEM_STATUS) begin @@ -193,10 +193,10 @@ module usb_ft1248 ( end if (state == STATE_DATA) begin - ft_cs = 1'b0; if (phase[0] || phase[1]) begin ft_clk = 1'b1; end + ft_cs = 1'b0; if (cmd == CMD_WRITE) begin ft_miosi_out = tx_rdata; ft_oe = 1'b1; @@ -215,12 +215,12 @@ module usb_ft1248 ( rx_wdata = ft_miosi_in; if (!ft_miso && (state == STATE_DATA) && phase[3]) begin - if (cmd == CMD_WRITE) begin - tx_read = 1'b1; - end if (cmd == CMD_READ) begin rx_write = 1'b1; end + if (cmd == CMD_WRITE) begin + tx_read = 1'b1; + end end end @@ -277,14 +277,14 @@ module usb_ft1248 ( if (phase[3]) begin if (ft_miso) begin next_state = STATE_DESELECT; - end else if (cmd == CMD_WRITE) begin - if (tx_almost_empty) begin - next_state = STATE_DESELECT; - end end else if (cmd == CMD_READ) begin if (rx_almost_full) begin next_state = STATE_DESELECT; end + end else if (cmd == CMD_WRITE) begin + if (tx_almost_empty) begin + next_state = STATE_DESELECT; + end end else begin next_state = STATE_DESELECT; end diff --git a/fw/rtl/intel/flash/intel_flash.qsys b/fw/rtl/vendor/intel/generated/intel_flash.qsys similarity index 100% rename from fw/rtl/intel/flash/intel_flash.qsys rename to fw/rtl/vendor/intel/generated/intel_flash.qsys diff --git a/fw/rtl/intel/gpio/intel_gpio_ddro.qip b/fw/rtl/vendor/intel/generated/intel_gpio_ddro.qip similarity index 100% rename from fw/rtl/intel/gpio/intel_gpio_ddro.qip rename to fw/rtl/vendor/intel/generated/intel_gpio_ddro.qip diff --git a/fw/rtl/intel/gpio/intel_gpio_ddro.v b/fw/rtl/vendor/intel/generated/intel_gpio_ddro.v similarity index 100% rename from fw/rtl/intel/gpio/intel_gpio_ddro.v rename to fw/rtl/vendor/intel/generated/intel_gpio_ddro.v diff --git a/fw/rtl/intel/gpio/intel_gpio_ddro/altera_gpio_lite.sv b/fw/rtl/vendor/intel/generated/intel_gpio_ddro/altera_gpio_lite.sv similarity index 100% rename from fw/rtl/intel/gpio/intel_gpio_ddro/altera_gpio_lite.sv rename to fw/rtl/vendor/intel/generated/intel_gpio_ddro/altera_gpio_lite.sv diff --git a/fw/rtl/intel/pll/intel_pll.ppf b/fw/rtl/vendor/intel/generated/intel_pll.ppf similarity index 100% rename from fw/rtl/intel/pll/intel_pll.ppf rename to fw/rtl/vendor/intel/generated/intel_pll.ppf diff --git a/fw/rtl/intel/pll/intel_pll.qip b/fw/rtl/vendor/intel/generated/intel_pll.qip similarity index 100% rename from fw/rtl/intel/pll/intel_pll.qip rename to fw/rtl/vendor/intel/generated/intel_pll.qip diff --git a/fw/rtl/intel/pll/intel_pll.v b/fw/rtl/vendor/intel/generated/intel_pll.v similarity index 100% rename from fw/rtl/intel/pll/intel_pll.v rename to fw/rtl/vendor/intel/generated/intel_pll.v diff --git a/fw/rtl/vendor/vendor_flash.sv b/fw/rtl/vendor/intel/vendor_flash.sv similarity index 100% rename from fw/rtl/vendor/vendor_flash.sv rename to fw/rtl/vendor/intel/vendor_flash.sv diff --git a/fw/rtl/vendor/vendor_reconfigure.sv b/fw/rtl/vendor/intel/vendor_reconfigure.sv similarity index 100% rename from fw/rtl/vendor/vendor_reconfigure.sv rename to fw/rtl/vendor/intel/vendor_reconfigure.sv diff --git a/sw/pc/sc64.py b/sw/pc/sc64.py index 24384a2..c2ed6d4 100644 --- a/sw/pc/sc64.py +++ b/sw/pc/sc64.py @@ -835,8 +835,8 @@ if __name__ == "__main__": if (disk_file): print(f"Using 64DD disk image file [{disk_file}]") sc64.set_dd_configuration_for_disk(disk_file) - print(f"Setting 64DD disk state to [Changed]") - sc64.set_dd_disk_state("changed" if disk_file else "ejected") + print(f"Setting 64DD disk state to [Inserted]") + sc64.set_dd_disk_state("inserted" if disk_file else "ejected") sc64.debug_loop(is_viewer_enabled) except SC64Exception as e: diff --git a/sw/riscv/SC64.ld b/sw/riscv/SC64.ld index 50075c3..c71e22b 100644 --- a/sw/riscv/SC64.ld +++ b/sw/riscv/SC64.ld @@ -1,6 +1,6 @@ MEMORY { rom (rx) : org = 0x00010000, len = 26k - ram (rwx) : org = 0x10000000, len = 32k + ram (rwx) : org = 0x10000000, len = 16k } ENTRY(reset_handler) diff --git a/sw/riscv/src/cfg.c b/sw/riscv/src/cfg.c index 9d720f8..a59326f 100644 --- a/sw/riscv/src/cfg.c +++ b/sw/riscv/src/cfg.c @@ -8,20 +8,6 @@ #include "usb.h" -#define SAVE_SIZE_EEPROM_4K (512) -#define SAVE_SIZE_EEPROM_16K (2048) -#define SAVE_SIZE_SRAM (32 * 1024) -#define SAVE_SIZE_FLASHRAM (128 * 1024) -#define SAVE_SIZE_SRAM_BANKED (3 * 32 * 1024) - -#define ISV_SIZE (64 * 1024) - -#define SAVE_OFFSET_PKST2 (0x01608000UL) - -#define DEFAULT_SAVE_OFFSET (0x03FD0000UL) -#define DEFAULT_DDIPL_OFFSET (0x03BD0000UL) - - enum cfg_id { CFG_ID_SCR, CFG_ID_SDRAM_SWITCH, @@ -86,8 +72,6 @@ static void set_usb_drive_not_busy (void) { } static void set_save_type (enum save_type save_type) { - uint32_t save_offset = DEFAULT_SAVE_OFFSET; - change_scr_bits(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, false); joybus_set_eeprom(EEPROM_NONE); @@ -95,37 +79,26 @@ static void set_save_type (enum save_type save_type) { case SAVE_TYPE_NONE: break; case SAVE_TYPE_EEPROM_4K: - save_offset = SDRAM_SIZE - SAVE_SIZE_EEPROM_4K - ISV_SIZE; joybus_set_eeprom(EEPROM_4K); break; case SAVE_TYPE_EEPROM_16K: - save_offset = SDRAM_SIZE - SAVE_SIZE_EEPROM_16K - ISV_SIZE; joybus_set_eeprom(EEPROM_16K); break; case SAVE_TYPE_SRAM: - save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM - ISV_SIZE; change_scr_bits(CFG_SCR_SRAM_EN, true); break; case SAVE_TYPE_FLASHRAM: - save_offset = SDRAM_SIZE - SAVE_SIZE_FLASHRAM - ISV_SIZE; change_scr_bits(CFG_SCR_FLASHRAM_EN, true); break; case SAVE_TYPE_SRAM_BANKED: - save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM_BANKED - ISV_SIZE; change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, true); break; - case SAVE_TYPE_FLASHRAM_PKST2: - save_offset = SAVE_OFFSET_PKST2; - change_scr_bits(CFG_SCR_FLASHRAM_EN, true); - break; default: save_type = SAVE_TYPE_NONE; break; } p.save_type = save_type; - - CFG->SAVE_OFFSET = save_offset; } @@ -157,10 +130,10 @@ void cfg_query (uint32_t *args) { args[1] = (uint32_t) (p.tv_type); break; case CFG_ID_SAVE_OFFEST: - args[1] = CFG->SAVE_OFFSET; + args[1] = SAVE_OFFSET; break; case CFG_ID_DDIPL_OFFEST: - args[1] = CFG->DDIPL_OFFSET; + args[1] = DDIPL_OFFSET; break; case CFG_ID_BOOT_MODE: args[1] = p.boot_mode; @@ -210,10 +183,8 @@ void cfg_update (uint32_t *args) { p.tv_type = (uint8_t) (args[1] & 0x03); break; case CFG_ID_SAVE_OFFEST: - CFG->SAVE_OFFSET = args[1]; break; case CFG_ID_DDIPL_OFFEST: - CFG->DDIPL_OFFSET = args[1]; break; case CFG_ID_BOOT_MODE: p.boot_mode = args[1]; @@ -240,7 +211,6 @@ void cfg_update (uint32_t *args) { dd_set_drive_id((uint16_t) (args[1])); break; case CFG_ID_DD_THB_TABLE_OFFSET: - dd_set_thb_table_offset(args[1]); break; case CFG_ID_IS_VIEWER_ENABLE: isv_set_enabled(args[1]); @@ -270,7 +240,6 @@ void cfg_set_time (uint32_t *args) { void cfg_init (void) { set_save_type(SAVE_TYPE_NONE); - CFG->DDIPL_OFFSET = DEFAULT_DDIPL_OFFSET; CFG->SCR = CFG_SCR_CPU_READY; p.cic_seed = 0xFFFF; diff --git a/sw/riscv/src/dd.c b/sw/riscv/src/dd.c index f8b1aee..376b07a 100644 --- a/sw/riscv/src/dd.c +++ b/sw/riscv/src/dd.c @@ -5,9 +5,10 @@ #define DD_USER_SECTORS_PER_BLOCK (85) -#define DD_BUFFERS_OFFSET (SDRAM_BASE + 0x03BC0000UL) -#define DD_THB_TABLE_OFFSET (DD_BUFFERS_OFFSET + 0x0000) -#define DD_BLOCK_BUFFER_OFFSET (DD_BUFFERS_OFFSET + 0x5000) +#define DD_BUFFERS_OFFSET (SDRAM_BASE + 0x07E5A7F8UL) +#define DD_STORAGE_TABLE_OFFSET (DD_BUFFERS_OFFSET + 0x00000000UL) +#define DD_THB_TABLE_OFFSET (DD_BUFFERS_OFFSET + 0x0007BD90UL) +#define DD_BLOCK_BUFFER_OFFSET (DD_BUFFERS_OFFSET + 0x00080700UL) #define USB_DEBUG_ID_DD_BLOCK (0xF5) @@ -187,10 +188,6 @@ uint16_t dd_get_drive_id (void) { return DD->DRIVE_ID; } -void dd_set_thb_table_offset (uint32_t offset) { - p.thb_table = (io32_t *) (SDRAM_BASE + offset); -} - uint32_t dd_get_thb_table_offset (void) { return (((uint32_t) (p.thb_table)) & 0x0FFFFFFF); } diff --git a/sw/riscv/src/dd.h b/sw/riscv/src/dd.h index 84acf95..cb45fc8 100644 --- a/sw/riscv/src/dd.h +++ b/sw/riscv/src/dd.h @@ -16,7 +16,6 @@ void dd_set_disk_state (disk_state_t disk_state); disk_state_t dd_get_disk_state (void); void dd_set_drive_id (uint16_t id); uint16_t dd_get_drive_id (void); -void dd_set_thb_table_offset (uint32_t offset); uint32_t dd_get_thb_table_offset (void); void dd_init (void); void process_dd (void); diff --git a/sw/riscv/src/flashram.c b/sw/riscv/src/flashram.c index 02c5b5a..7aeeb12 100644 --- a/sw/riscv/src/flashram.c +++ b/sw/riscv/src/flashram.c @@ -1,4 +1,4 @@ -#include "flashram.h" +#include "sys.h" #define FLASHRAM_SIZE (128 * 1024) @@ -65,7 +65,7 @@ void process_flashram (void) { p.op = get_operation_type(); if (p.op != OP_NONE) { - uint32_t sdram_address = SDRAM_BASE + CFG->SAVE_OFFSET; + uint32_t sdram_address = SDRAM_BASE + SAVE_OFFSET; p.save_in_progress = true; if (p.op != OP_ERASE_ALL) { diff --git a/sw/riscv/src/flashram.h b/sw/riscv/src/flashram.h index 2d682bc..4cd8425 100644 --- a/sw/riscv/src/flashram.h +++ b/sw/riscv/src/flashram.h @@ -2,9 +2,6 @@ #define FLASHRAM_H__ -#include "sys.h" - - void flashram_init (void); void process_flashram (void); diff --git a/sw/riscv/src/isv.c b/sw/riscv/src/isv.c index 1a48951..296ade3 100644 --- a/sw/riscv/src/isv.c +++ b/sw/riscv/src/isv.c @@ -2,13 +2,21 @@ #include "usb.h" -#define ISV_REGS_SIZE (0x20) -#define ISV_BUFFER_SIZE ((64 * 1024) - ISV_REGS_SIZE) -#define ISV_DEFAULT_OFFSET (0x03FF0000UL) +typedef struct { + io32_t __padding_1[5]; + io32_t RD_PTR; + io32_t __padding_2[2]; + io8_t BUFFER[(64 * 1024) - 0x20]; +} isv_t; + +#define ISV_BASE (SDRAM_BASE + 0x03FF0000UL) +#define ISV ((isv_t *) ISV_BASE) struct process { + bool enabled; bool ready; + uint16_t current_read_pointer; }; static struct process p; @@ -20,35 +28,36 @@ static void isv_set_ready (void) { void isv_set_enabled (bool enabled) { if (enabled) { - CFG->SCR |= CFG_SCR_ISV_EN; - CFG->ISV_CURRENT_RD_PTR = CFG->ISV_RD_PTR; + CFG->SCR |= CFG_SCR_WRITES_ON_RESET_EN; + ISV->RD_PTR = SWAP32(0); + p.enabled = true; p.ready = true; + p.current_read_pointer = 0; } else { - CFG->SCR &= ~(CFG_SCR_ISV_EN); + CFG->SCR &= ~(CFG_SCR_WRITES_ON_RESET_EN); + p.enabled = false; } } bool isv_get_enabled (void) { - return (CFG->SCR & CFG_SCR_ISV_EN); + return p.enabled; } void isv_init (void) { - CFG->ISV_OFFSET = ISV_DEFAULT_OFFSET; - p.ready = true; + p.enabled = false; } void process_isv (void) { - if (p.ready && (CFG->SCR & CFG_SCR_ISV_EN)) { - uint16_t read_pointer = CFG->ISV_RD_PTR; - uint16_t current_read_pointer = CFG->ISV_CURRENT_RD_PTR; + if (p.enabled && p.ready) { + uint16_t read_pointer = (uint16_t) (SWAP32(ISV->RD_PTR)); - if (read_pointer != current_read_pointer) { - bool wrap = read_pointer < current_read_pointer; + if (read_pointer != p.current_read_pointer) { + bool wrap = read_pointer < p.current_read_pointer; - uint32_t length = ((wrap ? ISV_BUFFER_SIZE : read_pointer) - current_read_pointer); - uint32_t offset = CFG->ISV_OFFSET + ISV_REGS_SIZE + current_read_pointer; + uint32_t length = ((wrap ? sizeof(ISV->BUFFER) : read_pointer) - p.current_read_pointer); + uint32_t offset = (((uint32_t) (&ISV->BUFFER[p.current_read_pointer])) & 0x0FFFFFFF); usb_event_t event; event.id = EVENT_ID_IS_VIEWER; @@ -57,7 +66,7 @@ void process_isv (void) { uint32_t data[2] = { length, offset }; if (usb_put_event(&event, data, sizeof(data))) { - CFG->ISV_CURRENT_RD_PTR = wrap ? 0 : read_pointer; + p.current_read_pointer = wrap ? 0 : read_pointer; p.ready = false; } } diff --git a/sw/riscv/src/joybus.c b/sw/riscv/src/joybus.c index 2e93af1..f70f931 100644 --- a/sw/riscv/src/joybus.c +++ b/sw/riscv/src/joybus.c @@ -1,5 +1,6 @@ #include "joybus.h" #include "rtc.h" +#include "sys.h" #define CMD_EEPROM_STATUS (0x00) @@ -83,7 +84,7 @@ void process_joybus (void) { } if (p.eeprom_type != EEPROM_NONE) { - save_data = (io32_t *) (SDRAM_BASE + CFG->SAVE_OFFSET + (rx_data[1] * EEPROM_PAGE_SIZE)); + save_data = (io32_t *) (SDRAM_BASE + SAVE_OFFSET + (rx_data[1] * EEPROM_PAGE_SIZE)); switch (rx_data[0]) { case CMD_EEPROM_STATUS: tx_data[1] = p.eeprom_type == EEPROM_16K ? EEPROM_ID_16K : EEPROM_ID_4K; diff --git a/sw/riscv/src/joybus.h b/sw/riscv/src/joybus.h index ef2d21f..8a9f703 100644 --- a/sw/riscv/src/joybus.h +++ b/sw/riscv/src/joybus.h @@ -2,9 +2,6 @@ #define JOYBUS_H__ -#include "sys.h" - - enum eeprom_type { EEPROM_NONE, EEPROM_4K, diff --git a/sw/riscv/src/sys.h b/sw/riscv/src/sys.h index 29b3610..5563cb0 100644 --- a/sw/riscv/src/sys.h +++ b/sw/riscv/src/sys.h @@ -21,6 +21,10 @@ typedef volatile uint16_t io16_t; typedef volatile uint32_t io32_t; +#define DDIPL_OFFSET (0x07800000UL) +#define SAVE_OFFSET (0x07EE0000UL) + + #define FLASH_BASE (0x00000000UL) #define FLASH_SIZE (0x39800) #define FLASH (*((io32_t *) FLASH_BASE)) @@ -33,16 +37,11 @@ typedef volatile uint32_t io32_t; typedef volatile struct cfg_regs { io32_t SCR; - io32_t DDIPL_OFFSET; - io32_t SAVE_OFFSET; io8_t CMD; io8_t __padding[3]; io32_t DATA[2]; io32_t VERSION; io32_t RECONFIGURE; - io32_t ISV_OFFSET; - io16_t ISV_RD_PTR; - io16_t ISV_CURRENT_RD_PTR; } cfg_regs_t; #define CFG_BASE (0x20000000UL) @@ -55,7 +54,7 @@ typedef volatile struct cfg_regs { #define CFG_SCR_SRAM_BANKED (1 << 4) #define CFG_SCR_FLASHRAM_EN (1 << 5) #define CFG_SCR_SKIP_BOOTLOADER (1 << 6) -#define CFG_SCR_ISV_EN (1 << 7) +#define CFG_SCR_WRITES_ON_RESET_EN (1 << 7) #define CFG_SCR_FLASH_ERASE_START (1 << 24) #define CFG_SCR_FLASH_ERASE_BUSY (1 << 25) #define CFG_SCR_FLASH_WP_ENABLE (1 << 26)