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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2025-01-11 12:09:08 +01:00
flashram fixes
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be006aff10
commit
8a2a729a69
@ -285,7 +285,7 @@ void cfg_update_config (uint32_t *args) {
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void cfg_set_save_type (uint8_t type) {
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CFG->SCR &= ~(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN);
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uint32_t save_offset = 0;
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uint32_t save_offset = DEFAULT_SAVE_OFFSET;
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switch (type) {
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case 0: {
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@ -68,7 +68,7 @@ module cpu_flashram (
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flashram.operation_done <= 1'b0;
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if (bus.request) begin
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if (!bus.address[5] && bus.wmask[0]) begin
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if (!bus.address[7] && bus.wmask[0]) begin
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flashram.operation_done <= bus.wdata[1];
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end
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end
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@ -44,7 +44,7 @@ module cpu_sdram (
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bus.rdata = rdata;
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end
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sdram.write = current_word ? &bus.wmask[3:2] : &bus.wmask[1:0];
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sdram.write = current_word ? &bus.wmask[1:0] : &bus.wmask[3:2];
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sdram.address = {1'b0, bus.address[30:2], current_word, 1'b0};
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sdram.wdata = current_word ? bus.wdata[15:0] : bus.wdata[31:16];
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end
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@ -44,21 +44,25 @@ module n64_flashram (
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logic [7:0] flashram_command;
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logic flashram_erase_enabled;
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logic [1:0][15:0] write_buffer [0:31];
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logic [31:0] write_buffer [0:31];
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logic [1:0] write_buffer_wmask;
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logic [15:0] high_buffer;
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always_comb begin
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write_buffer_wmask = 2'b00;
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if (bus.request && bus.write && !bus.address[16] && flashram_state == FS_BUFFER) begin
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write_buffer_wmask[0] = bus.address[1];
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write_buffer_wmask[1] = !bus.address[1];
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write_buffer_wmask[0] = !bus.address[1];
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write_buffer_wmask[1] = bus.address[1];
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end
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end
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always_ff @(posedge sys.clk) begin
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if (write_buffer_wmask[0]) high_buffer <= bus.wdata;
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end
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always @(posedge sys.clk) begin
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flashram.rdata <= {write_buffer[flashram.address][1], write_buffer[flashram.address][0]};
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if (write_buffer_wmask[0]) write_buffer[bus.address[6:2]][0] <= bus.wdata;
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if (write_buffer_wmask[1]) write_buffer[bus.address[6:2]][1] <= bus.wdata;
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flashram.rdata <= write_buffer[flashram.address];
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if (write_buffer_wmask[1]) write_buffer[bus.address[6:2]] <= {high_buffer, bus.wdata};
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end
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always_comb begin
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