diff --git a/fw/rtl/cpu/cpu_cfg.sv b/fw/rtl/cpu/cpu_cfg.sv index da2f0c1..cd1ccf7 100644 --- a/fw/rtl/cpu/cpu_cfg.sv +++ b/fw/rtl/cpu/cpu_cfg.sv @@ -51,7 +51,7 @@ module cpu_cfg ( R_DATA_0: bus.rdata = cfg.data[0]; R_DATA_1: bus.rdata = cfg.data[1]; R_VERSION: bus.rdata = sc64::SC64_VER; - R_RECONFIGURE: bus.rdata = {31'd0, trigger_reconfiguration}; + R_RECONFIGURE: bus.rdata = RECONFIGURE_MAGIC; default: bus.rdata = 32'd0; endcase end diff --git a/sw/pc/update.py b/sw/pc/update.py index 1432798..43978f3 100644 --- a/sw/pc/update.py +++ b/sw/pc/update.py @@ -11,7 +11,7 @@ class SC64: def __init__(self, port): - self.__serial = serial.Serial(port) + self.__serial = serial.Serial(port, timeout=10.0, write_timeout=10.0) def __query_config(self, query, arg=0): @@ -35,12 +35,12 @@ class SC64: def reconfigure(self): magic = self.__query_config(self.__CFG_ID_RECONFIGURE) self.__change_config(self.__CFG_ID_RECONFIGURE, magic, ignore_response=True) - time.sleep(1) + time.sleep(0.2) def read_flash(self, file): size = self.__query_config(self.__CFG_ID_FLASH_OPERATION) - print('Flash size: {:08X}'.format(size)) + print(f'Flash size: {(size / 1024.0):1.1f} kB') self.__serial.write(b'CMDR') self.__serial.write((0).to_bytes(4, byteorder='big')) self.__serial.write((size).to_bytes(4, byteorder='big')) diff --git a/sw/riscv/src/cfg.c b/sw/riscv/src/cfg.c index 0889df0..ff9923d 100644 --- a/sw/riscv/src/cfg.c +++ b/sw/riscv/src/cfg.c @@ -139,8 +139,8 @@ void cfg_update (uint32_t *args) { flash_program(args[1]); break; case CFG_ID_RECONFIGURE: - if (args[1] == CFG_RECONFIGURE_MAGIC) { - CFG->RECONFIGURE = CFG_RECONFIGURE_MAGIC; + if (args[1] == CFG->RECONFIGURE) { + CFG->RECONFIGURE = args[1]; __asm__ volatile ( "ebreak \n" ); @@ -185,7 +185,7 @@ void cfg_query (uint32_t *args) { args[1] = flash_read(args[1]); break; case CFG_ID_RECONFIGURE: - args[1] = CFG_RECONFIGURE_MAGIC; + args[1] = CFG->RECONFIGURE; break; } } diff --git a/sw/riscv/src/sys.h b/sw/riscv/src/sys.h index 728a894..41d5f2e 100644 --- a/sw/riscv/src/sys.h +++ b/sw/riscv/src/sys.h @@ -115,8 +115,6 @@ typedef volatile struct cfg_regs { #define CFG_SCR_CPU_BUSY (1 << 30) #define CFG_SCR_CPU_READY (1 << 31) -#define CFG_RECONFIGURE_MAGIC (0x52535446) - #define SDRAM_BASE (0x80000000UL) #define SDRAM (*((io32_t *) SDRAM_BASE))