From 9599db830740a6d2f2d4e923bfdbde61ba12306a Mon Sep 17 00:00:00 2001 From: Mateusz Faderewski Date: Sun, 5 May 2024 07:08:44 +0200 Subject: [PATCH] [SC64][FW] Set timing constraints for SDRAM pins --- fw/project/lcmxo2/sc64.lpf | 43 +++++++++++++++++++ .../lcmxo2/generated/pll_lattice_generated.v | 10 ++--- fw/rtl/vendor/lcmxo2/pll.sv | 4 +- 3 files changed, 50 insertions(+), 7 deletions(-) diff --git a/fw/project/lcmxo2/sc64.lpf b/fw/project/lcmxo2/sc64.lpf index 4ce07ec..6feb8ab 100644 --- a/fw/project/lcmxo2/sc64.lpf +++ b/fw/project/lcmxo2/sc64.lpf @@ -96,6 +96,9 @@ IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; IOBUF PORT "sdram_ras" PULLMODE=NONE IO_TYPE=LVCMOS33 ; IOBUF PORT "sdram_we" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "test_point[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "test_point[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "test_point[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; IOBUF PORT "usb_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ; IOBUF PORT "usb_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ; IOBUF PORT "usb_miosi[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; @@ -216,3 +219,43 @@ BLOCK PATH TO PORT "mcu_int" ; BLOCK PATH TO PORT "n64_irq" ; BLOCK PATH FROM PORT "usb_pwrsav" ; BLOCK PATH FROM PORT "sd_det" ; +DEFINE PORT GROUP "sdram_output" "sdram_cs" +"sdram_ras" +"sdram_cas" +"sdram_we" +"sdram_ba[1]" +"sdram_ba[0]" +"sdram_a[12]" +"sdram_a[11]" +"sdram_a[10]" +"sdram_a[9]" +"sdram_a[8]" +"sdram_a[7]" +"sdram_a[6]" +"sdram_a[5]" +"sdram_a[4]" +"sdram_a[3]" +"sdram_a[2]" +"sdram_a[1]" +"sdram_a[0]" +"sdram_dqm[1]" +"sdram_dqm[0]" ; +DEFINE PORT GROUP "sdram_bidir" "sdram_dq[15]" +"sdram_dq[14]" +"sdram_dq[13]" +"sdram_dq[12]" +"sdram_dq[11]" +"sdram_dq[10]" +"sdram_dq[9]" +"sdram_dq[8]" +"sdram_dq[7]" +"sdram_dq[6]" +"sdram_dq[5]" +"sdram_dq[4]" +"sdram_dq[3]" +"sdram_dq[2]" +"sdram_dq[1]" +"sdram_dq[0]" ; +INPUT_SETUP GROUP "sdram_bidir"INPUT_DELAY 5.400000 ns HOLD -2.500000 ns CLKNET "clk" CLK_OFFSET -0.250000 X ; +CLOCK_TO_OUT GROUP "sdram_output" OUTPUT_DELAY 1.500000 ns MIN 0.800000 ns CLKNET "clk" CLKOUT PORT "sdram_clk" ; +CLOCK_TO_OUT GROUP "sdram_bidir" OUTPUT_DELAY 1.500000 ns MIN 0.800000 ns CLKNET "clk" CLKOUT PORT "sdram_clk" ; diff --git a/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v b/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v index 5f3ad98..964fe17 100644 --- a/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v +++ b/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v @@ -1,7 +1,7 @@ -/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.13.0.56.2 */ /* Module Version: 5.7 */ -/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll_lattice_generated -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 100 -fclkop_tol 0.0 -fclkos 100 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 90 -trims_r -phase_cntl STATIC -fb_mode 1 -lock */ -/* Sat Mar 19 17:10:12 2022 */ +/* C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n pll_lattice_generated -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 100 -fclkop_tol 0.0 -fclkos 100 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 270 -trims_r -phase_cntl STATIC -fb_mode 1 -lock */ +/* Sun May 05 06:07:05 2024 */ `timescale 1 ns / 1 ps @@ -29,8 +29,8 @@ module pll_lattice_generated (CLKI, CLKOP, CLKOS, LOCK)/* synthesis NGD_DRC_MASK defparam PLLInst_0.CLKOS3_CPHASE = 0 ; defparam PLLInst_0.CLKOS2_FPHASE = 0 ; defparam PLLInst_0.CLKOS2_CPHASE = 0 ; - defparam PLLInst_0.CLKOS_FPHASE = 2 ; - defparam PLLInst_0.CLKOS_CPHASE = 5 ; + defparam PLLInst_0.CLKOS_FPHASE = 6 ; + defparam PLLInst_0.CLKOS_CPHASE = 7 ; defparam PLLInst_0.CLKOP_FPHASE = 0 ; defparam PLLInst_0.CLKOP_CPHASE = 4 ; defparam PLLInst_0.PLL_LOCK_MODE = 0 ; diff --git a/fw/rtl/vendor/lcmxo2/pll.sv b/fw/rtl/vendor/lcmxo2/pll.sv index 30c63d4..88d958f 100644 --- a/fw/rtl/vendor/lcmxo2/pll.sv +++ b/fw/rtl/vendor/lcmxo2/pll.sv @@ -17,8 +17,8 @@ module pll ( ); ODDRXE oddrxe_sdram_clk_inst ( - .D0(1'b0), - .D1(1'b1), + .D0(1'b1), + .D1(1'b0), .SCLK(pll_sdram_clk), .RST(1'b0), .Q(buf_sdram_clk)