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[SC64][SW] Fix linguist-vendored 2

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This commit is contained in:
Mateusz Faderewski 2022-11-10 16:47:42 +01:00
parent b5734982f3
commit a36e013574
10 changed files with 11433 additions and 11433 deletions
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2
.gitattributes vendored
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@ -1 +1 @@
sw/controller/lib/* linguist-vendored sw/controller/inc/* linguist-vendored

2
sw/controller/common.mk
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@ -6,7 +6,7 @@ OBJDUMP = $(TOOLCHAIN)objdump
SIZE = $(TOOLCHAIN)size SIZE = $(TOOLCHAIN)size
FLAGS = -mcpu=cortex-m0plus -mthumb -DSTM32G030xx $(USER_FLAGS) -g -ggdb3 FLAGS = -mcpu=cortex-m0plus -mthumb -DSTM32G030xx $(USER_FLAGS) -g -ggdb3
CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP -I./lib CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP -I./inc
LDFLAGS = -nostartfiles -Wl,--gc-sections LDFLAGS = -nostartfiles -Wl,--gc-sections
SRC_DIR = src SRC_DIR = src

566
sw/controller/lib/cmsis_compiler.h → sw/controller/inc/cmsis_compiler.h vendored
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@ -1,283 +1,283 @@
/**************************************************************************//** /**************************************************************************//**
* @file cmsis_compiler.h * @file cmsis_compiler.h
* @brief CMSIS compiler generic header file * @brief CMSIS compiler generic header file
* @version V5.1.0 * @version V5.1.0
* @date 09. October 2018 * @date 09. October 2018
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#ifndef __CMSIS_COMPILER_H #ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H
#include <stdint.h> #include <stdint.h>
/* /*
* Arm Compiler 4/5 * Arm Compiler 4/5
*/ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/* /*
* Arm Compiler 6.6 LTM (armclang) * Arm Compiler 6.6 LTM (armclang)
*/ */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h" #include "cmsis_armclang_ltm.h"
/* /*
* Arm Compiler above 6.10.1 (armclang) * Arm Compiler above 6.10.1 (armclang)
*/ */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h" #include "cmsis_armclang.h"
/* /*
* GNU Compiler * GNU Compiler
*/ */
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/* /*
* IAR Compiler * IAR Compiler
*/ */
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h> #include <cmsis_iccarm.h>
/* /*
* TI Arm Compiler * TI Arm Compiler
*/ */
#elif defined ( __TI_ARM__ ) #elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
#ifndef __ASM #ifndef __ASM
#define __ASM __asm #define __ASM __asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn)) #define __NO_RETURN __attribute__((noreturn))
#endif #endif
#ifndef __USED #ifndef __USED
#define __USED __attribute__((used)) #define __USED __attribute__((used))
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __attribute__((weak)) #define __WEAK __attribute__((weak))
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED __attribute__((packed)) #define __PACKED __attribute__((packed))
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed)) #define __PACKED_STRUCT struct __attribute__((packed))
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed)) #define __PACKED_UNION union __attribute__((packed))
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x))) #define __ALIGNED(x) __attribute__((aligned(x)))
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#define __RESTRICT __restrict #define __RESTRICT __restrict
#endif #endif
#ifndef __COMPILER_BARRIER #ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0 #define __COMPILER_BARRIER() (void)0
#endif #endif
/* /*
* TASKING Compiler * TASKING Compiler
*/ */
#elif defined ( __TASKING__ ) #elif defined ( __TASKING__ )
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
#ifndef __ASM #ifndef __ASM
#define __ASM __asm #define __ASM __asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn)) #define __NO_RETURN __attribute__((noreturn))
#endif #endif
#ifndef __USED #ifndef __USED
#define __USED __attribute__((used)) #define __USED __attribute__((used))
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __attribute__((weak)) #define __WEAK __attribute__((weak))
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED __packed__ #define __PACKED __packed__
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__ #define __PACKED_STRUCT struct __packed__
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__ #define __PACKED_UNION union __packed__
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; }; struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#define __ALIGNED(x) __align(x) #define __ALIGNED(x) __align(x)
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT #define __RESTRICT
#endif #endif
#ifndef __COMPILER_BARRIER #ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0 #define __COMPILER_BARRIER() (void)0
#endif #endif
/* /*
* COSMIC Compiler * COSMIC Compiler
*/ */
#elif defined ( __CSMC__ ) #elif defined ( __CSMC__ )
#include <cmsis_csm.h> #include <cmsis_csm.h>
#ifndef __ASM #ifndef __ASM
#define __ASM _asm #define __ASM _asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here // NO RETURN is automatically detected hence no warning here
#define __NO_RETURN #define __NO_RETURN
#endif #endif
#ifndef __USED #ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored. #warning No compiler specific solution for __USED. __USED is ignored.
#define __USED #define __USED
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __weak #define __WEAK __weak
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED @packed #define __PACKED @packed
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct #define __PACKED_STRUCT @packed struct
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION @packed union #define __PACKED_UNION @packed union
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; }; @packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x) #define __ALIGNED(x)
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT #define __RESTRICT
#endif #endif
#ifndef __COMPILER_BARRIER #ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0 #define __COMPILER_BARRIER() (void)0
#endif #endif
#else #else
#error Unknown compiler. #error Unknown compiler.
#endif #endif
#endif /* __CMSIS_COMPILER_H */ #endif /* __CMSIS_COMPILER_H */

4336
sw/controller/lib/cmsis_gcc.h → sw/controller/inc/cmsis_gcc.h vendored
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78
sw/controller/lib/cmsis_version.h → sw/controller/inc/cmsis_version.h vendored
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@ -1,39 +1,39 @@
/**************************************************************************//** /**************************************************************************//**
* @file cmsis_version.h * @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions * @brief CMSIS Core(M) Version definitions
* @version V5.0.3 * @version V5.0.3
* @date 24. June 2019 * @date 24. June 2019
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CMSIS_VERSION_H #ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H #define __CMSIS_VERSION_H
/* CMSIS Version definitions */ /* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif #endif

2170
sw/controller/lib/core_cm0plus.h → sw/controller/inc/core_cm0plus.h vendored
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544
sw/controller/lib/mpu_armv7.h → sw/controller/inc/mpu_armv7.h vendored
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@ -1,272 +1,272 @@
/****************************************************************************** /******************************************************************************
* @file mpu_armv7.h * @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU * @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0 * @version V5.1.0
* @date 08. March 2019 * @date 08. March 2019
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved. * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef ARM_MPU_ARMV7_H #ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value /** MPU Region Base Address Register Value
* *
* \param Region The region to be configured, number 0 to 15. * \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region. * \param BaseAddress The base address for the region.
*/ */
#define ARM_MPU_RBAR(Region, BaseAddress) \ #define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \ ((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk)) (MPU_RBAR_VALID_Msk))
/** /**
* MPU Memory Access Attributes * MPU Memory Access Attributes
* *
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters. * \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/ */
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/** /**
* MPU Region Attribute and Size Register Value * MPU Region Attribute and Size Register Value
* *
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field. * \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K. * \param Size Region size of the region to be configured, for example 4K, 8K.
*/ */
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk)))) (((MPU_RASR_ENABLE_Msk))))
/** /**
* MPU Region Attribute and Size Register Value * MPU Region Attribute and Size Register Value
* *
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters. * \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field. * \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K. * \param Size Region size of the region to be configured, for example 4K, 8K.
*/ */
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/** /**
* MPU Memory Access Attribute for strongly ordered memory. * MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b * - TEX: 000b
* - Shareable * - Shareable
* - Non-cacheable * - Non-cacheable
* - Non-bufferable * - Non-bufferable
*/ */
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/** /**
* MPU Memory Access Attribute for device memory. * MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable) * - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable * - Shareable or non-shareable
* - Non-cacheable * - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable) * - Bufferable (if shareable) or non-bufferable (if non-shareable)
* *
* \param IsShareable Configures the device memory as shareable or non-shareable. * \param IsShareable Configures the device memory as shareable or non-shareable.
*/ */
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/** /**
* MPU Memory Access Attribute for normal memory. * MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules) * - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable * - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules) * - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules) * - Bufferable or non-bufferable (reflecting inner cacheability rules)
* *
* \param OuterCp Configures the outer cache policy. * \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy. * \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable. * \param IsShareable Configures the memory as shareable or non-shareable.
*/ */
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/** /**
* MPU Memory Access Attribute non-cacheable policy. * MPU Memory Access Attribute non-cacheable policy.
*/ */
#define ARM_MPU_CACHEP_NOCACHE 0U #define ARM_MPU_CACHEP_NOCACHE 0U
/** /**
* MPU Memory Access Attribute write-back, write and read allocate policy. * MPU Memory Access Attribute write-back, write and read allocate policy.
*/ */
#define ARM_MPU_CACHEP_WB_WRA 1U #define ARM_MPU_CACHEP_WB_WRA 1U
/** /**
* MPU Memory Access Attribute write-through, no write allocate policy. * MPU Memory Access Attribute write-through, no write allocate policy.
*/ */
#define ARM_MPU_CACHEP_WT_NWA 2U #define ARM_MPU_CACHEP_WT_NWA 2U
/** /**
* MPU Memory Access Attribute write-back, no write allocate policy. * MPU Memory Access Attribute write-back, no write allocate policy.
*/ */
#define ARM_MPU_CACHEP_WB_NWA 3U #define ARM_MPU_CACHEP_WB_NWA 3U
/** /**
* Struct for a single MPU Region * Struct for a single MPU Region
*/ */
typedef struct { typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t; } ARM_MPU_Region_t;
/** Enable the MPU. /** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions. * \param MPU_Control Default access permissions for unconfigured regions.
*/ */
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{ {
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
__DSB(); __DSB();
__ISB(); __ISB();
} }
/** Disable the MPU. /** Disable the MPU.
*/ */
__STATIC_INLINE void ARM_MPU_Disable(void) __STATIC_INLINE void ARM_MPU_Disable(void)
{ {
__DMB(); __DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
} }
/** Clear and disable the given MPU region. /** Clear and disable the given MPU region.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{ {
MPU->RNR = rnr; MPU->RNR = rnr;
MPU->RASR = 0U; MPU->RASR = 0U;
} }
/** Configure an MPU region. /** Configure an MPU region.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rsar Value for RSAR register. * \param rsar Value for RSAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{ {
MPU->RBAR = rbar; MPU->RBAR = rbar;
MPU->RASR = rasr; MPU->RASR = rasr;
} }
/** Configure the given MPU region. /** Configure the given MPU region.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rsar Value for RSAR register. * \param rsar Value for RSAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{ {
MPU->RNR = rnr; MPU->RNR = rnr;
MPU->RBAR = rbar; MPU->RBAR = rbar;
MPU->RASR = rasr; MPU->RASR = rasr;
} }
/** Memcopy with strictly ordered memory access, e.g. for register targets. /** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to. * \param dst Destination data is copied to.
* \param src Source data is copied from. * \param src Source data is copied from.
* \param len Amount of data words to be copied. * \param len Amount of data words to be copied.
*/ */
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{ {
uint32_t i; uint32_t i;
for (i = 0U; i < len; ++i) for (i = 0U; i < len; ++i)
{ {
dst[i] = src[i]; dst[i] = src[i];
} }
} }
/** Load the given number of MPU regions from a table. /** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) { while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES; table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES;
} }
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
} }
#endif #endif

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@ -1,249 +1,249 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32g0xx.h * @file stm32g0xx.h
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains: * is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select: * - Configuration section that allows to select:
* - The STM32G0xx device used in the target application * - The STM32G0xx device used in the target application
* - To use or not the peripherals drivers in application code(i.e. * - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers * code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by * rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER" * "#define USE_HAL_DRIVER"
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2018-2021 STMicroelectronics. * Copyright (c) 2018-2021 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32g0xx /** @addtogroup stm32g0xx
* @{ * @{
*/ */
#ifndef STM32G0xx_H #ifndef STM32G0xx_H
#define STM32G0xx_H #define STM32G0xx_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif /* __cplusplus */ #endif /* __cplusplus */
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/** /**
* @brief STM32 Family * @brief STM32 Family
*/ */
#if !defined (STM32G0) #if !defined (STM32G0)
#define STM32G0 #define STM32G0
#endif /* STM32G0 */ #endif /* STM32G0 */
/* Uncomment the line below according to the target STM32G0 device used in your /* Uncomment the line below according to the target STM32G0 device used in your
application application
*/ */
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \ #if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \
&& !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \ && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \
&& !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \ && !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \
&& !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx) && !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx)
/* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */ /* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */
/* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */ /* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */
/* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */ /* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */
/* #define STM32G070xx */ /*!< STM32G070xx Devices */ /* #define STM32G070xx */ /*!< STM32G070xx Devices */
/* #define STM32G071xx */ /*!< STM32G071xx Devices */ /* #define STM32G071xx */ /*!< STM32G071xx Devices */
/* #define STM32G081xx */ /*!< STM32G081xx Devices */ /* #define STM32G081xx */ /*!< STM32G081xx Devices */
/* #define STM32G050xx */ /*!< STM32G050xx Devices */ /* #define STM32G050xx */ /*!< STM32G050xx Devices */
/* #define STM32G051xx */ /*!< STM32G051xx Devices */ /* #define STM32G051xx */ /*!< STM32G051xx Devices */
/* #define STM32G061xx */ /*!< STM32G061xx Devices */ /* #define STM32G061xx */ /*!< STM32G061xx Devices */
/* #define STM32G030xx */ /*!< STM32G030xx Devices */ /* #define STM32G030xx */ /*!< STM32G030xx Devices */
/* #define STM32G031xx */ /*!< STM32G031xx Devices */ /* #define STM32G031xx */ /*!< STM32G031xx Devices */
/* #define STM32G041xx */ /*!< STM32G041xx Devices */ /* #define STM32G041xx */ /*!< STM32G041xx Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor. devices, you can define the device in your toolchain compiler preprocessor.
*/ */
#if !defined (USE_HAL_DRIVER) #if !defined (USE_HAL_DRIVER)
/** /**
* @brief Comment the line below if you will not use the peripherals drivers. * @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
/*#define USE_HAL_DRIVER */ /*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number $VERSION$ * @brief CMSIS Device version number $VERSION$
*/ */
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
#define __STM32G0_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32G0_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ #define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
|(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\ |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32G0_CMSIS_VERSION_RC)) |(__STM32G0_CMSIS_VERSION_RC))
/** /**
* @} * @}
*/ */
/** @addtogroup Device_Included /** @addtogroup Device_Included
* @{ * @{
*/ */
#if defined(STM32G0B1xx) #if defined(STM32G0B1xx)
#include "stm32g0b1xx.h" #include "stm32g0b1xx.h"
#elif defined(STM32G0C1xx) #elif defined(STM32G0C1xx)
#include "stm32g0c1xx.h" #include "stm32g0c1xx.h"
#elif defined(STM32G0B0xx) #elif defined(STM32G0B0xx)
#include "stm32g0b0xx.h" #include "stm32g0b0xx.h"
#elif defined(STM32G071xx) #elif defined(STM32G071xx)
#include "stm32g071xx.h" #include "stm32g071xx.h"
#elif defined(STM32G081xx) #elif defined(STM32G081xx)
#include "stm32g081xx.h" #include "stm32g081xx.h"
#elif defined(STM32G070xx) #elif defined(STM32G070xx)
#include "stm32g070xx.h" #include "stm32g070xx.h"
#elif defined(STM32G031xx) #elif defined(STM32G031xx)
#include "stm32g031xx.h" #include "stm32g031xx.h"
#elif defined(STM32G041xx) #elif defined(STM32G041xx)
#include "stm32g041xx.h" #include "stm32g041xx.h"
#elif defined(STM32G030xx) #elif defined(STM32G030xx)
#include "stm32g030xx.h" #include "stm32g030xx.h"
#elif defined(STM32G051xx) #elif defined(STM32G051xx)
#include "stm32g051xx.h" #include "stm32g051xx.h"
#elif defined(STM32G061xx) #elif defined(STM32G061xx)
#include "stm32g061xx.h" #include "stm32g061xx.h"
#elif defined(STM32G050xx) #elif defined(STM32G050xx)
#include "stm32g050xx.h" #include "stm32g050xx.h"
#else #else
#error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)" #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
#endif #endif
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_types /** @addtogroup Exported_types
* @{ * @{
*/ */
typedef enum typedef enum
{ {
RESET = 0, RESET = 0,
SET = !RESET SET = !RESET
} FlagStatus, ITStatus; } FlagStatus, ITStatus;
typedef enum typedef enum
{ {
DISABLE = 0, DISABLE = 0,
ENABLE = !DISABLE ENABLE = !DISABLE
} FunctionalState; } FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum typedef enum
{ {
SUCCESS = 0, SUCCESS = 0,
ERROR = !SUCCESS ERROR = !SUCCESS
} ErrorStatus; } ErrorStatus;
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_macros /** @addtogroup Exported_macros
* @{ * @{
*/ */
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) #define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT)) #define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0)) #define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) #define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG)) #define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/* Use of interrupt control for register exclusive access */ /* Use of interrupt control for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */ /* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \ #define ATOMIC_SET_BIT(REG, BIT) \
do { \ do { \
uint32_t primask; \ uint32_t primask; \
primask = __get_PRIMASK(); \ primask = __get_PRIMASK(); \
__set_PRIMASK(1); \ __set_PRIMASK(1); \
SET_BIT((REG), (BIT)); \ SET_BIT((REG), (BIT)); \
__set_PRIMASK(primask); \ __set_PRIMASK(primask); \
} while(0) } while(0)
/* Atomic 32-bit register access macro to clear one or several bits */ /* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \ #define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \ do { \
uint32_t primask; \ uint32_t primask; \
primask = __get_PRIMASK(); \ primask = __get_PRIMASK(); \
__set_PRIMASK(1); \ __set_PRIMASK(1); \
CLEAR_BIT((REG), (BIT)); \ CLEAR_BIT((REG), (BIT)); \
__set_PRIMASK(primask); \ __set_PRIMASK(primask); \
} while(0) } while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */ /* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \ do { \
uint32_t primask; \ uint32_t primask; \
primask = __get_PRIMASK(); \ primask = __get_PRIMASK(); \
__set_PRIMASK(1); \ __set_PRIMASK(1); \
MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
__set_PRIMASK(primask); \ __set_PRIMASK(primask); \
} while(0) } while(0)
/* Atomic 16-bit register access macro to set one or several bits */ /* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \ #define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
/* Atomic 16-bit register access macro to clear one or several bits */ /* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \ #define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
/* Atomic 16-bit register access macro to clear and set one or several bits */ /* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/ /*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/
/** /**
* @} * @}
*/ */
#if defined (USE_HAL_DRIVER) #if defined (USE_HAL_DRIVER)
#include "stm32g0xx_hal.h" #include "stm32g0xx_hal.h"
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
#endif /* STM32G0xx_H */ #endif /* STM32G0xx_H */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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sw/controller/lib/system_stm32g0xx.h → sw/controller/inc/system_stm32g0xx.h vendored
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