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DMA write wmask fix

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This commit is contained in:
Mateusz Faderewski 2023-05-06 00:13:43 +02:00
parent 647aa5cfc9
commit a9ee74f480
1 changed files with 12 additions and 9 deletions
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21
fw/rtl/memory/memory_dma.sv
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@ -64,6 +64,7 @@ module memory_dma (
// RX FIFO controller // RX FIFO controller
logic [1:0] rx_wmask;
logic rx_rdata_pop; logic rx_rdata_pop;
logic rx_rdata_shift; logic rx_rdata_shift;
logic rx_rdata_valid; logic rx_rdata_valid;
@ -91,11 +92,11 @@ module memory_dma (
if (dma_start) begin if (dma_start) begin
if (dma_scb.starting_address[0]) begin if (dma_scb.starting_address[0]) begin
mem_bus.wmask <= 2'b01; rx_wmask <= 2'b01;
rx_buffer_counter <= 2'd1; rx_buffer_counter <= 2'd1;
rx_buffer_valid_counter <= 2'd1; rx_buffer_valid_counter <= 2'd1;
end else begin end else begin
mem_bus.wmask <= 2'b11; rx_wmask <= 2'b11;
rx_buffer_counter <= 2'd0; rx_buffer_counter <= 2'd0;
rx_buffer_valid_counter <= 2'd0; rx_buffer_valid_counter <= 2'd0;
end end
@ -106,16 +107,21 @@ module memory_dma (
end end
if (rx_rdata_shift || rx_rdata_valid) begin if (rx_rdata_shift || rx_rdata_valid) begin
rx_buffer <= {rx_buffer[7:0], fifo_bus.rx_rdata}; if (dma_scb.byte_swap) begin
rx_buffer <= {fifo_bus.rx_rdata, rx_buffer[15:8]};
end else begin
rx_buffer <= {rx_buffer[7:0], fifo_bus.rx_rdata};
end
rx_buffer_valid_counter <= rx_buffer_valid_counter + 1'd1; rx_buffer_valid_counter <= rx_buffer_valid_counter + 1'd1;
if (remaining == 27'd0 && rx_buffer_counter == 2'd1) begin if (remaining == 27'd0 && rx_buffer_counter == 2'd1) begin
mem_bus.wmask <= 2'b10; rx_wmask <= 2'b10;
rx_rdata_shift <= 1'b1; rx_rdata_shift <= 1'b1;
rx_buffer_counter <= rx_buffer_counter + 1'd1; rx_buffer_counter <= rx_buffer_counter + 1'd1;
end end
end end
if (rx_buffer_valid && !mem_bus.request) begin if (rx_buffer_valid && !mem_bus.request) begin
rx_wmask <= 2'b11;
rx_buffer_counter <= 2'd0; rx_buffer_counter <= 2'd0;
rx_buffer_valid_counter <= 2'd0; rx_buffer_valid_counter <= 2'd0;
end end
@ -212,11 +218,8 @@ module memory_dma (
if (mem_bus.write) begin if (mem_bus.write) begin
if (rx_buffer_valid) begin if (rx_buffer_valid) begin
mem_bus.request <= 1'b1; mem_bus.request <= 1'b1;
if (dma_scb.byte_swap) begin mem_bus.wmask <= rx_wmask;
mem_bus.wdata <= {rx_buffer[7:0], rx_buffer[15:8]}; mem_bus.wdata <= rx_buffer;
end else begin
mem_bus.wdata <= rx_buffer;
end
end end
end else begin end else begin
if (tx_buffer_ready) begin if (tx_buffer_ready) begin