mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-23 22:29:15 +01:00
small cleanup in usb.c
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parent
2bb47720e2
commit
ab5b02251f
@ -174,9 +174,9 @@ static void usb_flush_packet (void) {
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p.packet_pending = false;
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p.packet_pending = false;
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p.packet_info.done_callback();
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p.packet_info.done_callback();
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}
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}
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if (p.tx_state != TX_STATE_IDLE && p.tx_info.done_callback) {
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if (p.tx_state != TX_STATE_IDLE && p.tx_info.done_callback) {
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p.tx_info.done_callback();
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p.tx_info.done_callback();
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p.tx_info.done_callback = NULL;
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}
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}
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}
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}
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@ -461,27 +461,34 @@ static void usb_rx_process (void) {
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}
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}
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if (p.rx_state == RX_STATE_FLUSH) {
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if (p.rx_state == RX_STATE_FLUSH) {
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if (usb_dma_ready()) {
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if (p.rx_args[1] > 0) {
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if (p.rx_args[1] != 0) {
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if (usb_dma_ready()) {
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uint32_t length = (p.rx_args[1] > RX_FLUSH_LENGTH) ? RX_FLUSH_LENGTH : p.rx_args[1];
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uint32_t length = (p.rx_args[1] > RX_FLUSH_LENGTH) ? RX_FLUSH_LENGTH : p.rx_args[1];
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fpga_reg_set(REG_USB_DMA_ADDRESS, RX_FLUSH_ADDRESS);
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if (!p.rx_dma_running) {
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fpga_reg_set(REG_USB_DMA_LENGTH, length);
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fpga_reg_set(REG_USB_DMA_ADDRESS, RX_FLUSH_ADDRESS);
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fpga_reg_set(REG_USB_DMA_SCR, DMA_SCR_DIRECTION | DMA_SCR_START);
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fpga_reg_set(REG_USB_DMA_LENGTH, length);
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p.rx_args[1] -= length;
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fpga_reg_set(REG_USB_DMA_SCR, DMA_SCR_DIRECTION | DMA_SCR_START);
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} else {
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p.rx_dma_running = true;
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if (p.flush_response) {
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p.rx_state = RX_STATE_IDLE;
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p.response_pending = true;
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p.response_error = true;
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} else if (p.flush_packet) {
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usb_tx_info_t packet_info;
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usb_create_packet(&packet_info, PACKET_CMD_DATA_FLUSHED);
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if (usb_enqueue_packet(&packet_info)) {
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p.rx_state = RX_STATE_IDLE;
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}
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} else {
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} else {
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p.rx_args[1] -= length;
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p.rx_dma_running = false;
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}
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}
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}
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if (p.rx_args[1] == 0) {
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if (p.flush_response) {
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p.rx_state = RX_STATE_IDLE;
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p.response_pending = true;
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p.response_error = true;
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} else if (p.flush_packet) {
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usb_tx_info_t packet_info;
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usb_create_packet(&packet_info, PACKET_CMD_DATA_FLUSHED);
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if (usb_enqueue_packet(&packet_info)) {
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p.rx_state = RX_STATE_IDLE;
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p.rx_state = RX_STATE_IDLE;
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}
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}
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} else {
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p.rx_state = RX_STATE_IDLE;
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}
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}
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}
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}
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}
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}
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