diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 4da4db4..320601b 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -20,8 +20,18 @@ jobs:
- uses: actions/checkout@v2
with:
submodules: true
+
+ - name: Prepare Lattice Diamond license
+ env:
+ ENCODED_LICENSE: ${{ secrets.LATTICE_DIAMOND_LICENSE }}
+ run: |
+ mkdir -p ./flexlm
+ echo "$ENCODED_LICENSE" > ./flexlm/encoded_license
+ base64 -d ./flexlm/encoded_license > ./flexlm/license.dat
- name: Build script
+ env:
+ MAC_ADDRESS: ${{ secrets.LATTICE_DIAMOND_MAC }}
run: ./docker_build.sh release --force-clean
- name: Upload artifact
diff --git a/.gitignore b/.gitignore
index ca0d302..2aba42e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,8 @@
**/.DS_Store
-**/.vscode/settings.json
+**/.vscode/
**/*.bak
**/*.zip
+/flexlm
+
+!**/.vscode/launch.json
+!**/.vscode/tasks.json
diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index e1371e8..0000000
--- a/.gitmodules
+++ /dev/null
@@ -1,8 +0,0 @@
-[submodule "fw/picorv32"]
- path = fw/picorv32
- url = https://github.com/cliffordwolf/picorv32.git
- ignore = dirty
-[submodule "sw/cic"]
- path = sw/cic
- url = https://github.com/ManCloud/UltraCIC-III.git
- ignore = dirty
diff --git a/.vscode/launch.json b/.vscode/launch.json
index 8160f17..d1b2dfb 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -2,11 +2,58 @@
"version": "0.2.0",
"configurations": [
{
- "name": "Build SW and Update",
+ "cwd": "${workspaceRoot}/sw/controller",
+ "executable": "./build/controller.elf",
+ "name": "Load ARM",
+ "request": "launch",
+ "type": "cortex-debug",
+ "servertype": "stlink",
+ // "serverpath": "C:\\msys64\\mingw64\\bin\\openocd.exe",
+ "preLaunchTask": "build_controller",
+ "device": "STM32G030F6",
+ "svdFile": "./STM32G030.svd",
+ // "configFiles": ["interface/stlink.cfg", "target/stm32g0x.cfg"],
+ // "runToMain": true
+ "postRestartCommands": [
+ // "b Reset_Handler"
+ // "monitor reset halt",
+ // "load",
+ // "b main",
+ // "monitor reset",
+ ]
+ },
+ {
+ "name": "Run ROM",
"type": "python",
"request": "launch",
"program": "sw/pc/sc64.py",
- "preLaunchTask": "build",
+ // "preLaunchTask": "build",
+ "justMyCode": false,
+ "args": [
+ // "-u", "fw/output_files/SC64_update.bin",
+ // "-rtc",
+ // "-f", "\\\\.\\D:",
+ // "-d", "-df",
+ // "-i", "S:/n64/64dd/ipl/NDXJ0.n64",
+ // "-k", "S:/n64/64dd/dev/EZLJ_Expansion_DEV_v1.1.ndd",
+ // "-t", "1",
+ // "-b", "2",
+ // "-s", "1",
+ // "-q",
+ // "-v",
+ // "-e", "S:/n64/saves/majora_snowhead.fla",
+ // "S:/n64/roms/Legend of Zelda, The - Ocarina of Time (USA) (Rev B).z64",
+ // "S:/n64/roms/ZELOOTD.z64",
+ "S:/n64/roms/switchtome.z64",
+ // "D:/sc64menu.n64",
+ ],
+ },
+ {
+ "name": "Build SW and Update",
+ "type": "python",
+ "request": "launch",
+ "program": "sw/pc/v2.py",
+ // "preLaunchTask": "build",
"args": [
"-u", "fw/output_files/SC64_update.bin",
]
diff --git a/.vscode/tasks.json b/.vscode/tasks.json
index 3306bae..6a40325 100644
--- a/.vscode/tasks.json
+++ b/.vscode/tasks.json
@@ -2,15 +2,54 @@
"version": "2.0.0",
"tasks": [
{
- "label": "build",
+ "label": "build_bootloader",
"type": "shell",
- "command": "./docker_build.sh update -s -c -d",
+ "command": "./docker_build.sh bootloader",
"presentation": {
"showReuseMessage": false,
"clear": true
},
- "windows":{
- "command": "wsl -- ./docker_build.sh update -s -c -d"
+ "windows": {
+ "command": "wsl -- ./docker_build.sh bootloader"
+ },
+ "group": "build"
+ },
+ {
+ "label": "build_controller",
+ "type": "shell",
+ "command": "./docker_build.sh controller",
+ "presentation": {
+ "showReuseMessage": false,
+ "clear": true
+ },
+ "windows": {
+ "command": "wsl -- ./docker_build.sh controller"
+ },
+ "group": "build"
+ },
+ {
+ "label": "build_fpga",
+ "type": "shell",
+ "command": "./docker_build.sh fpga",
+ "presentation": {
+ "showReuseMessage": false,
+ "clear": true
+ },
+ "windows": {
+ "command": "wsl -- ./docker_build.sh fpga"
+ },
+ "group": "build"
+ },
+ {
+ "label": "build_update",
+ "type": "shell",
+ "command": "./docker_build.sh update",
+ "presentation": {
+ "showReuseMessage": false,
+ "clear": true
+ },
+ "windows": {
+ "command": "wsl -- ./docker_build.sh update"
},
"group": {
"kind": "build",
@@ -18,30 +57,17 @@
}
},
{
- "label": "build_full",
+ "label": "build_release",
"type": "shell",
- "command": "./docker_build.sh release -c -d",
+ "command": "./docker_build.sh release --force-clean",
"presentation": {
"showReuseMessage": false,
"clear": true
},
- "windows": {
- "command": "wsl -- ./docker_build.sh update -c -d"
+ "windows":{
+ "command": "wsl -- ./docker_build.sh release --force-clean"
},
"group": "build"
},
- {
- "label": "build_n64",
- "type": "shell",
- "command": "./docker_build.sh n64 -d",
- "presentation": {
- "showReuseMessage": false,
- "clear": true
- },
- "windows": {
- "command": "wsl -- ./docker_build.sh n64 -d"
- },
- "group": "build"
- }
]
}
\ No newline at end of file
diff --git a/assets/sc64_logo.blend b/assets/sc64_logo.blend
new file mode 100644
index 0000000..ecde59d
Binary files /dev/null and b/assets/sc64_logo.blend differ
diff --git a/build.sh b/build.sh
index 5ef217b..bc13443 100755
--- a/build.sh
+++ b/build.sh
@@ -2,99 +2,67 @@
set -e
-PACKAGE_FILE_NAME="SummerCart64"
+PACKAGE_FILE_NAME="SC64"
FILES=(
- "./fw/output_files/SC64_firmware.pof"
- "./fw/output_files/SC64_update.bin"
+ "./fw/project/lcmxo2/impl1/sc64_impl1.bit"
+ "./fw/project/lcmxo2/impl1/sc64_impl1.jed"
"./hw/ftdi-template.xml"
- "./sw/cic/UltraCIC-III.hex"
+ "./sw/bootloader/build/bootloader.bin"
+ "./sw/controller/build/controller.bin"
+ "./sw/controller/build/controller.elf"
+ "./sw/pc/helpers.py"
+ "./sw/pc/sc64.py"
"./LICENSE"
+ "./README.md"
)
-BUILT_CIC=false
-BUILT_N64=false
-BUILT_RISCV=false
-BUILT_SW=false
+BUILT_BOOTLOADER=false
+BUILT_CONTROLLER=false
BUILT_FPGA=false
BUILT_UPDATE=false
BUILT_RELEASE=false
FORCE_CLEAN=false
-SKIP_FPGA_REBUILD=false
-DEBUG_ENABLED=false
-build_cic () {
- if [ "$BUILT_CIC" = true ]; then return; fi
+build_bootloader () {
+ if [ "$BUILT_BOOTLOADER" = true ]; then return; fi
- pushd sw/cic > /dev/null
- avra UltraCIC-III.asm -D attiny45
- popd > /dev/null
-
- BUILT_CIC=true
-}
-
-build_n64 () {
- if [ "$BUILT_N64" = true ]; then return; fi
-
- pushd sw/n64 > /dev/null
+ pushd sw/bootloader > /dev/null
if [ "$FORCE_CLEAN" = true ]; then
make clean
fi
- N64_FLAGS="$USER_FLAGS"
- if [ ! -z "${GIT_BRANCH+x}" ]; then N64_FLAGS+=" -DGIT_BRANCH='\"$GIT_BRANCH\"'"; fi
- if [ ! -z "${GIT_TAG+x}" ]; then N64_FLAGS+=" -DGIT_TAG='\"$GIT_TAG\"'"; fi
- if [ ! -z "${GIT_SHA+x}" ]; then N64_FLAGS+=" -DGIT_SHA='\"$GIT_SHA\"'"; fi
- make all -j USER_FLAGS="$N64_FLAGS"
+ FLAGS="$USER_FLAGS"
+ if [ ! -z "${GIT_BRANCH+x}" ]; then FLAGS+=" -DGIT_BRANCH='\"$GIT_BRANCH\"'"; fi
+ if [ ! -z "${GIT_TAG+x}" ]; then FLAGS+=" -DGIT_TAG='\"$GIT_TAG\"'"; fi
+ if [ ! -z "${GIT_SHA+x}" ]; then FLAGS+=" -DGIT_SHA='\"$GIT_SHA\"'"; fi
+ make all -j USER_FLAGS="$FLAGS"
popd > /dev/null
- BUILT_N64=true
+ BUILT_BOOTLOADER=true
}
-build_riscv () {
- if [ "$BUILT_RISCV" = true ]; then return; fi
+build_controller () {
+ if [ "$BUILT_CONTROLLER" = true ]; then return; fi
- pushd sw/riscv > /dev/null
+ pushd sw/controller > /dev/null
if [ "$FORCE_CLEAN" = true ]; then
make clean
fi
make all -j USER_FLAGS="$USER_FLAGS"
popd > /dev/null
- BUILT_RISCV=true
-}
-
-build_sw () {
- if [ "$BUILT_SW" = true ]; then return; fi
-
- build_n64
- build_riscv
-
- pushd fw > /dev/null
- mkdir -p output_files > /dev/null
- cat ../sw/n64/build/n64boot.bin ../sw/riscv/build/governor.bin > output_files/SC64_software.bin
- objcopy -I binary -O ihex output_files/SC64_software.bin output_files/SC64_software.hex
- popd
-
- BUILT_SW=true
+ BUILT_CONTROLLER=true
}
build_fpga () {
if [ "$BUILT_FPGA" = true ]; then return; fi
- build_sw
-
- pushd fw > /dev/null
- if [ "$SKIP_FPGA_REBUILD" = true ] && [ -f output_files/SummerCart64.sof ]; then
- quartus_cpf -c SummerCart64.cof
- else
- if [ "$DEBUG_ENABLED" = true ]; then
- quartus_sh --set VERILOG_MACRO="DEBUG" ./SummerCart64.qpf
- else
- quartus_sh --set -remove VERILOG_MACRO="DEBUG" ./SummerCart64.qpf
- fi
- quartus_sh --flow compile ./SummerCart64.qpf
+ pushd fw/project/lcmxo2 > /dev/null
+ if [ "$FORCE_CLEAN" = true ]; then
+ rm -rf ./impl1/
fi
+ ./build.sh
popd > /dev/null
BUILT_FPGA=true
@@ -103,20 +71,16 @@ build_fpga () {
build_update () {
if [ "$BUILT_UPDATE" = true ]; then return; fi
+ build_bootloader
+ build_controller
build_fpga
- pushd fw/output_files > /dev/null
- objcopy -I binary -O binary --reverse-bytes=4 sc64_firmware_cfm0_auto.rpd SC64_firmware.bin
- cat SC64_software.bin SC64_firmware.bin > SC64_update.bin
- popd > /dev/null
-
BUILT_UPDATE=true
}
build_release () {
if [ "$BUILT_RELEASE" = true ]; then return; fi
- build_cic
build_update
if [ -e "./${PACKAGE_FILE_NAME}.zip" ]; then
@@ -129,22 +93,16 @@ build_release () {
print_usage () {
echo "builder script for SummerCart64"
- echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [-c] [-s] [-d] [--help]"
+ echo "usage: ./build.sh [bootloader] [controller] [fpga] [update] [release] [-c] [--help]"
echo "parameters:"
- echo " cic - assemble UltraCIC-III software"
- echo " n64 - compile N64 bootloader software"
- echo " riscv - compile cart governor software"
- echo " sw - compile all software (triggers 'n64' and 'riscv' build)"
- echo " fpga - compile FPGA design (triggers 'sw' build)"
- echo " update - convert programming .pof file to raw binary for self-upgrade (triggers 'fpga' build)"
- echo " release - collect and zip files for release (triggers 'cic' and 'update' build)"
+ echo " bootloader - compile N64 bootloader software"
+ echo " controller - compile ARM controller software"
+ echo " fpga - compile FPGA design"
+ echo " update - compile all software and designs"
+ echo " release - collect and zip files for release (triggers 'update' build)"
echo " -c | --force-clean"
- echo " - clean software compilation result directories before build"
- echo " -s | --skip-fpga-rebuild"
- echo " - do not recompile whole FPGA design if it's already done, just update software binaries"
- echo " -d | --debug"
- echo " - enable debug features"
- echo " --help - print this guide"
+ echo " - clean compilation result directories before build"
+ echo " --help - print this guide"
}
if test $# -eq 0; then
@@ -154,27 +112,19 @@ if test $# -eq 0; then
exit 1
fi
-TRIGGER_CIC=false
-TRIGGER_N64=false
-TRIGGER_RISCV=false
-TRIGGER_SW=false
+TRIGGER_BOOTLOADER=false
+TRIGGER_CONTROLLER=false
TRIGGER_FPGA=false
TRIGGER_UPDATE=false
TRIGGER_RELEASE=false
while test $# -gt 0; do
case "$1" in
- cic)
- TRIGGER_CIC=true
+ bootloader)
+ TRIGGER_BOOTLOADER=true
;;
- n64)
- TRIGGER_N64=true
- ;;
- riscv)
- TRIGGER_RISCV=true
- ;;
- sw)
- TRIGGER_SW=true
+ controller)
+ TRIGGER_CONTROLLER=true
;;
fpga)
TRIGGER_FPGA=true
@@ -188,12 +138,6 @@ while test $# -gt 0; do
-c|--force-clean)
FORCE_CLEAN=true
;;
- -s|--skip-fpga-rebuild)
- SKIP_FPGA_REBUILD=true
- ;;
- -d|--debug)
- DEBUG_ENABLED=true
- ;;
--help)
print_usage
exit 0
@@ -208,11 +152,8 @@ while test $# -gt 0; do
shift
done
-if [ "$DEBUG_ENABLED" = true ]; then USER_FLAGS+=" -DDEBUG"; fi
-if [ "$TRIGGER_CIC" = true ]; then build_cic; fi
-if [ "$TRIGGER_N64" = true ]; then build_n64; fi
-if [ "$TRIGGER_RISCV" = true ]; then build_riscv; fi
-if [ "$TRIGGER_SW" = true ]; then build_sw; fi
+if [ "$TRIGGER_BOOTLOADER" = true ]; then build_bootloader; fi
+if [ "$TRIGGER_CONTROLLER" = true ]; then build_controller; fi
if [ "$TRIGGER_FPGA" = true ]; then build_fpga; fi
if [ "$TRIGGER_UPDATE" = true ]; then build_update; fi
if [ "$TRIGGER_RELEASE" = true ]; then build_release; fi
diff --git a/hw/ftdi-template.xml b/cfg/ftdi_template.xml
similarity index 55%
rename from hw/ftdi-template.xml
rename to cfg/ftdi_template.xml
index 50922cc..664dde4 100644
Binary files a/hw/ftdi-template.xml and b/cfg/ftdi_template.xml differ
diff --git a/docker_build.sh b/docker_build.sh
index 33e5dcb..68f6dcf 100755
--- a/docker_build.sh
+++ b/docker_build.sh
@@ -1,17 +1,8 @@
#!/bin/bash
-CONTAINER_NAME="sc64builder"
+BUILDER_IMAGE="ghcr.io/polprzewodnikowy/sc64env:v1.4"
-docker ps | grep $CONTAINER_NAME > /dev/null
-
-if [ $? -eq 1 ]; then
- docker run \
- -dt --rm \
- --name $CONTAINER_NAME \
- --user $(id -u):$(id -g) \
- --mount type=bind,src="$(pwd)",target="/workdir" \
- ghcr.io/polprzewodnikowy/sc64env:v1.2
-fi
+pushd $(dirname $0) > /dev/null
GIT_BRANCH=$(git rev-parse --abbrev-ref HEAD)
GIT_TAG=$(git describe --tags 2> /dev/null)
@@ -21,10 +12,18 @@ if [ -t 1 ]; then
DOCKER_OPTIONS="-it"
fi
-docker exec \
+docker run \
$DOCKER_OPTIONS \
+ --rm \
+ --privileged \
+ --user $(id -u):$(id -g) \
+ --mac-address ${MAC_ADDRESS:-F8:12:34:56:78:90} \
+ --mount type=bind,src="$(pwd)/flexlm",target="/flexlm" \
+ --mount type=bind,src="$(pwd)",target="/workdir" \
-e GIT_BRANCH="$GIT_BRANCH" \
-e GIT_TAG="$GIT_TAG" \
-e GIT_SHA="$GIT_SHA" \
- $CONTAINER_NAME \
+ $BUILDER_IMAGE \
./build.sh $@
+
+popd > /dev/null
diff --git a/fw/.gitignore b/fw/.gitignore
deleted file mode 100644
index e8bfb66..0000000
--- a/fw/.gitignore
+++ /dev/null
@@ -1,13 +0,0 @@
-/db
-/greybox_tmp
-/incremental_db
-/output_files
-**/.qsys_edit
-**/*.bin
-**/*.dat
-**/*.elf
-*.qws
-*.rpt
-*.sopcinfo
-*.srf
-*.txt
diff --git a/fw/SummerCart64.cof b/fw/SummerCart64.cof
deleted file mode 100644
index d10644c..0000000
--- a/fw/SummerCart64.cof
+++ /dev/null
@@ -1,40 +0,0 @@
-
-
- output_files/SC64_firmware.pof
- 1
- 1
- 14
-
- Page_0
- 1
-
- output_files/SummerCart64.sof1
-
-
- 10
- 0
- 0
- 1
- 0
-
- 1
-
-
- 0
- 1
- 0
- 0
- 0
- 0
- 2
- output_files/SC64_software.hex
-
-
- 1
- 2
- 0
- -1
- -1
- 1
-
-
\ No newline at end of file
diff --git a/fw/SummerCart64.qpf b/fw/SummerCart64.qpf
deleted file mode 100644
index b58ed21..0000000
--- a/fw/SummerCart64.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:53:32 August 01, 2021
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "10:53:32 August 01, 2021"
-
-# Revisions
-
-PROJECT_REVISION = "SummerCart64"
diff --git a/fw/SummerCart64.qsf b/fw/SummerCart64.qsf
deleted file mode 100644
index d137f48..0000000
--- a/fw/SummerCart64.qsf
+++ /dev/null
@@ -1,293 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2021 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 19:19:14 February 04, 2022
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# SummerCart64_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Intel recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:53:32 AUGUST 01, 2021"
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
-set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/post_module.tcl"
-set_global_assignment -name QSYS_FILE rtl/vendor/intel/generated/intel_flash.qsys
-set_global_assignment -name QIP_FILE rtl/intel/fifo/intel_fifo_8.qip
-set_global_assignment -name QIP_FILE rtl/vendor/intel/generated/intel_gpio_ddro.qip
-set_global_assignment -name QIP_FILE rtl/vendor/intel/generated/intel_pll.qip
-set_global_assignment -name SDC_FILE SummerCart64.sdc
-set_global_assignment -name SYSTEMVERILOG_FILE picorv32/picorv32.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_cfg.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_dd.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_flash.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_flashram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_i2c.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_ram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_sdram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_si.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_soc.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_uart.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_usb.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_wrapper.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/memory_dma.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/memory_sdram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_bootloader.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_bus.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_cfg.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_dd.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_flashram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_pi.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_pi_fifo.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_sdram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_si.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_soc.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/SummerCart64.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/config.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/vendor/intel/vendor_flash.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/vendor/intel/vendor_reconfigure.sv
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_6 -to o_usb_cs
-set_location_assignment PIN_7 -to i_usb_miso
-set_location_assignment PIN_8 -to o_usb_clk
-set_location_assignment PIN_12 -to i_uart_rxd
-set_location_assignment PIN_13 -to o_uart_txd
-set_location_assignment PIN_17 -to o_led
-set_location_assignment PIN_21 -to o_rtc_scl
-set_location_assignment PIN_22 -to io_rtc_sda
-set_location_assignment PIN_24 -to io_n64_si_dq
-set_location_assignment PIN_25 -to i_n64_nmi
-set_location_assignment PIN_26 -to i_clk
-set_location_assignment PIN_27 -to i_n64_reset
-set_location_assignment PIN_28 -to i_n64_si_clk
-set_location_assignment PIN_32 -to io_n64_pi_ad[7]
-set_location_assignment PIN_33 -to io_n64_pi_ad[8]
-set_location_assignment PIN_38 -to io_n64_pi_ad[6]
-set_location_assignment PIN_39 -to io_n64_pi_ad[9]
-set_location_assignment PIN_41 -to io_n64_pi_ad[5]
-set_location_assignment PIN_43 -to io_n64_pi_ad[10]
-set_location_assignment PIN_44 -to io_n64_pi_ad[4]
-set_location_assignment PIN_45 -to io_n64_pi_ad[11]
-set_location_assignment PIN_46 -to i_n64_pi_aleh
-set_location_assignment PIN_47 -to i_n64_pi_read
-set_location_assignment PIN_48 -to i_n64_pi_write
-set_location_assignment PIN_50 -to i_n64_pi_alel
-set_location_assignment PIN_52 -to io_n64_pi_ad[12]
-set_location_assignment PIN_54 -to io_n64_pi_ad[3]
-set_location_assignment PIN_55 -to io_n64_pi_ad[13]
-set_location_assignment PIN_56 -to io_n64_pi_ad[2]
-set_location_assignment PIN_57 -to io_n64_pi_ad[14]
-set_location_assignment PIN_58 -to io_n64_pi_ad[1]
-set_location_assignment PIN_59 -to io_n64_pi_ad[15]
-set_location_assignment PIN_60 -to io_n64_pi_ad[0]
-set_location_assignment PIN_61 -to o_sdram_a[4]
-set_location_assignment PIN_62 -to o_sdram_a[5]
-set_location_assignment PIN_64 -to o_sdram_a[6]
-set_location_assignment PIN_65 -to o_sdram_a[7]
-set_location_assignment PIN_66 -to o_sdram_a[8]
-set_location_assignment PIN_69 -to o_sdram_a[9]
-set_location_assignment PIN_70 -to o_sdram_a[11]
-set_location_assignment PIN_74 -to o_sdram_a[12]
-set_location_assignment PIN_75 -to o_sdram_clk
-set_location_assignment PIN_76 -to o_sdram_a[3]
-set_location_assignment PIN_77 -to o_sdram_a[2]
-set_location_assignment PIN_78 -to o_sdram_a[1]
-set_location_assignment PIN_79 -to o_sdram_a[0]
-set_location_assignment PIN_80 -to o_sdram_a[10]
-set_location_assignment PIN_81 -to o_sdram_ba[1]
-set_location_assignment PIN_84 -to o_sdram_ba[0]
-set_location_assignment PIN_85 -to o_sdram_cs
-set_location_assignment PIN_86 -to o_sdram_ras
-set_location_assignment PIN_87 -to o_sdram_cas
-set_location_assignment PIN_88 -to o_sdram_we
-set_location_assignment PIN_89 -to io_sdram_dq[7]
-set_location_assignment PIN_90 -to io_sdram_dq[6]
-set_location_assignment PIN_91 -to io_sdram_dq[5]
-set_location_assignment PIN_92 -to io_sdram_dq[4]
-set_location_assignment PIN_93 -to io_sdram_dq[3]
-set_location_assignment PIN_96 -to io_sdram_dq[2]
-set_location_assignment PIN_97 -to io_sdram_dq[1]
-set_location_assignment PIN_98 -to io_sdram_dq[0]
-set_location_assignment PIN_99 -to io_sdram_dq[8]
-set_location_assignment PIN_100 -to io_sdram_dq[9]
-set_location_assignment PIN_101 -to io_sdram_dq[10]
-set_location_assignment PIN_102 -to io_sdram_dq[11]
-set_location_assignment PIN_105 -to io_sdram_dq[12]
-set_location_assignment PIN_106 -to io_sdram_dq[13]
-set_location_assignment PIN_110 -to io_sdram_dq[14]
-set_location_assignment PIN_111 -to io_sdram_dq[15]
-set_location_assignment PIN_112 -to io_sd_dat[1]
-set_location_assignment PIN_113 -to io_sd_dat[0]
-set_location_assignment PIN_114 -to o_sd_clk
-set_location_assignment PIN_118 -to io_sd_cmd
-set_location_assignment PIN_119 -to io_sd_dat[3]
-set_location_assignment PIN_120 -to io_sd_dat[2]
-set_location_assignment PIN_123 -to o_n64_irq
-set_location_assignment PIN_124 -to io_usb_miosi[7]
-set_location_assignment PIN_127 -to io_usb_miosi[6]
-set_location_assignment PIN_130 -to io_usb_miosi[4]
-set_location_assignment PIN_131 -to io_usb_miosi[5]
-set_location_assignment PIN_134 -to io_usb_miosi[3]
-set_location_assignment PIN_135 -to io_usb_miosi[2]
-set_location_assignment PIN_140 -to io_usb_miosi[1]
-set_location_assignment PIN_141 -to io_usb_miosi[0]
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
-
-# Compiler Assignments
-# ====================
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "MAX 10"
-set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name TOP_LEVEL_ENTITY SummerCart64
-set_global_assignment -name VERILOG_MACRO DEBUG
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE 10M08SCE144C8G
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name ENABLE_OCT_DONE OFF
-set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# --------------------------
-# start ENTITY(SummerCart64)
-
- # Pin & Location Assignments
- # ==========================
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_nmi
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_aleh
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_alel
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_read
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_write
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_reset
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_si_clk
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_uart_rxd
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_usb_miso
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_n64_pi_ad[*]
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_rtc_sda
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_sdram_dq[*]
- set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[*]
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_n64_pi_ad[*]
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_rtc_sda
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_sdram_dq[*]
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[*]
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_rtc_scl
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_sdram_a[*]
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_sdram_ba[*]
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_sdram_cas
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_sdram_cs
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_sdram_ras
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_sdram_we
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_uart_txd
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_clk
- set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_cs
- set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_n64_pi_ad[*]
- set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_sdram_dq[*]
- set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[*]
-
- # Fitter Assignments
- # ==================
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_nmi
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_uart_rxd
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_aleh
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_read
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_write
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_alel
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_n64_irq
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_usb_miso
-
- # start DESIGN_PARTITION(Top)
- # ---------------------------
-
- # Incremental Compilation Assignments
- # ===================================
- set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
- set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
- set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
- # end DESIGN_PARTITION(Top)
- # -------------------------
-
-# end ENTITY(SummerCart64)
-# ------------------------
\ No newline at end of file
diff --git a/fw/SummerCart64.sdc b/fw/SummerCart64.sdc
deleted file mode 100644
index c8db83c..0000000
--- a/fw/SummerCart64.sdc
+++ /dev/null
@@ -1,91 +0,0 @@
-# Clocks
-
-derive_pll_clocks -create_base_clocks
-
-set sys_clk {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[0]}
-set sdram_pll_clk {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[1]}
-# set sd_reg_clk {sd_interface_inst|sd_clk_inst|o_sd_clk|q}
-
-create_generated_clock -name sdram_clk -source [get_pins $sdram_pll_clk] [get_ports {o_sdram_clk}]
-create_clock -name usb_clk -period 40.0 [get_ports {o_usb_clk}]
-# create_generated_clock -name sd_reg_clk -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] -divide_by 2 [get_pins $sd_reg_clk]
-# create_generated_clock -name sd_clk -source [get_pins $sd_reg_clk] [get_ports {o_sd_clk}]
-create_generated_clock -name flash_se_neg_reg \
- -source [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk}] \
- -divide_by 2 \
- [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q}]
-
-derive_clock_uncertainty
-
-
-# SDRAM timings
-
-set sdram_outputs {o_sdram_cs o_sdram_ras o_sdram_cas o_sdram_we o_sdram_a[*] o_sdram_ba[*] io_sdram_dq[*]}
-set sdram_inputs {io_sdram_dq[*]}
-
-set_output_delay -clock [get_clocks {sdram_clk}] -max 1.5 [get_ports $sdram_outputs]
-set_output_delay -clock [get_clocks {sdram_clk}] -min -0.8 [get_ports $sdram_outputs]
-
-set_input_delay -clock [get_clocks {sdram_clk}] -max 5.4 [get_ports $sdram_inputs]
-set_input_delay -clock [get_clocks {sdram_clk}] -min 2.5 [get_ports $sdram_inputs]
-
-set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks $sys_clk]
-set_multicycle_path -hold -end 1 -from [get_clocks {sdram_clk}] -to [get_clocks $sys_clk]
-
-
-# SD card timings
-
-# set_output_delay -clock [get_clocks {sd_clk}] -max 6.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
-# set_output_delay -clock [get_clocks {sd_clk}] -min -2.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
-
-# set_input_delay -clock [get_clocks {sd_clk}] -max 15.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
-# set_input_delay -clock [get_clocks {sd_clk}] -min 6.5 [get_ports {io_sd_cmd io_sd_dat[*]}]
-
-# set_multicycle_path -hold -start 1 -from [get_clocks $sys_clk] -to [get_clocks {sd_clk}]
-
-# set_multicycle_path -setup -end 3 -from [get_clocks {sd_clk}] -to [get_clocks $sys_clk]
-# set_multicycle_path -hold -end 1 -from [get_clocks {sd_clk}] -to [get_clocks $sys_clk]
-
-
-# FT1248 timings
-
-set_output_delay -clock [get_clocks {usb_clk}] -max 2.0 [get_ports {io_usb_miosi[*] o_usb_cs}]
-set_output_delay -clock [get_clocks {usb_clk}] -min -1.0 [get_ports {io_usb_miosi[*] o_usb_cs}]
-
-set_input_delay -clock [get_clocks {usb_clk}] -max 5.0 [get_ports {io_usb_miosi[*] i_usb_miso}]
-set_input_delay -clock [get_clocks {usb_clk}] -min 2.5 [get_ports {io_usb_miosi[*] i_usb_miso}]
-
-set_multicycle_path -setup -start 2 -from [get_clocks $sys_clk] -to [get_clocks {usb_clk}]
-set_multicycle_path -hold -start 3 -from [get_clocks $sys_clk] -to [get_clocks {usb_clk}]
-
-set_multicycle_path -setup -end 2 -from [get_clocks {usb_clk}] -to [get_clocks $sys_clk]
-set_multicycle_path -hold -end 3 -from [get_clocks {usb_clk}] -to [get_clocks $sys_clk]
-
-
-# N64, PI and SI timings
-
-set_false_path -to [get_ports {o_n64_irq}]
-set_false_path -from [get_ports {i_n64_reset i_n64_nmi}]
-
-set_false_path -to [get_ports {io_n64_pi_ad[*]}]
-set_false_path -from [get_ports {i_n64_pi_* io_n64_pi_ad[*]}]
-
-set_false_path -to [get_ports {io_n64_si_dq}]
-set_false_path -from [get_ports {i_n64_si_clk io_n64_si_dq}]
-
-
-# LED timings
-
-set_false_path -to [get_ports {o_led}]
-
-
-# UART timings
-
-set_false_path -to [get_ports {o_uart_txd}]
-set_false_path -from [get_ports {i_uart_rxd}]
-
-
-# I2C timings
-
-set_false_path -to [get_ports {o_rtc_scl io_rtc_sda}]
-set_false_path -from [get_ports {io_rtc_sda}]
diff --git a/fw/picorv32 b/fw/picorv32
deleted file mode 160000
index f00a88c..0000000
--- a/fw/picorv32
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit f00a88c36eaab478b64ee27d8162e421049bcc66
diff --git a/fw/project/lcmxo2/.gitignore b/fw/project/lcmxo2/.gitignore
new file mode 100644
index 0000000..9eb10ae
--- /dev/null
+++ b/fw/project/lcmxo2/.gitignore
@@ -0,0 +1,15 @@
+.recovery
+*.dir/
+*.html
+*.ini
+*.rva
+*.rvl
+*.rvs
+*.svf
+*.tcl
+*.tpf
+*.trc
+*.xml
+impl*/
+
+!build.tcl
diff --git a/fw/project/lcmxo2/build.sh b/fw/project/lcmxo2/build.sh
new file mode 100644
index 0000000..35a8b44
--- /dev/null
+++ b/fw/project/lcmxo2/build.sh
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+source $bindir/diamond_env
+
+diamondc build.tcl
diff --git a/fw/project/lcmxo2/build.tcl b/fw/project/lcmxo2/build.tcl
new file mode 100644
index 0000000..328fe4e
--- /dev/null
+++ b/fw/project/lcmxo2/build.tcl
@@ -0,0 +1,3 @@
+prj_project open sc64.ldf
+prj_run Export -impl impl1 -task Bitgen
+prj_run Export -impl impl1 -task Jedecgen
diff --git a/fw/project/lcmxo2/sc64.ldf b/fw/project/lcmxo2/sc64.ldf
new file mode 100644
index 0000000..147bffc
--- /dev/null
+++ b/fw/project/lcmxo2/sc64.ldf
@@ -0,0 +1,104 @@
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diff --git a/fw/project/lcmxo2/sc64.lpf b/fw/project/lcmxo2/sc64.lpf
new file mode 100644
index 0000000..32501c3
--- /dev/null
+++ b/fw/project/lcmxo2/sc64.lpf
@@ -0,0 +1,204 @@
+rvl_alias "clk" "clk";
+BANK 0 VCCIO 3.3 V;
+BANK 1 VCCIO 3.3 V;
+BANK 2 VCCIO 3.3 V;
+BANK 3 VCCIO 3.3 V;
+BANK 4 VCCIO 3.3 V;
+BANK 5 VCCIO 3.3 V;
+BLOCK ASYNCPATHS ;
+BLOCK JTAGPATHS ;
+BLOCK PATH FROM PORT "button" ;
+BLOCK RESETPATHS ;
+IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
+IOBUF PORT "button" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "flash_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "flash_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "flash_dq[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "flash_dq[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "flash_dq[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "flash_dq[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "inclk" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "mcu_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "mcu_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "mcu_int" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "mcu_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "mcu_mosi" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "n64_irq" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_nmi" PULLMODE=DOWN IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_ad[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_aleh" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_alel" PULLMODE=DOWN IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_read" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_pi_write" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_reset" PULLMODE=DOWN IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_si_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 ;
+IOBUF PORT "n64_si_dq" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sd_dat[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sd_dat[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sd_dat[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sd_dat[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sd_det" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_cas" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dq[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_ras" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "sdram_we" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miosi[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miosi[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miosi[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miosi[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miosi[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miosi[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miosi[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miosi[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_miso" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "usb_pwrsav" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+LOCATE COMP "button" SITE "1" ;
+LOCATE COMP "flash_clk" SITE "142" ;
+LOCATE COMP "flash_cs" SITE "138" ;
+LOCATE COMP "flash_dq[0]" SITE "141" ;
+LOCATE COMP "flash_dq[1]" SITE "139" ;
+LOCATE COMP "flash_dq[2]" SITE "140" ;
+LOCATE COMP "flash_dq[3]" SITE "143" ;
+LOCATE COMP "inclk" SITE "3" ;
+LOCATE COMP "mcu_clk" SITE "121" ;
+LOCATE COMP "mcu_cs" SITE "122" ;
+LOCATE COMP "mcu_int" SITE "117" ;
+LOCATE COMP "mcu_miso" SITE "119" ;
+LOCATE COMP "mcu_mosi" SITE "120" ;
+LOCATE COMP "n64_irq" SITE "32" ;
+LOCATE COMP "n64_nmi" SITE "28" ;
+LOCATE COMP "n64_pi_ad[0]" SITE "60" ;
+LOCATE COMP "n64_pi_ad[1]" SITE "58" ;
+LOCATE COMP "n64_pi_ad[10]" SITE "42" ;
+LOCATE COMP "n64_pi_ad[11]" SITE "44" ;
+LOCATE COMP "n64_pi_ad[12]" SITE "52" ;
+LOCATE COMP "n64_pi_ad[13]" SITE "55" ;
+LOCATE COMP "n64_pi_ad[14]" SITE "57" ;
+LOCATE COMP "n64_pi_ad[15]" SITE "59" ;
+LOCATE COMP "n64_pi_ad[2]" SITE "56" ;
+LOCATE COMP "n64_pi_ad[3]" SITE "54" ;
+LOCATE COMP "n64_pi_ad[4]" SITE "45" ;
+LOCATE COMP "n64_pi_ad[5]" SITE "43" ;
+LOCATE COMP "n64_pi_ad[6]" SITE "40" ;
+LOCATE COMP "n64_pi_ad[7]" SITE "38" ;
+LOCATE COMP "n64_pi_ad[8]" SITE "39" ;
+LOCATE COMP "n64_pi_ad[9]" SITE "41" ;
+LOCATE COMP "n64_pi_aleh" SITE "48" ;
+LOCATE COMP "n64_pi_alel" SITE "50" ;
+LOCATE COMP "n64_pi_read" SITE "47" ;
+LOCATE COMP "n64_pi_write" SITE "49" ;
+LOCATE COMP "n64_reset" SITE "31" ;
+LOCATE COMP "n64_si_clk" SITE "33" ;
+LOCATE COMP "n64_si_dq" SITE "27" ;
+LOCATE COMP "sd_clk" SITE "111" ;
+LOCATE COMP "sd_cmd" SITE "112" ;
+LOCATE COMP "sd_dat[0]" SITE "110" ;
+LOCATE COMP "sd_dat[1]" SITE "109" ;
+LOCATE COMP "sd_dat[2]" SITE "114" ;
+LOCATE COMP "sd_dat[3]" SITE "113" ;
+LOCATE COMP "sd_det" SITE "115" ;
+LOCATE COMP "sdram_a[0]" SITE "85" ;
+LOCATE COMP "sdram_a[1]" SITE "86" ;
+LOCATE COMP "sdram_a[10]" SITE "84" ;
+LOCATE COMP "sdram_a[11]" SITE "63" ;
+LOCATE COMP "sdram_a[12]" SITE "62" ;
+LOCATE COMP "sdram_a[2]" SITE "87" ;
+LOCATE COMP "sdram_a[3]" SITE "89" ;
+LOCATE COMP "sdram_a[4]" SITE "71" ;
+LOCATE COMP "sdram_a[5]" SITE "70" ;
+LOCATE COMP "sdram_a[6]" SITE "69" ;
+LOCATE COMP "sdram_a[7]" SITE "68" ;
+LOCATE COMP "sdram_a[8]" SITE "67" ;
+LOCATE COMP "sdram_a[9]" SITE "65" ;
+LOCATE COMP "sdram_ba[0]" SITE "92" ;
+LOCATE COMP "sdram_ba[1]" SITE "91" ;
+LOCATE COMP "sdram_cas" SITE "95" ;
+LOCATE COMP "sdram_clk" SITE "61" ;
+LOCATE COMP "sdram_cs" SITE "93" ;
+LOCATE COMP "sdram_dq[0]" SITE "107" ;
+LOCATE COMP "sdram_dq[1]" SITE "106" ;
+LOCATE COMP "sdram_dq[10]" SITE "76" ;
+LOCATE COMP "sdram_dq[11]" SITE "77" ;
+LOCATE COMP "sdram_dq[12]" SITE "78" ;
+LOCATE COMP "sdram_dq[13]" SITE "81" ;
+LOCATE COMP "sdram_dq[14]" SITE "82" ;
+LOCATE COMP "sdram_dq[15]" SITE "83" ;
+LOCATE COMP "sdram_dq[2]" SITE "105" ;
+LOCATE COMP "sdram_dq[3]" SITE "104" ;
+LOCATE COMP "sdram_dq[4]" SITE "103" ;
+LOCATE COMP "sdram_dq[5]" SITE "100" ;
+LOCATE COMP "sdram_dq[6]" SITE "99" ;
+LOCATE COMP "sdram_dq[7]" SITE "98" ;
+LOCATE COMP "sdram_dq[8]" SITE "74" ;
+LOCATE COMP "sdram_dq[9]" SITE "75" ;
+LOCATE COMP "sdram_dqm[0]" SITE "97" ;
+LOCATE COMP "sdram_dqm[1]" SITE "73" ;
+LOCATE COMP "sdram_ras" SITE "94" ;
+LOCATE COMP "sdram_we" SITE "96" ;
+LOCATE COMP "usb_clk" SITE "12" ;
+LOCATE COMP "usb_cs" SITE "11" ;
+LOCATE COMP "usb_miosi[0]" SITE "22" ;
+LOCATE COMP "usb_miosi[1]" SITE "21" ;
+LOCATE COMP "usb_miosi[2]" SITE "20" ;
+LOCATE COMP "usb_miosi[3]" SITE "19" ;
+LOCATE COMP "usb_miosi[4]" SITE "17" ;
+LOCATE COMP "usb_miosi[5]" SITE "15" ;
+LOCATE COMP "usb_miosi[6]" SITE "14" ;
+LOCATE COMP "usb_miosi[7]" SITE "13" ;
+LOCATE COMP "usb_miso" SITE "10" ;
+LOCATE COMP "usb_pwrsav" SITE "2" ;
+SYSCONFIG SDM_PORT=DISABLE ;
+VOLTAGE 3.300 V;
diff --git a/fw/project/lcmxo2/sc64.sty b/fw/project/lcmxo2/sc64.sty
new file mode 100644
index 0000000..ee5086b
--- /dev/null
+++ b/fw/project/lcmxo2/sc64.sty
@@ -0,0 +1,205 @@
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diff --git a/fw/rtl/SummerCart64.sv b/fw/rtl/SummerCart64.sv
deleted file mode 100644
index ac2b36f..0000000
--- a/fw/rtl/SummerCart64.sv
+++ /dev/null
@@ -1,138 +0,0 @@
-module SummerCart64 (
- input i_clk,
-
- input i_n64_reset,
- input i_n64_nmi,
- output o_n64_irq,
-
- input i_n64_pi_alel,
- input i_n64_pi_aleh,
- input i_n64_pi_read,
- input i_n64_pi_write,
- inout [15:0] io_n64_pi_ad,
-
- input i_n64_si_clk,
- inout io_n64_si_dq,
-
- output o_sdram_clk,
- output o_sdram_cs,
- output o_sdram_ras,
- output o_sdram_cas,
- output o_sdram_we,
- output [1:0] o_sdram_ba,
- output [12:0] o_sdram_a,
- inout [15:0] io_sdram_dq,
-
- output o_rtc_scl,
- inout io_rtc_sda,
-
- output o_usb_clk,
- output o_usb_cs,
- input i_usb_miso,
- inout [7:0] io_usb_miosi,
-
- input i_uart_rxd,
- output o_uart_txd,
-
- output o_sd_clk,
- inout io_sd_cmd,
- inout [3:0] io_sd_dat,
-
- output o_led
-);
-
- logic dd_interrupt;
-
- if_system sys (
- .in_clk(i_clk),
- .n64_reset(i_n64_reset),
- .n64_nmi(i_n64_nmi)
- );
-
- if_config cfg ();
-
- if_memory_dma usb_dma ();
-
- if_sdram sdram ();
-
- if_flashram flashram ();
-
- if_si si ();
-
- if_flash flash ();
-
- if_dd dd (
- .dd_interrupt(dd_interrupt)
- );
-
-
- system system_inst (
- .sys(sys)
- );
-
- intel_gpio_ddro sdram_clk_ddro (
- .outclock(sys.sdram.sdram_clk),
- .din({1'b0, 1'b1}),
- .pad_out(o_sdram_clk)
- );
-
- n64_soc n64_soc_inst (
- .sys(sys),
- .cfg(cfg),
- .usb_dma(usb_dma),
- .sdram(sdram),
- .flashram(flashram),
- .si(si),
- .flash(flash),
- .dd(dd),
-
- .n64_pi_alel(i_n64_pi_alel),
- .n64_pi_aleh(i_n64_pi_aleh),
- .n64_pi_read(i_n64_pi_read),
- .n64_pi_write(i_n64_pi_write),
- .n64_pi_ad(io_n64_pi_ad),
-
- .n64_si_clk(i_n64_si_clk),
- .n64_si_dq(io_n64_si_dq),
-
- .sdram_cs(o_sdram_cs),
- .sdram_ras(o_sdram_ras),
- .sdram_cas(o_sdram_cas),
- .sdram_we(o_sdram_we),
- .sdram_ba(o_sdram_ba),
- .sdram_a(o_sdram_a),
- .sdram_dq(io_sdram_dq)
- );
-
- cpu_soc cpu_soc_inst (
- .sys(sys),
- .cfg(cfg),
- .usb_dma(usb_dma),
- .sdram(sdram),
- .flashram(flashram),
- .si(si),
- .flash(flash),
- .dd(dd),
-
- .i2c_scl(o_rtc_scl),
- .i2c_sda(io_rtc_sda),
-
- .usb_clk(o_usb_clk),
- .usb_cs(o_usb_cs),
- .usb_miso(i_usb_miso),
- .usb_miosi(io_usb_miosi),
-
- .uart_rxd(i_uart_rxd),
- .uart_txd(o_uart_txd),
-
- .sd_clk(o_sd_clk),
- .sd_cmd(io_sd_cmd),
- .sd_dat(io_sd_dat)
- );
-
- always_comb begin
- o_n64_irq = dd_interrupt ? 1'b0 : 1'bZ;
- o_led = 1'bZ;
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_bus.sv b/fw/rtl/cpu/cpu_bus.sv
deleted file mode 100644
index b2b1e14..0000000
--- a/fw/rtl/cpu/cpu_bus.sv
+++ /dev/null
@@ -1,54 +0,0 @@
-interface if_cpu_bus #(
- parameter bit [3:0] NUM_DEVICES
-) ();
-
- logic request;
- logic ack;
- logic [3:0] wmask;
- logic [31:0] address;
- logic [31:0] wdata;
- logic [31:0] rdata;
-
- logic device_ack [(NUM_DEVICES - 1):0];
- logic [31:0] device_rdata [(NUM_DEVICES - 1):0];
-
- always_comb begin
- ack = 1'b0;
- rdata = 32'd0;
-
- for (integer i = 0; i < NUM_DEVICES; i++) begin
- ack = ack | device_ack[i];
- rdata = rdata | device_rdata[i];
- end
- end
-
- modport cpu (
- output request,
- input ack,
- output wmask,
- output address,
- output wdata,
- input rdata
- );
-
- genvar n;
- generate
- for (n = 0; n < NUM_DEVICES; n++) begin : at
- logic device_request;
-
- always_comb begin
- device_request = request && address[31:28] == n[3:0];
- end
-
- modport device (
- input .request(device_request),
- output .ack(device_ack[n]),
- input .wmask(wmask),
- input .address(address),
- input .wdata(wdata),
- output .rdata(device_rdata[n])
- );
- end
- endgenerate
-
-endinterface
diff --git a/fw/rtl/cpu/cpu_cfg.sv b/fw/rtl/cpu/cpu_cfg.sv
deleted file mode 100644
index a587216..0000000
--- a/fw/rtl/cpu/cpu_cfg.sv
+++ /dev/null
@@ -1,142 +0,0 @@
-module cpu_cfg (
- if_system.sys sys,
- if_cpu_bus bus,
- if_config.cpu cfg
-);
-
- logic skip_bootloader;
- logic enable_writes_on_reset;
- logic trigger_reconfiguration;
-
- typedef enum bit [2:0] {
- R_SCR,
- R_COMMAND,
- R_DATA_0,
- R_DATA_1,
- R_VERSION,
- R_RECONFIGURE
- } e_reg_id;
-
- const logic [31:0] RECONFIGURE_MAGIC = 32'h52535446;
-
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- if (bus.request) begin
- bus.ack <= 1'b1;
- end
- end
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- case (bus.address[4:2])
- R_SCR: bus.rdata = {
- cfg.cpu_ready,
- cfg.cpu_busy,
- 1'b0,
- cfg.cmd_error,
- 2'd0,
- cfg.flash_erase_busy,
- 1'd0,
- 16'd0,
- enable_writes_on_reset,
- skip_bootloader,
- cfg.flashram_enabled,
- cfg.sram_banked,
- cfg.sram_enabled,
- cfg.dd_enabled,
- cfg.sdram_writable,
- cfg.sdram_switch
- };
- R_COMMAND: bus.rdata = {24'd0, cfg.cmd};
- R_DATA_0: bus.rdata = cfg.data[0];
- R_DATA_1: bus.rdata = cfg.data[1];
- R_VERSION: bus.rdata = sc64::SC64_VER;
- R_RECONFIGURE: bus.rdata = RECONFIGURE_MAGIC;
- default: bus.rdata = 32'd0;
- endcase
- end
- end
-
- always_comb begin
- cfg.wdata = bus.wdata;
- cfg.data_write = 2'b00;
- if (bus.request && (&bus.wmask)) begin
- cfg.data_write[0] = bus.address[4:2] == R_DATA_0;
- cfg.data_write[1] = bus.address[4:2] == R_DATA_1;
- end
- end
-
- always_ff @(posedge sys.clk) begin
- cfg.flash_erase_start <= 1'b0;
- cfg.flash_wp_enable <= 1'b0;
- cfg.flash_wp_disable <= 1'b0;
-
- if (sys.reset) begin
- cfg.cpu_ready <= 1'b0;
- cfg.cpu_busy <= 1'b0;
- cfg.cmd_error <= 1'b0;
- cfg.sdram_switch <= 1'b0;
- cfg.sdram_writable <= 1'b0;
- cfg.dd_enabled <= 1'b0;
- cfg.sram_enabled <= 1'b0;
- cfg.sram_banked <= 1'b0;
- cfg.flashram_enabled <= 1'b0;
- skip_bootloader <= 1'b0;
- enable_writes_on_reset <= 1'b0;
- trigger_reconfiguration <= 1'b0;
- end else begin
- if (sys.n64_soft_reset) begin
- cfg.sdram_switch <= skip_bootloader;
- cfg.sdram_writable <= enable_writes_on_reset;
- end
-
- if (cfg.cmd_request) begin
- cfg.cpu_busy <= 1'b1;
- end
-
- if (bus.request) begin
- case (bus.address[4:2])
- R_SCR: begin
- if (bus.wmask[3]) begin
- {
- cfg.cpu_ready,
- cfg.cpu_busy,
- cfg.cmd_error,
- cfg.flash_wp_disable,
- cfg.flash_wp_enable,
- cfg.flash_erase_start
- } <= {bus.wdata[31:30], bus.wdata[28:26], bus.wdata[24]};
- end
- if (bus.wmask[0]) begin
- {
- enable_writes_on_reset,
- skip_bootloader,
- cfg.flashram_enabled,
- cfg.sram_banked,
- cfg.sram_enabled,
- cfg.dd_enabled,
- cfg.sdram_writable,
- cfg.sdram_switch
- } <= bus.wdata[7:0];
- end
- end
-
- R_RECONFIGURE: begin
- if (&bus.wmask && bus.wdata == RECONFIGURE_MAGIC) begin
- trigger_reconfiguration <= 1'b1;
- end
- end
- endcase
- end
- end
- end
-
- vendor_reconfigure vendor_reconfigure_inst (
- .clk(sys.clk),
- .reset(sys.reset),
-
- .trigger_reconfiguration(trigger_reconfiguration)
- );
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_dd.sv b/fw/rtl/cpu/cpu_dd.sv
deleted file mode 100644
index f4227d2..0000000
--- a/fw/rtl/cpu/cpu_dd.sv
+++ /dev/null
@@ -1,141 +0,0 @@
-module cpu_dd (
- if_system.sys sys,
- if_cpu_bus bus,
- if_dd.cpu dd
-);
-
- const bit [8:0] M_SECTOR_BUFFER = 9'h100;
-
- logic bm_ack;
- logic [31:0] seek_timer;
-
- typedef enum bit [2:0] {
- R_SCR,
- R_CMD_DATA,
- R_HEAD_TRACK,
- R_SECTOR_INFO,
- R_DRIVE_ID,
- R_SEEK_TIMER
- } e_reg_id;
-
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- if (bus.request) begin
- bus.ack <= 1'b1;
- end
- end
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- if (bus.address[8] == M_SECTOR_BUFFER[8]) begin
- bus.rdata = {
- dd.sector_rdata[7:0],
- dd.sector_rdata[15:8],
- dd.sector_rdata[23:16],
- dd.sector_rdata[31:24]
- };
- end else begin
- case (bus.address[5:2])
- R_SCR: bus.rdata = {
- 14'd0,
- bm_ack,
- dd.bm_micro_error,
- dd.bm_transfer_c2,
- dd.bm_transfer_data,
- dd.bm_transfer_blocks,
- dd.bm_transfer_mode,
- 1'b0,
- dd.bm_stop_pending,
- 1'b0,
- dd.bm_start_pending,
- dd.disk_changed,
- dd.disk_inserted,
- 1'b0,
- dd.bm_pending,
- 1'b0,
- dd.cmd_pending,
- 1'b0,
- dd.hard_reset
- };
- R_CMD_DATA: bus.rdata = {8'd0, dd.cmd, dd.data};
- R_HEAD_TRACK: bus.rdata = {18'd0, dd.index_lock, dd.head_track};
- R_SECTOR_INFO: bus.rdata = {
- dd.sectors_in_block,
- dd.sector_size_full,
- dd.sector_size,
- dd.sector_num
- };
- R_DRIVE_ID: bus.rdata = {dd.drive_id};
- R_SEEK_TIMER: bus.rdata = seek_timer;
- default: bus.rdata = 32'd0;
- endcase
- end
- end
- end
-
- always_comb begin
- dd.sector_address = bus.address[7:2];
- dd.sector_address_valid = bus.request && bus.address[8] == M_SECTOR_BUFFER[8];
- dd.sector_write = (&bus.wmask) && dd.sector_address_valid;
- dd.sector_wdata = {bus.wdata[7:0], bus.wdata[15:8], bus.wdata[23:16], bus.wdata[31:24]};
- end
-
- always_ff @(posedge sys.clk) begin
- dd.hard_reset_clear <= 1'b0;
- dd.cmd_ready <= 1'b0;
- dd.bm_start_clear <= 1'b0;
- dd.bm_stop_clear <= 1'b0;
- dd.bm_clear <= 1'b0;
- dd.bm_ready <= 1'b0;
-
- if (dd.bm_interrupt_ack) begin
- bm_ack <= 1'b1;
- end
-
- if (!(&seek_timer)) begin
- seek_timer <= seek_timer + 1'd1;
- end
-
- if (sys.reset) begin
- bm_ack <= 1'b0;
- end else begin
- if (bus.request && (!bus.address[8])) begin
- case (bus.address[4:2])
- R_SCR: if (&bus.wmask) begin
- if (bus.wdata[20]) begin
- seek_timer <= 32'd0;
- end
- dd.bm_clear <= bus.wdata[19];
- if (bus.wdata[18]) begin
- bm_ack <= 1'b0;
- end
- dd.bm_micro_error <= bus.wdata[16];
- dd.bm_transfer_c2 <= bus.wdata[15];
- dd.bm_transfer_data <= bus.wdata[14];
- dd.bm_stop_clear <= bus.wdata[11];
- dd.bm_start_clear <= bus.wdata[9];
- dd.disk_changed <= bus.wdata[7];
- dd.disk_inserted <= bus.wdata[6];
- dd.bm_ready <= bus.wdata[5];
- dd.cmd_ready <= bus.wdata[3];
- dd.hard_reset_clear <= bus.wdata[1];
- end
-
- R_CMD_DATA: if (&bus.wmask[1:0]) begin
- dd.cmd_data <= bus.wdata[15:0];
- end
-
- R_HEAD_TRACK: if (&bus.wmask[1:0]) begin
- {dd.index_lock, dd.head_track} <= bus.wdata[13:0];
- end
-
- R_DRIVE_ID: if (&bus.wmask[1:0]) begin
- dd.drive_id <= bus.wdata[15:0];
- end
- endcase
- end
- end
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_flash.sv b/fw/rtl/cpu/cpu_flash.sv
deleted file mode 100644
index fbc0cc3..0000000
--- a/fw/rtl/cpu/cpu_flash.sv
+++ /dev/null
@@ -1,61 +0,0 @@
-interface if_flash ();
-
- logic request;
- logic ack;
- logic write;
- logic [31:0] address;
- logic [31:0] rdata;
- logic [31:0] wdata;
-
- modport cpu (
- output request,
- input ack,
- output write,
- output address,
- input rdata,
- output wdata
- );
-
- modport flash (
- input request,
- output ack,
- input write,
- input address,
- output rdata,
- input wdata
- );
-
-endinterface
-
-
-module cpu_flash (
- if_system.sys sys,
- if_cpu_bus bus,
- if_flash.cpu flash
-);
-
- logic request;
-
- always_comb begin
- bus.ack = flash.ack;
- bus.rdata = flash.rdata;
- flash.request = bus.request || request;
- flash.write = &bus.wmask;
- flash.address = bus.address;
- flash.wdata = bus.wdata;
- end
-
- always_ff @(posedge sys.clk) begin
- if (sys.reset) begin
- request <= 1'b0;
- end else begin
- if (bus.request) begin
- request <= 1'b1;
- end
- if (flash.ack) begin
- request <= 1'b0;
- end
- end
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_flashram.sv b/fw/rtl/cpu/cpu_flashram.sv
deleted file mode 100644
index 7519811..0000000
--- a/fw/rtl/cpu/cpu_flashram.sv
+++ /dev/null
@@ -1,77 +0,0 @@
-interface if_flashram ();
-
- logic [4:0] address;
- logic [31:0] rdata;
- logic [9:0] sector;
- logic operation_pending;
- logic write_or_erase;
- logic sector_or_all;
- logic operation_done;
-
- modport cpu (
- output address,
- input rdata,
- input sector,
- input operation_pending,
- input write_or_erase,
- input sector_or_all,
- output operation_done
- );
-
- modport flashram (
- input address,
- output rdata,
- output sector,
- output operation_pending,
- output write_or_erase,
- output sector_or_all,
- input operation_done
- );
-
-endinterface
-
-
-module cpu_flashram (
- if_system.sys sys,
- if_cpu_bus bus,
- if_flashram.cpu flashram
-);
-
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- if (bus.request) begin
- bus.ack <= 1'b1;
- end
- end
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- bus.rdata = {
- 14'd0,
- flashram.sector,
- 4'd0,
- flashram.sector_or_all,
- flashram.write_or_erase,
- 1'b0,
- flashram.operation_pending
- };
- if (bus.address[7]) begin
- bus.rdata = {flashram.rdata[7:0], flashram.rdata[15:8], flashram.rdata[23:16], flashram.rdata[31:24]};
- end
- end
-
- flashram.address = bus.address[6:2];
- end
-
- always_ff @(posedge sys.clk) begin
- flashram.operation_done <= 1'b0;
-
- if (bus.request) begin
- if (!bus.address[7] && bus.wmask[0]) begin
- flashram.operation_done <= bus.wdata[1];
- end
- end
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_i2c.sv b/fw/rtl/cpu/cpu_i2c.sv
deleted file mode 100644
index ab2c7e2..0000000
--- a/fw/rtl/cpu/cpu_i2c.sv
+++ /dev/null
@@ -1,155 +0,0 @@
-module cpu_i2c (
- if_system.sys sys,
- if_cpu_bus bus,
-
- output i2c_scl,
- inout i2c_sda
-);
-
- reg [1:0] state;
- reg mack;
- reg [8:0] trx_data;
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- case (bus.address[2])
- 0: bus.rdata = {27'd0, |state, ~trx_data[0], mack, 2'b00};
- 1: bus.rdata = {23'd0, trx_data[0], trx_data[8:1]};
- default: bus.rdata = 32'd0;
- endcase
- end
- end
-
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- if (bus.request) begin
- bus.ack <= 1'b1;
- end
-
- if (sys.reset) begin
- mack <= 1'b0;
- end else if (bus.request && bus.wmask[0] && !bus.address[2]) begin
- mack <= bus.wdata[2];
- end
- end
-
- reg [5:0] clock_div;
- reg [3:0] clock_phase_gen;
-
- wire clock_tick = &clock_div;
- wire [3:0] clock_phase = {4{clock_tick}} & clock_phase_gen;
-
- always_ff @(posedge sys.clk) begin
- if (sys.reset) begin
- clock_div <= 6'd0;
- end else begin
- clock_div <= clock_div + 1'd1;
- end
-
- if (sys.reset || state == 2'd0) begin
- clock_phase_gen <= 4'b0001;
- end else if (clock_tick) begin
- clock_phase_gen <= {clock_phase_gen[2:0], clock_phase_gen[3]};
- end
- end
-
- reg [3:0] bit_counter;
-
- reg sda_i_ff1, sda_i_ff2;
- reg scl_o;
- reg sda_o;
-
- assign i2c_scl = scl_o ? 1'bZ : 1'b0;
- assign i2c_sda = sda_o ? 1'bZ : 1'b0;
-
- always_ff @(posedge sys.clk) begin
- {sda_i_ff2, sda_i_ff1} <= {sda_i_ff1, i2c_sda};
-
- if (sys.reset) begin
- state <= 2'd0;
- scl_o <= 1'b1;
- sda_o <= 1'b1;
- end else begin
- case (state)
- 2'd0: begin
- bit_counter <= 4'd0;
-
- if (bus.request && bus.wmask[0]) begin
- case (bus.address[2])
- 0: begin
- if (bus.wdata[1]) state <= 2'd2;
- if (bus.wdata[0]) state <= 2'd1;
- end
-
- 1: begin
- state <= 2'd3;
- trx_data <= {bus.wdata[7:0], ~mack};
- end
- endcase
- end
- end
-
- 2'd1: begin
- if (clock_phase[0]) begin
- scl_o <= 1'b1;
- sda_o <= 1'b1;
- end
-
- if (clock_phase[1]) begin
- sda_o <= 1'b0;
- end
-
- if (clock_phase[3]) begin
- state <= 2'd0;
- scl_o <= 1'b0;
- end
- end
-
- 2'd2: begin
- if (clock_phase[0]) begin
- scl_o <= 1'b0;
- sda_o <= 1'b0;
- end
-
- if (clock_phase[1]) begin
- scl_o <= 1'b1;
- end
-
- if (clock_phase[3]) begin
- state <= 2'd0;
- sda_o <= 1'b1;
- end
- end
-
- 2'd3: begin
- if (clock_phase[0]) begin
- bit_counter <= bit_counter + 1'd1;
- scl_o <= 1'b0;
- sda_o <= trx_data[8];
- end
-
- if (clock_phase[1]) begin
- scl_o <= 1'b1;
- end
-
- if (clock_phase[3]) begin
- trx_data <= {trx_data[7:0], sda_i_ff2};
- scl_o <= 1'b0;
- end
-
- if (bit_counter == 4'b1010) begin
- state <= 2'd0;
- end
- end
-
- default: begin
- state <= 2'd0;
- scl_o <= 1'b1;
- sda_o <= 1'b1;
- end
- endcase
- end
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_ram.sv b/fw/rtl/cpu/cpu_ram.sv
deleted file mode 100644
index 30dff79..0000000
--- a/fw/rtl/cpu/cpu_ram.sv
+++ /dev/null
@@ -1,33 +0,0 @@
-module cpu_ram (
- if_system.sys sys,
- if_cpu_bus bus
-);
-
- logic [3:0][7:0] ram [0:4095];
- logic [31:0] q;
-
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- if (bus.request) begin
- bus.ack <= 1'b1;
- end
- end
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- bus.rdata = q;
- end
- end
-
- always_ff @(posedge sys.clk) begin
- q <= ram[bus.address[13:2]];
- if (bus.request) begin
- if (bus.wmask[0]) ram[bus.address[13:2]][0] <= bus.wdata[7:0];
- if (bus.wmask[1]) ram[bus.address[13:2]][1] <= bus.wdata[15:8];
- if (bus.wmask[2]) ram[bus.address[13:2]][2] <= bus.wdata[23:16];
- if (bus.wmask[3]) ram[bus.address[13:2]][3] <= bus.wdata[31:24];
- end
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_sdram.sv b/fw/rtl/cpu/cpu_sdram.sv
deleted file mode 100644
index 6f01317..0000000
--- a/fw/rtl/cpu/cpu_sdram.sv
+++ /dev/null
@@ -1,76 +0,0 @@
-interface if_sdram ();
-
- logic request;
- logic ack;
- logic write;
- logic [31:0] address;
- logic [15:0] rdata;
- logic [15:0] wdata;
-
- modport cpu (
- output request,
- input ack,
- output write,
- output address,
- input rdata,
- output wdata
- );
-
- modport memory (
- input request,
- output ack,
- input write,
- input address,
- output rdata,
- input wdata
- );
-
-endinterface
-
-
-module cpu_sdram (
- if_system.sys sys,
- if_cpu_bus bus,
- if_sdram.cpu sdram
-);
-
- logic request;
- logic current_word;
- logic [31:0] rdata;
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- bus.rdata = {rdata[7:0], rdata[15:8], rdata[23:16], rdata[31:24]};
- end
-
- sdram.write = current_word ? &bus.wmask[1:0] : &bus.wmask[3:2];
- sdram.address = {1'b0, bus.address[30:2], current_word, 1'b0};
- sdram.wdata = current_word ? {bus.wdata[23:16], bus.wdata[31:24]} : {bus.wdata[7:0], bus.wdata[15:8]};
- end
-
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
-
- if (sys.reset) begin
- sdram.request <= 1'b0;
- end else begin
- if (bus.request) begin
- sdram.request <= 1'b1;
- current_word <= 1'b0;
- end
-
- if (sdram.ack) begin
- if (!current_word) begin
- current_word <= 1'b1;
- rdata[31:16] <= sdram.rdata;
- end else begin
- bus.ack <= 1'b1;
- sdram.request <= 1'b0;
- rdata[15:0] <= sdram.rdata;
- end
- end
- end
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_si.sv b/fw/rtl/cpu/cpu_si.sv
deleted file mode 100644
index 2197d68..0000000
--- a/fw/rtl/cpu/cpu_si.sv
+++ /dev/null
@@ -1,59 +0,0 @@
-module cpu_si (
- if_system.sys sys,
- if_cpu_bus bus,
- if_si.cpu si
-);
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- if (bus.request) begin
- bus.ack <= 1'b1;
- end
- end
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- case (bus.address[3:2])
- 0: bus.rdata = {
- 20'd0,
- si.rx_length[6:3],
- 4'd0,
- si.tx_busy,
- 1'b0,
- si.rx_data[0],
- si.rx_ready
- };
- 1: bus.rdata = {si.rx_data[56:49], si.rx_data[64:57], si.rx_data[72:65], si.rx_data[80:73]};
- 2: bus.rdata = {si.rx_data[24:17], si.rx_data[32:25], si.rx_data[40:33], si.rx_data[48:41]};
- 3: bus.rdata = {16'd0, si.rx_data[8:1], si.rx_data[16:9]};
- default: bus.rdata = 32'd0;
- endcase
- end
- end
-
- always_comb begin
- si.tx_data = {bus.wdata[7:0], bus.wdata[15:8], bus.wdata[23:16], bus.wdata[31:24]};
- si.tx_length = bus.wdata[22:16];
- end
-
- always_ff @(posedge sys.clk) begin
- si.tx_reset <= 1'b0;
- si.rx_reset <= 1'b0;
- si.tx_start <= 1'b0;
- si.tx_wmask <= 3'b000;
-
- if (bus.request && (&bus.wmask)) begin
- case (bus.address[3:2])
- 0: begin
- si.tx_reset <= bus.wdata[7];
- si.rx_reset <= bus.wdata[6];
- si.tx_start <= bus.wdata[2];
- end
- 1: si.tx_wmask[0] <= 1'b1;
- 2: si.tx_wmask[1] <= 1'b1;
- 3: si.tx_wmask[2] <= 1'b1;
- endcase
- end
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_soc.sv b/fw/rtl/cpu/cpu_soc.sv
deleted file mode 100644
index 36eac9b..0000000
--- a/fw/rtl/cpu/cpu_soc.sv
+++ /dev/null
@@ -1,123 +0,0 @@
-module cpu_soc (
- if_system.sys sys,
- if_config.cpu cfg,
- if_memory_dma usb_dma,
- if_sdram.cpu sdram,
- if_flashram.cpu flashram,
- if_si.cpu si,
- if_flash flash,
- if_dd.cpu dd,
-
- output i2c_scl,
- inout i2c_sda,
-
- output usb_clk,
- output usb_cs,
- input usb_miso,
- inout [7:0] usb_miosi,
-
- input uart_rxd,
- output uart_txd,
-
- output sd_clk,
- inout sd_cmd,
- inout [3:0] sd_dat
-);
-
- typedef enum bit [3:0] {
- DEV_FLASH,
- DEV_RAM,
- DEV_CFG,
- DEV_I2C,
- DEV_USB,
- DEV_UART,
- DEV_DD,
- DEV_SDRAM,
- DEV_FLASHRAM,
- DEV_SI,
- __NUM_DEVICES
- } e_bus_id;
-
- if_cpu_bus #(
- .NUM_DEVICES(__NUM_DEVICES)
- ) bus ();
-
- cpu_wrapper cpu_wrapper_inst (
- .sys(sys),
- .bus(bus)
- );
-
- cpu_flash cpu_flash_inst (
- .sys(sys),
- .bus(bus.at[DEV_FLASH].device),
- .flash(flash)
- );
-
- cpu_ram cpu_ram_inst (
- .sys(sys),
- .bus(bus.at[DEV_RAM].device)
- );
-
- cpu_cfg cpu_cfg_inst (
- .sys(sys),
- .bus(bus.at[DEV_CFG].device),
- .cfg(cfg)
- );
-
- cpu_i2c cpu_i2c_inst (
- .sys(sys),
- .bus(bus.at[DEV_I2C].device),
- .i2c_scl(i2c_scl),
- .i2c_sda(i2c_sda)
- );
-
- cpu_usb cpu_usb_inst (
- .sys(sys),
- .bus(bus.at[DEV_USB].device),
- .dma(usb_dma),
- .usb_clk(usb_clk),
- .usb_cs(usb_cs),
- .usb_miso(usb_miso),
- .usb_miosi(usb_miosi)
- );
-
- generate
- if (sc64::CPU_HAS_UART) begin
- cpu_uart cpu_uart_inst (
- .sys(sys),
- .bus(bus.at[DEV_UART].device),
- .uart_rxd(uart_rxd),
- .uart_txd(uart_txd)
- );
- end
- endgenerate
-
- cpu_dd cpu_dd_inst (
- .sys(sys),
- .bus(bus.at[DEV_DD].device),
- .dd(dd)
- );
-
- cpu_sdram cpu_sdram_inst (
- .sys(sys),
- .bus(bus.at[DEV_SDRAM].device),
- .sdram(sdram)
- );
-
- cpu_flashram cpu_flashram_inst (
- .sys(sys),
- .bus(bus.at[DEV_FLASHRAM].device),
- .flashram(flashram)
- );
-
- cpu_si cpu_si_inst (
- .sys(sys),
- .bus(bus.at[DEV_SI].device),
- .si(si)
- );
-
- assign sd_clk = 1'bZ;
- assign sd_cmd = 1'bZ;
- assign sd_dat = 4'bZZZZ;
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_uart.sv b/fw/rtl/cpu/cpu_uart.sv
deleted file mode 100644
index 6da1ed1..0000000
--- a/fw/rtl/cpu/cpu_uart.sv
+++ /dev/null
@@ -1,153 +0,0 @@
-module cpu_uart (
- if_system.sys sys,
- if_cpu_bus bus,
-
- input uart_rxd,
- output uart_txd
-);
-
- localparam BAUD_GEN_VALUE = int'(sc64::CLOCK_FREQUENCY / sc64::UART_BAUD_RATE) - 1'd1;
-
- typedef enum bit [1:0] {
- S_TRX_IDLE,
- S_TRX_DATA,
- S_TRX_SAMPLING_OFFSET
- } e_trx_state;
-
-
- // CPU bus controller
-
- e_trx_state tx_state;
- e_trx_state rx_state;
- logic [7:0] rx_data;
- logic rx_available;
- logic rx_overrun;
-
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- if (bus.request) begin
- bus.ack <= 1'b1;
- end
- end
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- case (bus.address[2:2])
- 0: bus.rdata = {29'd0, rx_overrun, tx_state == S_TRX_IDLE, rx_available};
- 1: bus.rdata = {24'd0, rx_data};
- default: bus.rdata = 32'd0;
- endcase
- end
- end
-
-
- // TX path
-
- logic [6:0] tx_baud_counter;
- logic [3:0] tx_bit_counter;
- logic [9:0] tx_shifter;
-
- always_ff @(posedge sys.clk) begin
- tx_baud_counter <= tx_baud_counter + 1'd1;
- uart_txd <= tx_shifter[0];
-
- if (sys.reset) begin
- tx_state <= S_TRX_IDLE;
- tx_shifter <= 10'h3FF;
- end else begin
- case (tx_state)
- S_TRX_IDLE: begin
- if (bus.request && bus.wmask[0] && bus.address[2]) begin
- tx_state <= S_TRX_DATA;
- tx_baud_counter <= 7'd0;
- tx_bit_counter <= 4'd0;
- tx_shifter <= {1'b1, bus.wdata[7:0], 1'b0};
- end
- end
-
- S_TRX_DATA: begin
- if (tx_baud_counter == BAUD_GEN_VALUE) begin
- tx_baud_counter <= 7'd0;
- tx_bit_counter <= tx_bit_counter + 1'd1;
- tx_shifter <= {1'b1, tx_shifter[9:1]};
- if (tx_bit_counter == 4'd9) begin
- tx_state <= S_TRX_IDLE;
- end
- end
- end
-
- default: begin
- tx_state <= S_TRX_IDLE;
- tx_shifter <= 10'h3FF;
- end
- endcase
- end
- end
-
-
- // RX path
-
- logic [6:0] rx_baud_counter;
- logic [3:0] rx_bit_counter;
- logic [7:0] rx_shifter;
- logic [1:0] rxd_ff;
-
- always_ff @(posedge sys.clk) begin
- rx_baud_counter <= rx_baud_counter + 1'd1;
- rxd_ff <= {rxd_ff[0], uart_rxd};
-
- if (bus.request && bus.wmask[0] && !bus.address[2]) begin
- rx_overrun <= bus.wdata[2];
- end
- if (bus.request && !bus.wmask[0] && bus.address[2]) begin
- rx_available <= 1'b0;
- end
-
- if (sys.reset) begin
- rx_state <= S_TRX_IDLE;
- rx_available <= 1'b0;
- rx_overrun <= 1'b0;
- end else begin
- case (rx_state)
- S_TRX_IDLE: begin
- if (!rxd_ff[1]) begin
- rx_state <= S_TRX_SAMPLING_OFFSET;
- rx_baud_counter <= 7'd0;
- rx_bit_counter <= 4'd0;
- end
- end
-
- S_TRX_SAMPLING_OFFSET: begin
- if (rx_baud_counter == (BAUD_GEN_VALUE / 2)) begin
- rx_state <= S_TRX_DATA;
- rx_baud_counter <= 7'd0;
- end
- end
-
- S_TRX_DATA: begin
- if (rx_baud_counter == BAUD_GEN_VALUE) begin
- rx_baud_counter <= 7'd0;
- rx_bit_counter <= rx_bit_counter + 1'd1;
- rx_shifter <= {rxd_ff[1], rx_shifter[7:1]};
- if (rx_bit_counter == 4'd8) begin
- rx_state <= S_TRX_IDLE;
- if (rxd_ff[1]) begin
- rx_data <= rx_shifter[7:0];
- rx_available <= 1'b1;
- rx_overrun <= rx_available;
- end
- end
- end
- end
-
- default: begin
- rx_state <= S_TRX_IDLE;
- rx_available <= 1'b0;
- rx_overrun <= 1'b0;
- end
- endcase
- end
- end
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_usb.sv b/fw/rtl/cpu/cpu_usb.sv
deleted file mode 100644
index f832483..0000000
--- a/fw/rtl/cpu/cpu_usb.sv
+++ /dev/null
@@ -1,126 +0,0 @@
-module cpu_usb (
- if_system sys,
- if_cpu_bus bus,
- if_memory_dma dma,
-
- output usb_clk,
- output usb_cs,
- input usb_miso,
- inout [7:0] usb_miosi
-);
-
- logic rx_flush;
- logic tx_flush;
- logic usb_enable;
- logic reset_pending;
- logic reset_ack;
- logic write_buffer_flush;
-
- typedef enum bit [1:0] {
- R_SCR,
- R_DATA,
- R_ADDR,
- R_LEN
- } e_reg_id;
-
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- if (bus.request) begin
- bus.ack <= 1'b1;
- end
- end
-
- always_comb begin
- bus.rdata = 32'd0;
- if (bus.ack) begin
- case (bus.address[3:2])
- R_SCR: bus.rdata = {
- 23'd0,
- dma.busy,
- 1'b0,
- reset_pending,
- 1'b0,
- usb_enable,
- 2'b00,
- ~dma.tx_full,
- ~dma.rx_empty
- };
- R_DATA: bus.rdata = {24'd0, dma.rx_rdata};
- default: bus.rdata = 32'd0;
- endcase
- end
- end
-
- always_ff @(posedge sys.clk) begin
- dma.start <= 1'b0;
- dma.stop <= 1'b0;
- dma.cpu_rx_read <= 1'b0;
- dma.cpu_tx_write <= 1'b0;
- rx_flush <= 1'b0;
- tx_flush <= 1'b0;
- reset_ack <= 1'b0;
- write_buffer_flush <= 1'b0;
-
- if (sys.reset) begin
- usb_enable <= 1'b0;
- end else begin
- if (bus.request) begin
- case (bus.address[3:2])
- R_SCR: if (&bus.wmask) begin
- {dma.direction, dma.stop, dma.start} <= bus.wdata[11:9];
- reset_ack <= bus.wdata[7];
- {write_buffer_flush, usb_enable, tx_flush, rx_flush} <= bus.wdata[5:2];
- end
-
- R_DATA: if (bus.wmask == 4'b0000) begin
- dma.cpu_rx_read <= 1'b1;
- end else if (bus.wmask == 4'b0001) begin
- dma.cpu_tx_write <= 1'b1;
- dma.cpu_tx_wdata <= bus.wdata[7:0];
- end
-
- R_ADDR: if (&bus.wmask) begin
- dma.starting_address <= bus.wdata;
- end
-
- R_LEN: if (&bus.wmask) begin
- dma.transfer_length <= bus.wdata;
- end
- endcase
- end
- end
- end
-
- memory_dma usb_memory_dma_inst (
- .clk(sys.clk),
- .reset(~usb_enable),
- .dma(dma)
- );
-
- usb_ft1248 usb_ft1248_inst (
- .clk(sys.clk),
- .reset(~usb_enable),
-
- .usb_clk(usb_clk),
- .usb_cs(usb_cs),
- .usb_miso(usb_miso),
- .usb_miosi(usb_miosi),
-
- .reset_pending(reset_pending),
- .reset_ack(reset_ack),
- .write_buffer_flush(write_buffer_flush),
-
- .rx_flush(rx_flush),
- .rx_empty(dma.rx_empty),
- .rx_almost_empty(dma.rx_almost_empty),
- .rx_read(dma.rx_read),
- .rx_rdata(dma.rx_rdata),
-
- .tx_flush(tx_flush),
- .tx_full(dma.tx_full),
- .tx_almost_full(dma.tx_almost_full),
- .tx_write(dma.tx_write),
- .tx_wdata(dma.tx_wdata)
- );
-
-endmodule
diff --git a/fw/rtl/cpu/cpu_wrapper.sv b/fw/rtl/cpu/cpu_wrapper.sv
deleted file mode 100644
index e248db0..0000000
--- a/fw/rtl/cpu/cpu_wrapper.sv
+++ /dev/null
@@ -1,85 +0,0 @@
-module cpu_wrapper (
- if_system.sys sys,
- if_cpu_bus.cpu bus
-);
-
- typedef enum bit [0:0] {
- S_IDLE,
- S_WAITING
- } e_bus_state;
-
- e_bus_state state;
-
- logic mem_la_read;
- logic mem_la_write;
-
- always_ff @(posedge sys.clk) begin
- bus.request <= 1'b0;
- if (sys.reset) begin
- state <= S_IDLE;
- end else begin
- if (state == S_IDLE && (mem_la_read || mem_la_write)) begin
- state <= S_WAITING;
- bus.request <= 1'b1;
- end
- if (state == S_WAITING && bus.ack) begin
- state <= S_IDLE;
- end
- end
- end
-
- logic trap;
- logic mem_valid;
- logic mem_instr;
- logic [31:0] mem_la_addr;
- logic [31:0] mem_la_wdata;
- logic [3:0] mem_la_wstrb;
- logic pcpi_valid;
- logic [31:0] pcpi_insn;
- logic [31:0] pcpi_rs1;
- logic [31:0] pcpi_rs2;
- logic [31:0] eoi;
- logic trace_valid;
- logic [35:0] trace_data;
-
- picorv32 #(
- .ENABLE_COUNTERS(0),
- .ENABLE_COUNTERS64(0),
- .TWO_STAGE_SHIFT(0),
- .TWO_CYCLE_COMPARE(1),
- .TWO_CYCLE_ALU(1),
- .CATCH_MISALIGN(0),
- .CATCH_ILLINSN(0),
- .PROGADDR_RESET(32'h0001_0000)
- ) cpu_inst (
- .clk(sys.clk),
- .resetn(~sys.reset),
- .mem_addr(bus.address),
- .mem_wdata(bus.wdata),
- .mem_wstrb(bus.wmask),
- .mem_ready(bus.ack),
- .mem_rdata(bus.rdata),
- .mem_la_read(mem_la_read),
- .mem_la_write(mem_la_write),
-
- .trap(trap),
- .mem_valid(mem_valid),
- .mem_instr(mem_instr),
- .mem_la_addr(mem_la_addr),
- .mem_la_wdata(mem_la_wdata),
- .mem_la_wstrb(mem_la_wstrb),
- .pcpi_valid(pcpi_valid),
- .pcpi_insn(pcpi_insn),
- .pcpi_rs1(pcpi_rs1),
- .pcpi_rs2(pcpi_rs2),
- .pcpi_wr(1'b0),
- .pcpi_rd(32'd0),
- .pcpi_wait(1'b0),
- .pcpi_ready(1'b0),
- .irq(32'd0),
- .eoi(eoi),
- .trace_valid(trace_valid),
- .trace_data(trace_data)
- );
-
-endmodule
diff --git a/fw/rtl/fifo/fifo_bus.sv b/fw/rtl/fifo/fifo_bus.sv
new file mode 100644
index 0000000..80ca607
--- /dev/null
+++ b/fw/rtl/fifo/fifo_bus.sv
@@ -0,0 +1,37 @@
+interface fifo_bus ();
+
+ logic rx_empty;
+ logic rx_almost_empty;
+ logic rx_read;
+ logic [7:0] rx_rdata;
+
+ logic tx_full;
+ logic tx_almost_full;
+ logic tx_write;
+ logic [7:0] tx_wdata;
+
+ modport controller (
+ input rx_empty,
+ input rx_almost_empty,
+ output rx_read,
+ input rx_rdata,
+
+ input tx_full,
+ input tx_almost_full,
+ output tx_write,
+ output tx_wdata
+ );
+
+ modport fifo (
+ output rx_empty,
+ output rx_almost_empty,
+ input rx_read,
+ output rx_rdata,
+
+ output tx_full,
+ output tx_almost_full,
+ input tx_write,
+ input tx_wdata
+ );
+
+endinterface
diff --git a/fw/rtl/fifo/fifo_junction.sv b/fw/rtl/fifo/fifo_junction.sv
new file mode 100644
index 0000000..cd3ffdc
--- /dev/null
+++ b/fw/rtl/fifo/fifo_junction.sv
@@ -0,0 +1,26 @@
+module fifo_junction (
+ fifo_bus.controller dev_bus,
+
+ fifo_bus.fifo cfg_bus,
+ fifo_bus.fifo dma_bus
+);
+
+ always_comb begin
+ dev_bus.rx_read = cfg_bus.rx_read || dma_bus.rx_read;
+ dev_bus.tx_write = cfg_bus.tx_write || dma_bus.tx_write;
+ dev_bus.tx_wdata = cfg_bus.tx_write ? cfg_bus.tx_wdata : dma_bus.tx_wdata;
+
+ cfg_bus.rx_empty = dev_bus.rx_empty;
+ cfg_bus.rx_almost_empty = dev_bus.rx_almost_empty;
+ cfg_bus.rx_rdata = dev_bus.rx_rdata;
+ cfg_bus.tx_full = dev_bus.tx_full;
+ cfg_bus.tx_almost_full = dev_bus.tx_almost_full;
+
+ dma_bus.rx_empty = dev_bus.rx_empty;
+ dma_bus.rx_almost_empty = dev_bus.rx_almost_empty;
+ dma_bus.rx_rdata = dev_bus.rx_rdata;
+ dma_bus.tx_full = dev_bus.tx_full;
+ dma_bus.tx_almost_full = dev_bus.tx_almost_full;
+ end
+
+endmodule
diff --git a/fw/rtl/intel/fifo/intel_fifo_8.qip b/fw/rtl/intel/fifo/intel_fifo_8.qip
deleted file mode 100644
index f252a4d..0000000
--- a/fw/rtl/intel/fifo/intel_fifo_8.qip
+++ /dev/null
@@ -1,4 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "FIFO"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_fifo_8.v"]
diff --git a/fw/rtl/intel/fifo/intel_fifo_8.v b/fw/rtl/intel/fifo/intel_fifo_8.v
deleted file mode 100644
index bf49b7b..0000000
--- a/fw/rtl/intel/fifo/intel_fifo_8.v
+++ /dev/null
@@ -1,179 +0,0 @@
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: scfifo
-
-// ============================================================
-// File Name: intel_fifo_8.v
-// Megafunction Name(s):
-// scfifo
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2021 Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
-//and other software and tools, and any partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors. Please
-//refer to the applicable agreement for further details, at
-//https://fpgasoftware.intel.com/eula.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module intel_fifo_8 (
- clock,
- data,
- rdreq,
- sclr,
- wrreq,
- almost_empty,
- almost_full,
- empty,
- full,
- q);
-
- input clock;
- input [7:0] data;
- input rdreq;
- input sclr;
- input wrreq;
- output almost_empty;
- output almost_full;
- output empty;
- output full;
- output [7:0] q;
-
- wire sub_wire0;
- wire sub_wire1;
- wire sub_wire2;
- wire sub_wire3;
- wire [7:0] sub_wire4;
- wire almost_empty = sub_wire0;
- wire almost_full = sub_wire1;
- wire empty = sub_wire2;
- wire full = sub_wire3;
- wire [7:0] q = sub_wire4[7:0];
-
- scfifo scfifo_component (
- .clock (clock),
- .data (data),
- .rdreq (rdreq),
- .sclr (sclr),
- .wrreq (wrreq),
- .almost_empty (sub_wire0),
- .almost_full (sub_wire1),
- .empty (sub_wire2),
- .full (sub_wire3),
- .q (sub_wire4),
- .aclr (),
- .eccstatus (),
- .usedw ());
- defparam
- scfifo_component.add_ram_output_register = "OFF",
- scfifo_component.almost_empty_value = 2,
- scfifo_component.almost_full_value = 1023,
- scfifo_component.intended_device_family = "MAX 10",
- scfifo_component.lpm_numwords = 1024,
- scfifo_component.lpm_showahead = "ON",
- scfifo_component.lpm_type = "scfifo",
- scfifo_component.lpm_width = 8,
- scfifo_component.lpm_widthu = 10,
- scfifo_component.overflow_checking = "ON",
- scfifo_component.underflow_checking = "ON",
- scfifo_component.use_eab = "ON";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "2"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "1023"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Depth NUMERIC "1024"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UsedW NUMERIC "0"
-// Retrieval info: PRIVATE: Width NUMERIC "8"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "8"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "2"
-// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "1023"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL "almost_empty"
-// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
-// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/fw/rtl/mcu/mcu_spi.sv b/fw/rtl/mcu/mcu_spi.sv
new file mode 100644
index 0000000..9cebb5f
--- /dev/null
+++ b/fw/rtl/mcu/mcu_spi.sv
@@ -0,0 +1,92 @@
+module mcu_spi (
+ input clk,
+ input reset,
+
+ output logic frame_start,
+ output logic data_ready,
+ output logic [7:0] rx_data,
+ input [7:0] tx_data,
+
+ input mcu_clk,
+ input mcu_cs,
+ input mcu_mosi,
+ output logic mcu_miso
+);
+
+ logic [2:0] mcu_clk_ff;
+ logic [2:0] mcu_cs_ff;
+
+ always_ff @(posedge clk) begin
+ mcu_clk_ff <= {mcu_clk_ff[1:0], mcu_clk};
+ mcu_cs_ff <= {mcu_cs_ff[1:0], mcu_cs};
+ end
+
+ logic mcu_clk_falling;
+ logic mcu_clk_rising;
+ logic mcu_cs_falling;
+ logic mcu_cs_rising;
+
+ always_comb begin
+ mcu_clk_falling = mcu_clk_ff[2] && !mcu_clk_ff[1];
+ mcu_clk_rising = !mcu_clk_ff[2] && mcu_clk_ff[1];
+ mcu_cs_falling = mcu_cs_ff[2] && !mcu_cs_ff[1];
+ mcu_cs_rising = !mcu_cs_ff[2] && mcu_cs_ff[1];
+ end
+
+ logic mcu_dq_in;
+ logic mcu_dq_out;
+ logic mcu_miso_out;
+
+ assign mcu_miso = mcu_cs_ff[1] ? 1'bZ : mcu_miso_out;
+
+ always_ff @(posedge clk) begin
+ mcu_dq_in <= mcu_mosi;
+ mcu_miso_out <= mcu_dq_out;
+ end
+
+ logic [7:0] spi_tx_shift;
+
+ assign mcu_dq_out = spi_tx_shift[7];
+
+ logic spi_enabled;
+ logic [2:0] spi_bit_counter;
+
+ always_ff @(posedge clk) begin
+ frame_start <= 1'b0;
+ data_ready <= 1'b0;
+
+ if (reset) begin
+ spi_enabled <= 1'b0;
+ spi_bit_counter <= 3'd0;
+ end else begin
+ if (mcu_cs_falling) begin
+ spi_enabled <= 1'b1;
+ spi_bit_counter <= 3'd0;
+ frame_start <= 1'b1;
+ end
+
+ if (mcu_cs_rising) begin
+ spi_enabled <= 1'b0;
+ end
+
+ if (spi_enabled) begin
+ if (mcu_clk_rising) begin
+ if (spi_bit_counter == 3'd0) begin
+ spi_tx_shift <= tx_data;
+ end else begin
+ spi_tx_shift <= {spi_tx_shift[6:0], 1'b0};
+ end
+ end
+
+ if (mcu_clk_falling) begin
+ spi_bit_counter <= spi_bit_counter + 1'd1;
+ rx_data <= {rx_data[6:0], mcu_dq_in};
+ if (spi_bit_counter == 3'd7) begin
+ data_ready <= 1'b1;
+ end
+ end
+ end
+ end
+ end
+
+endmodule
diff --git a/fw/rtl/mcu/mcu_top.sv b/fw/rtl/mcu/mcu_top.sv
new file mode 100644
index 0000000..92c75ca
--- /dev/null
+++ b/fw/rtl/mcu/mcu_top.sv
@@ -0,0 +1,753 @@
+module mcu_top (
+ input clk,
+ input reset,
+
+ usb_scb.controller usb_scb,
+ dma_scb.controller usb_dma_scb,
+ sd_scb.controller sd_scb,
+ dma_scb.controller sd_dma_scb,
+ n64_scb.controller n64_scb,
+ flash_scb.controller flash_scb,
+
+ fifo_bus.controller fifo_bus,
+ mem_bus.controller mem_bus,
+
+ input sd_det,
+ input button,
+
+ output logic mcu_int,
+ input mcu_clk,
+ input mcu_cs,
+ input mcu_mosi,
+ output mcu_miso
+);
+
+ // Button input synchronization
+
+ logic [2:0] sd_det_ff;
+ logic [2:0] button_ff;
+
+ always_ff @(posedge clk) begin
+ sd_det_ff <= {sd_det_ff[1:0], sd_det};
+ button_ff <= {button_ff[1:0], button};
+ end
+
+
+ // MCU <-> FPGA transport
+
+ logic frame_start;
+ logic data_ready;
+ logic [7:0] rdata;
+ logic [7:0] wdata;
+
+ mcu_spi mcu_spi_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .frame_start(frame_start),
+ .data_ready(data_ready),
+ .rx_data(rdata),
+ .tx_data(wdata),
+
+ .mcu_clk(mcu_clk),
+ .mcu_cs(mcu_cs),
+ .mcu_mosi(mcu_mosi),
+ .mcu_miso(mcu_miso)
+ );
+
+
+ // Protocol controller
+
+ const bit [7:0] FPGA_ID = 8'h64;
+
+ typedef enum bit [1:0] {
+ PHASE_CMD,
+ PHASE_ADDRESS,
+ PHASE_DATA,
+ PHASE_NOP
+ } phase_e;
+
+ typedef enum bit [7:0] {
+ CMD_IDENTIFY,
+ CMD_REG_READ,
+ CMD_REG_WRITE,
+ CMD_MEM_READ,
+ CMD_MEM_WRITE,
+ CMD_USB_STATUS,
+ CMD_USB_READ,
+ CMD_USB_WRITE,
+ CMD_FLASHRAM_READ,
+ CMD_EEPROM_READ,
+ CMD_EEPROM_WRITE
+ } cmd_e;
+
+ phase_e phase;
+ cmd_e cmd;
+
+ logic [1:0] counter;
+ logic [7:0] address;
+
+ logic reg_read;
+ logic reg_write;
+ logic [31:0] reg_rdata;
+ logic [31:0] reg_wdata;
+
+ logic mem_read;
+ logic mem_write;
+ logic [15:0] mem_rdata;
+ logic [15:0] mem_wdata;
+ logic mem_word_select;
+
+ always_ff @(posedge clk) begin
+ fifo_bus.rx_read <= 1'b0;
+ fifo_bus.tx_write <= 1'b0;
+
+ n64_scb.eeprom_write <= 1'b0;
+
+ reg_read <= 1'b0;
+ reg_write <= 1'b0;
+
+ mem_read <= 1'b0;
+ mem_write <= 1'b0;
+
+ if (reset) begin
+ end else begin
+ if (frame_start) begin
+ counter <= 2'd0;
+ phase <= PHASE_CMD;
+ end
+
+ if (reg_read || reg_write || (mem_word_select && (mem_read || mem_write))) begin
+ address <= address + 1'd1;
+ end
+
+ if (n64_scb.eeprom_write) begin
+ n64_scb.eeprom_address <= n64_scb.eeprom_address + 1'd1;
+ end
+
+ if (data_ready) begin
+ case (phase)
+ PHASE_CMD: begin
+ cmd <= cmd_e'(rdata);
+ phase <= PHASE_ADDRESS;
+
+ if (rdata == CMD_USB_STATUS) begin
+ phase <= PHASE_NOP;
+ end
+
+ if (rdata == CMD_USB_READ) begin
+ fifo_bus.rx_read <= 1'b1;
+ phase <= PHASE_DATA;
+ end
+
+ if (rdata == CMD_USB_WRITE) begin
+ phase <= PHASE_DATA;
+ end
+ end
+
+ PHASE_ADDRESS: begin
+ address <= rdata;
+ phase <= PHASE_DATA;
+
+ if (cmd == CMD_REG_READ) begin
+ reg_read <= 1'b1;
+ end
+
+ if (cmd == CMD_MEM_READ) begin
+ mem_read <= 1'b1;
+ mem_word_select <= 1'b0;
+ end
+
+ if (cmd == CMD_FLASHRAM_READ) begin
+ n64_scb.flashram_buffer_address <= rdata[6:1];
+ counter <= {1'b0, rdata[0]};
+ end
+
+ if ((cmd == CMD_EEPROM_READ) || (cmd == CMD_EEPROM_WRITE)) begin
+ n64_scb.eeprom_address <= {rdata, 3'd0};
+ end
+ end
+
+ PHASE_DATA: begin
+ counter <= counter + 1'd1;
+
+ if (cmd == CMD_REG_READ) begin
+ if (counter == 2'd3) begin
+ reg_read <= 1'd1;
+ end
+ end
+
+ if (cmd == CMD_REG_WRITE) begin
+ case (counter)
+ 2'd0: reg_wdata[7:0] <= rdata;
+ 2'd1: reg_wdata[15:8] <= rdata;
+ 2'd2: reg_wdata[23:16] <= rdata;
+ 2'd3: reg_wdata[31:24] <= rdata;
+ endcase
+ if (counter == 2'd3) begin
+ reg_write <= 1'd1;
+ end
+ end
+
+ if (cmd == CMD_MEM_READ) begin
+ if (counter[0]) begin
+ mem_read <= 1'b1;
+ mem_word_select <= ~mem_word_select;
+ end
+ end
+
+ if (cmd == CMD_MEM_WRITE) begin
+ case (counter[0])
+ 1'd0: mem_wdata[15:8] <= rdata;
+ 1'd1: mem_wdata[7:0] <= rdata;
+ endcase
+ if (counter[0]) begin
+ mem_write <= 1'b1;
+ mem_word_select <= counter[1];
+ end
+ end
+
+ if (cmd == CMD_USB_READ) begin
+ phase <= PHASE_NOP;
+ end
+
+ if (cmd == CMD_USB_WRITE) begin
+ fifo_bus.tx_write <= 1'b1;
+ fifo_bus.tx_wdata <= rdata;
+ phase <= PHASE_NOP;
+ end
+
+ if (cmd == CMD_FLASHRAM_READ) begin
+ if (counter[0]) begin
+ n64_scb.flashram_buffer_address <= n64_scb.flashram_buffer_address + 1'd1;
+ end
+ end
+
+ if (cmd == CMD_EEPROM_READ) begin
+ n64_scb.eeprom_address <= n64_scb.eeprom_address + 1'd1;
+ end
+
+ if (cmd == CMD_EEPROM_WRITE) begin
+ n64_scb.eeprom_write <= 1'b1;
+ n64_scb.eeprom_wdata <= rdata;
+ end
+ end
+
+ PHASE_NOP: begin end
+ endcase
+ end
+ end
+ end
+
+ always_comb begin
+ wdata = 8'h00;
+
+ case (cmd)
+ CMD_IDENTIFY: begin
+ wdata = FPGA_ID;
+ end
+
+ CMD_REG_READ: begin
+ case (counter)
+ 2'd0: wdata = reg_rdata[7:0];
+ 2'd1: wdata = reg_rdata[15:8];
+ 2'd2: wdata = reg_rdata[23:16];
+ 2'd3: wdata = reg_rdata[31:24];
+ endcase
+ end
+
+ CMD_REG_WRITE: begin
+ wdata = 8'h00;
+ end
+
+ CMD_MEM_READ: begin
+ case (counter[0])
+ 1'd0: wdata = mem_rdata[15:8];
+ 1'd1: wdata = mem_rdata[7:0];
+ endcase
+ end
+
+ CMD_MEM_WRITE: begin
+ wdata = 8'h00;
+ end
+
+ CMD_USB_STATUS: begin
+ wdata = {6'd0, ~fifo_bus.tx_full, ~fifo_bus.rx_empty};
+ end
+
+ CMD_USB_READ: begin
+ wdata = fifo_bus.rx_rdata;
+ end
+
+ CMD_USB_WRITE: begin
+ wdata = 8'h00;
+ end
+
+ CMD_FLASHRAM_READ: begin
+ case (counter[0])
+ 1'd0: wdata = n64_scb.flashram_buffer_rdata[15:8];
+ 1'd1: wdata = n64_scb.flashram_buffer_rdata[7:0];
+ endcase
+ end
+
+ CMD_EEPROM_READ: begin
+ wdata = n64_scb.eeprom_rdata;
+ end
+
+ CMD_EEPROM_WRITE: begin
+ wdata = 8'h00;
+ end
+ endcase
+ end
+
+
+ // Mem bus controller
+
+ logic [15:0] mem_buffer [0:511];
+
+ logic mem_start;
+ logic mem_stop;
+ logic mem_direction;
+ logic [8:0] mem_length;
+ logic [31:0] mem_address;
+
+ logic mem_busy;
+ logic mem_stop_pending;
+ logic [8:0] mem_counter;
+
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ mem_busy <= 1'b0;
+ mem_stop_pending <= 1'b0;
+ mem_bus.request <= 1'b0;
+ end else begin
+ if (mem_read) begin
+ mem_rdata <= mem_buffer[{address, mem_word_select}];
+ end
+
+ if (mem_write) begin
+ mem_buffer[{address, mem_word_select}] <= mem_wdata;
+ end
+
+ if (mem_stop) begin
+ mem_stop_pending <= mem_busy;
+ end else if (mem_start && !mem_busy) begin
+ mem_bus.write <= mem_direction;
+ mem_bus.address <= mem_address;
+ mem_busy <= 1'b1;
+ mem_counter <= 9'd0;
+ end
+
+ if (mem_busy) begin
+ if (!mem_bus.request) begin
+ mem_bus.request <= 1'b1;
+ mem_bus.wdata <= mem_buffer[mem_counter];
+ end
+
+ if (mem_bus.ack) begin
+ mem_bus.request <= 1'b0;
+ mem_bus.address <= mem_bus.address + 2'd2;
+ mem_counter <= mem_counter + 1'd1;
+ if (!mem_bus.write) begin
+ mem_buffer[mem_counter] <= mem_bus.rdata;
+ end
+ if ((mem_counter == mem_length) || mem_stop_pending) begin
+ mem_busy <= 1'b0;
+ mem_stop_pending <= 1'b0;
+ end
+ end
+ end
+ end
+ end
+
+ always_comb begin
+ mem_bus.wmask = 2'b11;
+ end
+
+
+ // Register list
+
+ typedef enum bit [7:0] {
+ REG_STATUS,
+ REG_MEM_ADDRESS,
+ REG_MEM_SCR,
+ REG_USB_SCR,
+ REG_USB_DMA_ADDRESS,
+ REG_USB_DMA_LENGTH,
+ REG_USB_DMA_SCR,
+ REG_CFG_SCR,
+ REG_CFG_DATA_0,
+ REG_CFG_DATA_1,
+ REG_CFG_CMD,
+ REG_CFG_VERSION,
+ REG_FLASHRAM_SCR,
+ REG_FLASH_SCR,
+ REG_RTC_SCR,
+ REG_RTC_TIME_0,
+ REG_RTC_TIME_1,
+ REG_SD_SCR,
+ REG_SD_ARG,
+ REG_SD_CMD,
+ REG_SD_RSP_0,
+ REG_SD_RSP_1,
+ REG_SD_RSP_2,
+ REG_SD_RSP_3,
+ REG_SD_DAT,
+ REG_SD_DMA_ADDRESS,
+ REG_SD_DMA_LENGTH,
+ REG_SD_DMA_SCR
+ } reg_address_e;
+
+ logic bootloader_skip;
+
+ assign n64_scb.cfg_version = 32'h53437632;
+
+
+ // Register read logic
+
+ always_ff @(posedge clk) begin
+ if (reg_read) begin
+ reg_rdata <= 32'd0;
+
+ case (address)
+ REG_STATUS: begin
+ reg_rdata <= {
+ 24'd0,
+ sd_det_ff[2],
+ ~fifo_bus.tx_full,
+ ~fifo_bus.rx_empty,
+ n64_scb.flashram_pending,
+ n64_scb.cfg_pending,
+ usb_dma_scb.busy,
+ usb_scb.reset_pending,
+ button_ff[2]
+ };
+ end
+
+ REG_MEM_ADDRESS: begin
+ reg_rdata <= mem_address;
+ end
+
+ REG_MEM_SCR: begin
+ reg_rdata <= {
+ 28'd0,
+ mem_busy,
+ 3'b000
+ };
+ end
+
+ REG_USB_SCR: begin
+ reg_rdata <= {
+ 28'd0,
+ usb_scb.reset_pending,
+ ~fifo_bus.tx_full,
+ ~fifo_bus.rx_empty,
+ 1'b0
+ };
+ end
+
+ REG_USB_DMA_ADDRESS: begin
+ reg_rdata <= {
+ 5'd0,
+ usb_dma_scb.starting_address
+ };
+ end
+
+ REG_USB_DMA_LENGTH: begin
+ reg_rdata <= {
+ 5'd0,
+ usb_dma_scb.transfer_length
+ };
+ end
+
+ REG_USB_DMA_SCR: begin
+ reg_rdata <= {
+ 28'd0,
+ usb_dma_scb.busy,
+ usb_dma_scb.direction,
+ 2'b00
+ };
+ end
+
+ REG_CFG_SCR: begin
+ reg_rdata <= {
+ 22'd0,
+ n64_scb.eeprom_16k_mode,
+ n64_scb.eeprom_enabled,
+ n64_scb.dd_enabled,
+ n64_scb.flashram_enabled,
+ n64_scb.sram_banked,
+ n64_scb.sram_enabled,
+ n64_scb.rom_shadow_enabled,
+ n64_scb.rom_write_enabled,
+ bootloader_skip,
+ n64_scb.bootloader_enabled
+ };
+ end
+
+ REG_CFG_DATA_0: begin
+ reg_rdata <= n64_scb.cfg_rdata[0];
+ end
+
+ REG_CFG_DATA_1: begin
+ reg_rdata <= n64_scb.cfg_rdata[1];
+ end
+
+ REG_CFG_CMD: begin
+ reg_rdata <= {
+ 24'd0,
+ n64_scb.cfg_cmd
+ };
+ end
+
+ REG_CFG_VERSION: begin
+ reg_rdata <= n64_scb.cfg_version;
+ end
+
+ REG_FLASHRAM_SCR: begin
+ reg_rdata <= {
+ 18'd0,
+ n64_scb.flashram_write_or_erase,
+ n64_scb.flashram_sector_or_all,
+ n64_scb.flashram_sector,
+ n64_scb.flashram_pending,
+ 1'b0
+ };
+ end
+
+ REG_FLASH_SCR: begin
+ reg_rdata <= {
+ 31'd0,
+ flash_scb.erase_pending
+ };
+ end
+
+ REG_RTC_SCR: begin
+ reg_rdata <= {
+ 31'd0,
+ n64_scb.rtc_pending
+ };
+ end
+
+ REG_RTC_TIME_0: begin
+ reg_rdata <= {
+ 5'd0, n64_scb.rtc_rdata[28:26],
+ 2'd0, n64_scb.rtc_rdata[19:14],
+ 1'd0, n64_scb.rtc_rdata[13:7],
+ 1'd0, n64_scb.rtc_rdata[6:0]
+ };
+ end
+
+ REG_RTC_TIME_1: begin
+ reg_rdata <= {
+ 8'd0,
+ n64_scb.rtc_rdata[41:34],
+ 3'd0, n64_scb.rtc_rdata[33:29],
+ 2'd0, n64_scb.rtc_rdata[25:20]
+ };
+ end
+
+ REG_SD_SCR: begin
+ reg_rdata <= {
+ 30'd0,
+ sd_scb.clock_mode
+ };
+ end
+
+ REG_SD_DMA_ADDRESS: begin
+ reg_rdata <= {
+ 5'd0,
+ sd_dma_scb.starting_address
+ };
+ end
+
+ REG_SD_DMA_LENGTH: begin
+ reg_rdata <= {
+ 5'd0,
+ sd_dma_scb.transfer_length
+ };
+ end
+
+ REG_SD_DMA_SCR: begin
+ reg_rdata <= {
+ 28'd0,
+ sd_dma_scb.busy,
+ sd_dma_scb.direction,
+ 2'b00
+ };
+ end
+ endcase
+ end
+ end
+
+
+ // Register write logic
+
+ logic [31:0] reg_buffer;
+
+ always_ff @(posedge clk) begin
+ mem_start <= 1'b0;
+ mem_stop <= 1'b0;
+
+ usb_scb.write_buffer_flush <= 1'b0;
+ usb_scb.reset_ack <= 1'b0;
+ usb_scb.fifo_flush <= 1'b0;
+
+ usb_dma_scb.start <= 1'b0;
+ usb_dma_scb.stop <= 1'b0;
+
+ sd_dma_scb.start <= 1'b0;
+ sd_dma_scb.stop <= 1'b0;
+
+ n64_scb.cfg_done <= 1'b0;
+ n64_scb.cfg_irq <= 1'b0;
+
+ n64_scb.flashram_done <= 1'b0;
+
+ n64_scb.rtc_done <= 1'b0;
+
+ if (n64_scb.n64_nmi) begin
+ n64_scb.bootloader_enabled <= !bootloader_skip;
+ end
+
+ if (flash_scb.erase_done) begin
+ flash_scb.erase_pending <= 1'b0;
+ end
+
+ if (reset) begin
+ mcu_int <= 1'b0;
+ sd_scb.clock_mode <= 2'd0;
+ n64_scb.eeprom_16k_mode <= 1'b0;
+ n64_scb.eeprom_enabled <= 1'b0;
+ n64_scb.dd_enabled <= 1'b0;
+ n64_scb.flashram_enabled <= 1'b0;
+ n64_scb.sram_banked <= 1'b0;
+ n64_scb.sram_enabled <= 1'b0;
+ n64_scb.rom_shadow_enabled <= 1'b0;
+ n64_scb.rom_write_enabled <= 1'b0;
+ bootloader_skip <= 1'b0;
+ n64_scb.bootloader_enabled <= 1'b1;
+ flash_scb.erase_pending <= 1'b0;
+ end else if (reg_write) begin
+ case (address)
+ REG_STATUS: begin end
+
+ REG_MEM_ADDRESS: begin
+ mem_address <= reg_wdata;
+ end
+
+ REG_MEM_SCR: begin
+ {
+ mem_length,
+ mem_direction,
+ mem_stop,
+ mem_start
+ } <= {(reg_wdata[14:5] - 1'd1), reg_wdata[2:0]};
+ end
+
+ REG_USB_SCR: begin
+ {
+ usb_scb.write_buffer_flush,
+ usb_scb.reset_ack,
+ usb_scb.fifo_flush
+ } <= {reg_wdata[5:4], reg_wdata[0]};
+ end
+
+ REG_USB_DMA_ADDRESS: begin
+ usb_dma_scb.starting_address <= reg_wdata[26:0];
+ end
+
+ REG_USB_DMA_LENGTH: begin
+ usb_dma_scb.transfer_length <= reg_wdata[26:0];
+ end
+
+ REG_USB_DMA_SCR: begin
+ {
+ usb_dma_scb.direction,
+ usb_dma_scb.stop,
+ usb_dma_scb.start
+ } <= reg_wdata[2:0];
+ end
+
+ REG_CFG_SCR: begin
+ {
+ n64_scb.eeprom_16k_mode,
+ n64_scb.eeprom_enabled,
+ n64_scb.dd_enabled,
+ n64_scb.flashram_enabled,
+ n64_scb.sram_banked,
+ n64_scb.sram_enabled,
+ n64_scb.rom_shadow_enabled,
+ n64_scb.rom_write_enabled,
+ bootloader_skip,
+ n64_scb.bootloader_enabled
+ } <= reg_wdata[9:0];
+ end
+
+ REG_CFG_DATA_0: begin
+ n64_scb.cfg_wdata[0] <= reg_wdata;
+ end
+
+ REG_CFG_DATA_1: begin
+ n64_scb.cfg_wdata[1] <= reg_wdata;
+ end
+
+ REG_CFG_CMD: begin
+ {
+ n64_scb.cfg_irq,
+ n64_scb.cfg_error,
+ n64_scb.cfg_done
+ } <= reg_wdata[2:0];
+ end
+
+ REG_FLASHRAM_SCR: begin
+ n64_scb.flashram_done <= reg_wdata[0];
+ end
+
+ REG_FLASH_SCR: begin
+ flash_scb.erase_pending <= 1'b1;
+ flash_scb.erase_block <= reg_wdata[23:16];
+ end
+
+ REG_RTC_SCR: begin
+ n64_scb.rtc_done <= reg_wdata[1];
+ end
+
+ REG_RTC_TIME_0: begin
+ reg_buffer <= reg_wdata;
+ end
+
+ REG_RTC_TIME_1: begin
+ n64_scb.rtc_wdata[41:34] <= reg_wdata[23:16];
+ n64_scb.rtc_wdata[33:29] <= reg_wdata[12:8];
+ n64_scb.rtc_wdata[25:20] <= reg_wdata[5:0];
+ n64_scb.rtc_wdata[28:26] <= reg_buffer[26:24];
+ n64_scb.rtc_wdata[19:14] <= reg_buffer[21:16];
+ n64_scb.rtc_wdata[13:7] <= reg_buffer[14:8];
+ n64_scb.rtc_wdata[6:0] <= reg_buffer[6:0];
+ end
+
+ REG_SD_SCR: begin
+ sd_scb.clock_mode <= reg_wdata[1:0];
+ end
+
+ REG_SD_DMA_ADDRESS: begin
+ sd_dma_scb.starting_address <= reg_wdata[26:0];
+ end
+
+ REG_SD_DMA_LENGTH: begin
+ sd_dma_scb.transfer_length <= reg_wdata[26:0];
+ end
+
+ REG_SD_DMA_SCR: begin
+ {
+ sd_dma_scb.direction,
+ sd_dma_scb.stop,
+ sd_dma_scb.start
+ } <= reg_wdata[2:0];
+ end
+ endcase
+ end
+ end
+
+endmodule
diff --git a/fw/rtl/memory/mem_bus.sv b/fw/rtl/memory/mem_bus.sv
new file mode 100644
index 0000000..75e92f5
--- /dev/null
+++ b/fw/rtl/memory/mem_bus.sv
@@ -0,0 +1,31 @@
+interface mem_bus ();
+
+ logic request;
+ logic ack;
+ logic write;
+ logic [1:0] wmask;
+ logic [26:0] address;
+ logic [15:0] rdata;
+ logic [15:0] wdata;
+
+ modport controller (
+ output request,
+ input ack,
+ output write,
+ output wmask,
+ output address,
+ input rdata,
+ output wdata
+ );
+
+ modport memory (
+ input request,
+ output ack,
+ input write,
+ input wmask,
+ input address,
+ output rdata,
+ input wdata
+ );
+
+endinterface
diff --git a/fw/rtl/memory/memory_arbiter.sv b/fw/rtl/memory/memory_arbiter.sv
new file mode 100644
index 0000000..0b0453a
--- /dev/null
+++ b/fw/rtl/memory/memory_arbiter.sv
@@ -0,0 +1,159 @@
+module memory_arbiter (
+ input clk,
+ input reset,
+
+ mem_bus.memory n64_bus,
+ mem_bus.memory cfg_bus,
+ mem_bus.memory usb_dma_bus,
+ mem_bus.memory sd_dma_bus,
+
+ mem_bus.controller sdram_mem_bus,
+ mem_bus.controller flash_mem_bus
+);
+
+ typedef enum bit [1:0] {
+ SOURCE_N64,
+ SOURCE_CFG,
+ SOURCE_USB_DMA,
+ SOURCE_SD_DMA
+ } e_source_request;
+
+ logic n64_sdram_request;
+ logic cfg_sdram_request;
+ logic usb_dma_sdram_request;
+ logic sd_dma_sdram_request;
+
+ logic n64_flash_request;
+ logic cfg_flash_request;
+ logic usb_dma_flash_request;
+ logic sd_dma_flash_request;
+
+ assign n64_sdram_request = n64_bus.request && !n64_bus.address[26];
+ assign cfg_sdram_request = cfg_bus.request && !cfg_bus.address[26];
+ assign usb_dma_sdram_request = usb_dma_bus.request && !usb_dma_bus.address[26];
+ assign sd_dma_sdram_request = sd_dma_bus.request && !sd_dma_bus.address[26];
+
+ assign n64_flash_request = n64_bus.request && n64_bus.address[26];
+ assign cfg_flash_request = cfg_bus.request && cfg_bus.address[26];
+ assign usb_dma_flash_request = usb_dma_bus.request && usb_dma_bus.address[26];
+ assign sd_dma_flash_request = sd_dma_bus.request && sd_dma_bus.address[26];
+
+ e_source_request sdram_source_request;
+
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ sdram_mem_bus.request <= 1'b0;
+ end else begin
+ if (!sdram_mem_bus.request) begin
+ sdram_mem_bus.request <= (
+ n64_sdram_request ||
+ cfg_sdram_request ||
+ usb_dma_sdram_request ||
+ sd_dma_sdram_request
+ );
+
+ if (n64_sdram_request) begin
+ sdram_mem_bus.write <= n64_bus.write;
+ sdram_mem_bus.wmask <= n64_bus.wmask;
+ sdram_mem_bus.address <= n64_bus.address;
+ sdram_mem_bus.wdata <= n64_bus.wdata;
+ sdram_source_request <= SOURCE_N64;
+ end else if (cfg_sdram_request) begin
+ sdram_mem_bus.write <= cfg_bus.write;
+ sdram_mem_bus.wmask <= cfg_bus.wmask;
+ sdram_mem_bus.address <= cfg_bus.address;
+ sdram_mem_bus.wdata <= cfg_bus.wdata;
+ sdram_source_request <= SOURCE_CFG;
+ end else if (usb_dma_sdram_request) begin
+ sdram_mem_bus.write <= usb_dma_bus.write;
+ sdram_mem_bus.wmask <= usb_dma_bus.wmask;
+ sdram_mem_bus.address <= usb_dma_bus.address;
+ sdram_mem_bus.wdata <= usb_dma_bus.wdata;
+ sdram_source_request <= SOURCE_USB_DMA;
+ end else if (sd_dma_sdram_request) begin
+ sdram_mem_bus.write <= sd_dma_bus.write;
+ sdram_mem_bus.wmask <= sd_dma_bus.wmask;
+ sdram_mem_bus.address <= sd_dma_bus.address;
+ sdram_mem_bus.wdata <= sd_dma_bus.wdata;
+ sdram_source_request <= SOURCE_SD_DMA;
+ end
+ end
+
+ if (sdram_mem_bus.ack) begin
+ sdram_mem_bus.request <= 1'b0;
+ end
+ end
+ end
+
+ e_source_request flash_source_request;
+
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ flash_mem_bus.request <= 1'b0;
+ end else begin
+ if (!flash_mem_bus.request) begin
+ flash_mem_bus.request <= (
+ n64_flash_request ||
+ cfg_flash_request ||
+ usb_dma_flash_request ||
+ sd_dma_flash_request
+ );
+
+ if (n64_flash_request) begin
+ flash_mem_bus.write <= n64_bus.write;
+ flash_mem_bus.wmask <= n64_bus.wmask;
+ flash_mem_bus.address <= n64_bus.address;
+ flash_mem_bus.wdata <= n64_bus.wdata;
+ flash_source_request <= SOURCE_N64;
+ end else if (cfg_flash_request) begin
+ flash_mem_bus.write <= cfg_bus.write;
+ flash_mem_bus.wmask <= cfg_bus.wmask;
+ flash_mem_bus.address <= cfg_bus.address;
+ flash_mem_bus.wdata <= cfg_bus.wdata;
+ flash_source_request <= SOURCE_CFG;
+ end else if (usb_dma_flash_request) begin
+ flash_mem_bus.write <= usb_dma_bus.write;
+ flash_mem_bus.wmask <= usb_dma_bus.wmask;
+ flash_mem_bus.address <= usb_dma_bus.address;
+ flash_mem_bus.wdata <= usb_dma_bus.wdata;
+ flash_source_request <= SOURCE_USB_DMA;
+ end else if (sd_dma_flash_request) begin
+ flash_mem_bus.write <= sd_dma_bus.write;
+ flash_mem_bus.wmask <= sd_dma_bus.wmask;
+ flash_mem_bus.address <= sd_dma_bus.address;
+ flash_mem_bus.wdata <= sd_dma_bus.wdata;
+ flash_source_request <= SOURCE_SD_DMA;
+ end
+ end
+
+ if (flash_mem_bus.ack) begin
+ flash_mem_bus.request <= 1'b0;
+ end
+ end
+ end
+
+ always_comb begin
+ n64_bus.ack = (
+ ((sdram_source_request == SOURCE_N64) && sdram_mem_bus.ack) ||
+ ((flash_source_request == SOURCE_N64) && flash_mem_bus.ack)
+ );
+ cfg_bus.ack = (
+ ((sdram_source_request == SOURCE_CFG) && sdram_mem_bus.ack) ||
+ ((flash_source_request == SOURCE_CFG) && flash_mem_bus.ack)
+ );
+ usb_dma_bus.ack = (
+ ((sdram_source_request == SOURCE_USB_DMA) && sdram_mem_bus.ack) ||
+ ((flash_source_request == SOURCE_USB_DMA) && flash_mem_bus.ack)
+ );
+ sd_dma_bus.ack = (
+ ((sdram_source_request == SOURCE_SD_DMA) && sdram_mem_bus.ack) ||
+ ((flash_source_request == SOURCE_SD_DMA) && flash_mem_bus.ack)
+ );
+
+ n64_bus.rdata = n64_flash_request ? flash_mem_bus.rdata : sdram_mem_bus.rdata;
+ cfg_bus.rdata = cfg_flash_request ? flash_mem_bus.rdata : sdram_mem_bus.rdata;
+ usb_dma_bus.rdata = usb_dma_flash_request ? flash_mem_bus.rdata : sdram_mem_bus.rdata;
+ sd_dma_bus.rdata = sd_dma_flash_request ? flash_mem_bus.rdata : sdram_mem_bus.rdata;
+ end
+
+endmodule
diff --git a/fw/rtl/memory/memory_dma.sv b/fw/rtl/memory/memory_dma.sv
index b036f67..9b4f5b7 100644
--- a/fw/rtl/memory/memory_dma.sv
+++ b/fw/rtl/memory/memory_dma.sv
@@ -1,108 +1,28 @@
-interface if_memory_dma ();
-
- logic request;
- logic ack;
- logic write;
- logic [1:0] wmask;
- logic [31:0] address;
- logic [15:0] rdata;
- logic [15:0] wdata;
+interface dma_scb ();
logic start;
logic stop;
logic busy;
logic direction;
- logic [31:0] transfer_length;
- logic [31:0] starting_address;
+ logic [26:0] starting_address;
+ logic [26:0] transfer_length;
- logic dma_rx_read;
- logic dma_tx_write;
- logic [7:0] dma_tx_wdata;
-
- logic cpu_rx_read;
- logic cpu_tx_write;
- logic [7:0] cpu_tx_wdata;
-
- logic rx_empty;
- logic rx_almost_empty;
- logic rx_read;
- logic [7:0] rx_rdata;
-
- logic tx_full;
- logic tx_almost_full;
- logic tx_write;
- logic [7:0] tx_wdata;
-
- always_comb begin
- rx_read = dma_rx_read || cpu_rx_read;
- tx_write = dma_tx_write || cpu_tx_write;
- tx_wdata = cpu_tx_write ? cpu_tx_wdata : dma_tx_wdata;
- end
+ modport controller (
+ output start,
+ output stop,
+ input busy,
+ output direction,
+ output starting_address,
+ output transfer_length
+ );
modport dma (
input start,
input stop,
output busy,
input direction,
- input transfer_length,
input starting_address,
-
- output request,
- input ack,
- output write,
- output wmask,
- output address,
- input rdata,
- output wdata,
-
- input rx_empty,
- input rx_almost_empty,
- output dma_rx_read,
- input rx_rdata,
-
- input tx_full,
- input tx_almost_full,
- output dma_tx_write,
- output dma_tx_wdata
- );
-
- modport cpu (
- output start,
- output stop,
- input busy,
- output direction,
- output transfer_length,
- output starting_address,
-
- input rx_empty,
- output cpu_rx_read,
- input rx_rdata,
-
- input tx_full,
- output cpu_tx_write,
- output cpu_tx_wdata
- );
-
- modport memory (
- input request,
- output ack,
- input write,
- input wmask,
- input address,
- output rdata,
- input wdata
- );
-
- modport device (
- output rx_empty,
- output rx_almost_empty,
- input rx_read,
- output rx_rdata,
-
- output tx_full,
- output tx_almost_full,
- input tx_write,
- input tx_wdata
+ input transfer_length
);
endinterface
@@ -111,7 +31,11 @@ endinterface
module memory_dma (
input clk,
input reset,
- if_memory_dma.dma dma
+
+ dma_scb.dma dma_scb,
+
+ fifo_bus.controller fifo_bus,
+ mem_bus.controller mem_bus
);
typedef enum bit [0:0] {
@@ -119,73 +43,79 @@ module memory_dma (
STATE_TRANSFER
} e_state;
- logic [31:0] remaining;
+ // logic [31:0] remaining;
+ logic [26:0] end_address;
logic [15:0] data_buffer;
logic byte_counter;
e_state state;
+ logic rx_delay;
always_ff @(posedge clk) begin
- dma.dma_rx_read <= 1'b0;
- dma.dma_tx_write <= 1'b0;
+ fifo_bus.rx_read <= 1'b0;
+ fifo_bus.tx_write <= 1'b0;
+ rx_delay <= fifo_bus.rx_read;
- if (dma.dma_rx_read) begin
- if (dma.address[0] || (remaining == 32'd1)) begin
- dma.wdata <= {dma.rx_rdata, dma.rx_rdata};
- end else begin
- dma.wdata <= {dma.wdata[7:0], dma.rx_rdata};
- end
+ if (rx_delay) begin
+ // if (dma.address[0] || (remaining == 32'd1)) begin
+ // dma.wdata <= {dma.rx_rdata, dma.rx_rdata};
+ // end else begin
+ mem_bus.wdata <= {mem_bus.wdata[7:0], fifo_bus.rx_rdata};
+ // end
end
if (reset) begin
- dma.busy <= 1'b0;
- dma.request <= 1'b0;
+ dma_scb.busy <= 1'b0;
+ mem_bus.request <= 1'b0;
end else begin
- if (!dma.busy) begin
- if (dma.start) begin
- dma.busy <= 1'b1;
- dma.write <= dma.direction;
- dma.address <= dma.starting_address;
- remaining <= dma.transfer_length;
+ if (!dma_scb.busy) begin
+ if (dma_scb.start) begin
+ dma_scb.busy <= 1'b1;
+ mem_bus.write <= dma_scb.direction;
+ mem_bus.address <= dma_scb.starting_address;
+ end_address <= dma_scb.starting_address + dma_scb.transfer_length;
+ // remaining <= dma.transfer_length;
byte_counter <= 1'd0;
state <= STATE_FETCH;
end
end else begin
- if (dma.stop) begin
- dma.busy <= 1'b0;
- dma.request <= 1'b0;
- end else if (remaining != 32'd0) begin
- if (dma.write) begin
+ if (dma_scb.stop) begin
+ dma_scb.busy <= 1'b0;
+ mem_bus.request <= 1'b0;
+ end else if (mem_bus.address != end_address/* remaining != 32'd0*/) begin
+ if (mem_bus.write) begin
case (state)
STATE_FETCH: begin
- if (!dma.rx_empty && !(dma.dma_rx_read && dma.rx_almost_empty)) begin
- dma.dma_rx_read <= 1'b1;
- if (dma.address[0]) begin
- dma.wmask <= 2'b01;
- state <= STATE_TRANSFER;
- end else if (remaining == 32'd1) begin
- dma.wmask <= 2'b10;
- state <= STATE_TRANSFER;
- end else begin
+ if (!fifo_bus.rx_empty && !(fifo_bus.rx_read && fifo_bus.rx_almost_empty)) begin
+ fifo_bus.rx_read <= 1'b1;
+ // if (dma.address[0]) begin
+ // dma.wmask <= 2'b01;
+ // state <= STATE_TRANSFER;
+ // end else if (dma.starting_address[0] remaining == 32'd1) begin
+ // dma.wmask <= 2'b10;
+ // state <= STATE_TRANSFER;
+ // end else begin
byte_counter <= byte_counter + 1'd1;
if (byte_counter) begin
- dma.wmask <= 2'b11;
+ mem_bus.wmask <= 2'b11;
state <= STATE_TRANSFER;
end
- end
+ // end
end
end
STATE_TRANSFER: begin
- dma.request <= 1'b1;
- if (dma.ack) begin
- dma.request <= 1'b0;
- if (dma.wmask != 2'b11) begin
- dma.address <= dma.address + 1'd1;
- remaining <= remaining - 1'd1;
- end else begin
- dma.address <= dma.address + 2'd2;
- remaining <= remaining - 2'd2;
- end
+ if (!fifo_bus.rx_read) begin
+ mem_bus.request <= 1'b1;
+ end
+ if (mem_bus.ack) begin
+ mem_bus.request <= 1'b0;
+ // if (dma.wmask != 2'b11) begin
+ // dma.address <= dma.address + 1'd1;
+ // remaining <= remaining - 1'd1;
+ // end else begin
+ mem_bus.address <= mem_bus.address + 2'd2;
+ // remaining <= remaining - 2'd2;
+ // end
state <= STATE_FETCH;
end
end
@@ -193,42 +123,42 @@ module memory_dma (
end else begin
case (state)
STATE_FETCH: begin
- dma.request <= 1'b1;
- if (dma.ack) begin
- dma.request <= 1'b0;
- data_buffer <= dma.rdata;
+ mem_bus.request <= 1'b1;
+ if (mem_bus.ack) begin
+ mem_bus.request <= 1'b0;
+ data_buffer <= mem_bus.rdata;
state <= STATE_TRANSFER;
end
end
STATE_TRANSFER: begin
- if (!dma.tx_full && !(dma.dma_tx_write && dma.tx_almost_full)) begin
- dma.dma_tx_write <= 1'b1;
- if (dma.address[0]) begin
- dma.address <= dma.address + 1'd1;
- remaining <= remaining - 1'd1;
- dma.dma_tx_wdata <= data_buffer[7:0];
- state <= STATE_FETCH;
- end else if (remaining == 32'd1) begin
- dma.address <= dma.address + 1'd1;
- remaining <= remaining - 1'd1;
- dma.dma_tx_wdata <= data_buffer[15:8];
- state <= STATE_FETCH;
- end else begin
- dma.dma_tx_wdata <= byte_counter ? data_buffer[7:0] : data_buffer[15:8];
+ if (!fifo_bus.tx_full && !(fifo_bus.tx_write && fifo_bus.tx_almost_full)) begin
+ fifo_bus.tx_write <= 1'b1;
+ // if (dma.address[0]) begin
+ // dma.address <= dma.address + 1'd1;
+ // // remaining <= remaining - 1'd1;
+ // dma.dma_tx_wdata <= data_buffer[7:0];
+ // state <= STATE_FETCH;
+ // end else if (remaining == 32'd1) begin
+ // dma.address <= dma.address + 1'd1;
+ // // remaining <= remaining - 1'd1;
+ // dma.dma_tx_wdata <= data_buffer[15:8];
+ // state <= STATE_FETCH;
+ // end else begin
+ fifo_bus.tx_wdata <= byte_counter ? data_buffer[7:0] : data_buffer[15:8];
byte_counter <= byte_counter + 1'd1;
if (byte_counter) begin
- dma.address <= dma.address + 2'd2;
- remaining <= remaining - 2'd2;
+ mem_bus.address <= mem_bus.address + 2'd2;
+ // remaining <= remaining - 2'd2;
state <= STATE_FETCH;
end
- end
+ // end
end
end
endcase
end
end else begin
- dma.busy <= 1'b0;
+ dma_scb.busy <= 1'b0;
end
end
end
diff --git a/fw/rtl/memory/memory_flash.sv b/fw/rtl/memory/memory_flash.sv
new file mode 100644
index 0000000..007e06a
--- /dev/null
+++ b/fw/rtl/memory/memory_flash.sv
@@ -0,0 +1,493 @@
+interface flash_scb ();
+
+ logic erase_pending;
+ logic erase_done;
+ logic [7:0] erase_block;
+
+ modport controller (
+ output erase_pending,
+ input erase_done,
+ output erase_block
+ );
+
+ modport flash (
+ input erase_pending,
+ output erase_done,
+ input erase_block
+ );
+
+endinterface
+
+
+module flash_qspi (
+ input clk,
+ input reset,
+
+ input start,
+ input finish,
+ output logic busy,
+ output logic valid,
+ input output_enable,
+ input quad_enable,
+ output logic [7:0] rdata,
+ input [7:0] wdata,
+
+ output logic flash_clk,
+ output logic flash_cs,
+ inout [3:0] flash_dq
+);
+
+ logic flash_dq_oe_s;
+ logic flash_dq_oe_q;
+ logic [3:0] flash_dq_out;
+
+ assign flash_dq[0] = flash_dq_oe_s ? flash_dq_out[0] : 1'bZ;
+ assign flash_dq[3:1] = flash_dq_oe_q ? flash_dq_out[3:1] : 3'bZZZ;
+
+ logic ff_clk;
+ logic ff_cs;
+ logic ff_dq_oe_s;
+ logic ff_dq_oe_q;
+ logic [3:0] ff_dq_out;
+ logic [3:0] ff_dq_in;
+
+ always_ff @(posedge clk) begin
+ flash_clk <= ff_clk;
+ flash_cs <= ff_cs;
+ flash_dq_oe_s <= ff_dq_oe_s;
+ flash_dq_oe_q <= ff_dq_oe_q;
+ flash_dq_out <= ff_dq_out;
+ ff_dq_in <= flash_dq;
+ end
+
+ logic running;
+ logic exit;
+ logic valid_enable;
+ logic quad_mode;
+ logic [2:0] counter;
+ logic [7:0] output_shift;
+ logic [2:0] sample_s;
+ logic [2:0] sample_q;
+ logic [2:0] valid_ff;
+
+ assign ff_dq_out = quad_mode ? output_shift[7:4] : {3'bXXX, output_shift[7]};
+
+ always_ff @(posedge clk) begin
+ sample_s <= {sample_s[1:0], 1'b0};
+ sample_q <= {sample_q[1:0], 1'b0};
+ valid_ff <= {valid_ff[1:0], 1'b0};
+ if (reset) begin
+ ff_clk <= 1'b0;
+ ff_cs <= 1'b1;
+ ff_dq_oe_s <= 1'b0;
+ ff_dq_oe_q <= 1'b0;
+ busy <= 1'b0;
+ running <= 1'b0;
+ end else begin
+ if (running) begin
+ ff_clk <= ~ff_clk;
+ if (!ff_clk) begin
+ if (counter == 3'd0) begin
+ busy <= 1'b0;
+ valid_ff[0] <= valid_enable;
+ end
+ if (!quad_mode) begin
+ sample_s[0] <= 1'b1;
+ end else begin
+ sample_q[0] <= 1'b1;
+ end
+ end else begin
+ counter <= counter - 1'd1;
+ if (counter == 3'd0) begin
+ running <= 1'b0;
+ end
+ if (!quad_mode) begin
+ output_shift <= {output_shift[6:0], 1'bX};
+ end else begin
+ output_shift <= {output_shift[3:0], 4'bXXXX};
+ end
+ end
+ end
+
+ if (exit) begin
+ ff_cs <= 1'b1;
+ counter <= counter - 1'd1;
+ if (counter == 3'd0) begin
+ busy <= 1'b0;
+ exit <= 1'b0;
+ end
+ end
+
+ if (!busy) begin
+ if (start) begin
+ ff_clk <= 1'b0;
+ ff_cs <= 1'b0;
+ ff_dq_oe_s <= !quad_enable || (quad_enable && output_enable);
+ ff_dq_oe_q <= quad_enable && output_enable;
+ busy <= 1'b1;
+ running <= 1'b1;
+ valid_enable <= !output_enable;
+ quad_mode <= quad_enable;
+ counter <= quad_enable ? 3'd1 : 3'd7;
+ output_shift <= wdata;
+ end else if (finish) begin
+ busy <= 1'b1;
+ exit <= 1'b1;
+ counter <= wdata[2:0];
+ end
+ end
+ end
+ end
+
+ always_ff @(posedge clk) begin
+ valid <= 1'b0;
+ if (sample_s[2]) begin
+ rdata <= {rdata[6:0], ff_dq_in[1]};
+ end
+ if (sample_q[2]) begin
+ rdata <= {rdata[3:0], ff_dq_in};
+ end
+ if (valid_ff[2]) begin
+ valid <= 1'b1;
+ end
+ end
+
+endmodule
+
+
+module memory_flash (
+ input clk,
+ input reset,
+
+ flash_scb.flash flash_scb,
+
+ mem_bus.memory mem_bus,
+
+ output flash_clk,
+ output flash_cs,
+ inout [3:0] flash_dq
+);
+
+ logic start;
+ logic finish;
+ logic busy;
+ logic valid;
+ logic output_enable;
+ logic quad_enable;
+ logic [7:0] rdata;
+ logic [7:0] wdata;
+
+ flash_qspi flash_qspi_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .start(start),
+ .finish(finish),
+ .busy(busy),
+ .valid(valid),
+ .output_enable(output_enable),
+ .quad_enable(quad_enable),
+ .rdata(rdata),
+ .wdata(wdata),
+
+ .flash_clk(flash_clk),
+ .flash_cs(flash_cs),
+ .flash_dq(flash_dq)
+ );
+
+ typedef enum bit [7:0] {
+ FLASH_CMD_PAGE_PROGRAM = 8'h02,
+ FLASH_CMD_READ_STATUS_1 = 8'h05,
+ FLASH_CMD_WRITE_ENABLE = 8'h06,
+ FLASH_CMD_BLOCK_ERASE_64KB = 8'hD8,
+ FLASH_CMD_FAST_READ_QUAD_IO = 8'hEB
+ } e_flash_cmd;
+
+ typedef enum {
+ FLASH_STATUS_1_BUSY = 0
+ } e_flash_status_1;
+
+ typedef enum bit [3:0] {
+ STATE_IDLE,
+ STATE_WRITE_ENABLE,
+ STATE_ERASE,
+ STATE_PROGRAM_START,
+ STATE_PROGRAM,
+ STATE_PROGRAM_END,
+ STATE_WAIT,
+ STATE_READ_START,
+ STATE_READ,
+ STATE_READ_END
+ } e_state;
+
+ e_state state;
+ e_state next_state;
+ logic [2:0] counter;
+ logic valid_counter;
+ logic [23:0] current_address;
+
+ always_ff @(posedge clk) begin
+ start <= 1'b0;
+ finish <= 1'b0;
+ flash_scb.erase_done <= 1'b0;
+ mem_bus.ack <= 1'b0;
+
+ if (reset) begin
+ state <= STATE_IDLE;
+ end else begin
+ if (!busy && (start || finish)) begin
+ counter <= counter + 1'd1;
+ end
+
+ case (state)
+ STATE_IDLE: begin
+ output_enable <= 1'b1;
+ quad_enable <= 1'b0;
+ counter <= 3'd0;
+ if (flash_scb.erase_pending) begin
+ state <= STATE_WRITE_ENABLE;
+ end else if (mem_bus.request) begin
+ current_address <= {mem_bus.address[23:1], 1'b0};
+ if (mem_bus.write) begin
+ state <= STATE_WRITE_ENABLE;
+ end else begin
+ state <= STATE_READ_START;
+ end
+ end
+ end
+
+ STATE_WRITE_ENABLE: begin
+ case (counter)
+ 3'd0: begin
+ start <= 1'b1;
+ wdata <= FLASH_CMD_WRITE_ENABLE;
+ end
+ 3'd1: begin
+ finish <= 1'b1;
+ wdata <= 8'd4;
+ if (!busy) begin
+ counter <= 3'd0;
+ if (flash_scb.erase_pending) begin
+ state <= STATE_ERASE;
+ end else begin
+ state <= STATE_PROGRAM_START;
+ end
+ end
+ end
+ endcase
+ end
+
+ STATE_ERASE: begin
+ case (counter)
+ 3'd0: begin
+ start <= 1'b1;
+ wdata <= FLASH_CMD_BLOCK_ERASE_64KB;
+ end
+ 3'd1: begin
+ start <= 1'b1;
+ wdata <= flash_scb.erase_block;
+ end
+ 3'd2: begin
+ start <= 1'b1;
+ wdata <= 8'd0;
+ end
+ 3'd3: begin
+ start <= 1'b1;
+ wdata <= 8'd0;
+ end
+ 3'd4: begin
+ finish <= 1'b1;
+ wdata <= 8'd4;
+ if (!busy) begin
+ flash_scb.erase_done <= 1'b1;
+ counter <= 3'd0;
+ state <= STATE_WAIT;
+ end
+ end
+ endcase
+ end
+
+ STATE_PROGRAM_START: begin
+ case (counter)
+ 3'd0: begin
+ start <= 1'b1;
+ wdata <= FLASH_CMD_PAGE_PROGRAM;
+ end
+ 3'd1: begin
+ start <= 1'b1;
+ wdata <= mem_bus.address[23:16];
+ end
+ 3'd2: begin
+ start <= 1'b1;
+ wdata <= mem_bus.address[15:8];
+ end
+ 3'd3: begin
+ start <= 1'b1;
+ wdata <= mem_bus.address[7:0];
+ if (!busy) begin
+ counter <= 3'd0;
+ state <= STATE_PROGRAM;
+ end
+ end
+ endcase
+ end
+
+ STATE_PROGRAM: begin
+ case (counter)
+ 3'd0: begin
+ start <= 1'b1;
+ wdata <= mem_bus.wdata[15:8];
+ end
+ 3'd1: begin
+ start <= 1'b1;
+ wdata <= mem_bus.wdata[7:0];
+ if (!busy) begin
+ mem_bus.ack <= 1'b1;
+ current_address <= current_address + 2'd2;
+ end
+ end
+ 3'd2: begin
+ if (current_address[7:0] == 8'h00) begin
+ state <= STATE_PROGRAM_END;
+ end else if (flash_scb.erase_pending) begin
+ state <= STATE_PROGRAM_END;
+ end else if (mem_bus.request && !mem_bus.ack) begin
+ if (!mem_bus.write || (mem_bus.address[23:0] != current_address)) begin
+ state <= STATE_PROGRAM_END;
+ end else begin
+ counter <= 3'd0;
+ end
+ end
+ end
+ endcase
+ end
+
+ STATE_PROGRAM_END: begin
+ finish <= 1'b1;
+ wdata <= 8'd4;
+ if (!busy) begin
+ counter <= 3'd0;
+ state <= STATE_WAIT;
+ end
+ end
+
+ STATE_WAIT: begin
+ case (counter)
+ 3'd0: begin
+ start <= 1'b1;
+ output_enable <= 1'b1;
+ wdata <= FLASH_CMD_READ_STATUS_1;
+ end
+ 3'd1: begin
+ start <= 1'b1;
+ output_enable <= 1'b0;
+ end
+ 3'd2: begin
+ finish <= 1'b1;
+ wdata <= 8'd0;
+ end
+ 3'd3: begin
+ counter <= counter;
+ end
+ endcase
+ if (valid) begin
+ if (rdata[FLASH_STATUS_1_BUSY]) begin
+ counter <= 3'd0;
+ end else begin
+ state <= STATE_IDLE;
+ end
+ end
+ end
+
+ STATE_READ_START: begin
+ case (counter)
+ 3'd0: begin
+ start <= 1'b1;
+ wdata <= FLASH_CMD_FAST_READ_QUAD_IO;
+ end
+ 3'd1: begin
+ start <= 1'b1;
+ quad_enable <= 1'b1;
+ wdata <= mem_bus.address[23:16];
+ end
+ 3'd2: begin
+ start <= 1'b1;
+ wdata <= mem_bus.address[15:8];
+ end
+ 3'd3: begin
+ start <= 1'b1;
+ wdata <= mem_bus.address[7:0];
+ end
+ 3'd4: begin
+ start <= 1'b1;
+ wdata <= 8'hFF;
+ end
+ 3'd5: begin
+ start <= 1'b1;
+ end
+ 3'd6: begin
+ start <= 1'b1;
+ if (!busy) begin
+ counter <= 3'd0;
+ valid_counter <= 1'b0;
+ state <= STATE_READ;
+ end
+ end
+ endcase
+ end
+
+ STATE_READ: begin
+ case (counter)
+ 3'd0: begin
+ start <= 1'b1;
+ output_enable <= 1'b0;
+ end
+ 3'd1: begin
+ start <= 1'b1;
+ end
+ 3'd2: begin end
+ 3'd3: begin
+ if (flash_scb.erase_pending) begin
+ state <= STATE_READ_END;
+ end else if (mem_bus.request && !mem_bus.ack) begin
+ if (mem_bus.write || (mem_bus.address[23:0] != current_address)) begin
+ state <= STATE_READ_END;
+ end else begin
+ start <= 1'b1;
+ counter <= 3'd0;
+ end
+ end
+ end
+ endcase
+ if (valid) begin
+ valid_counter <= ~valid_counter;
+ if (valid_counter) begin
+ mem_bus.ack <= 1'b1;
+ counter <= counter + 1'd1;
+ current_address <= current_address + 2'd2;
+ end
+ end
+ end
+
+ STATE_READ_END: begin
+ finish <= 1'b1;
+ wdata <= 8'd0;
+ if (!busy) begin
+ state <= STATE_IDLE;
+ end
+ end
+
+ default: begin
+ state <= STATE_IDLE;
+ end
+ endcase
+ end
+ end
+
+ always_ff @(posedge clk) begin
+ if (valid) begin
+ mem_bus.rdata <= {mem_bus.rdata[7:0], rdata};
+ end
+ end
+
+endmodule
diff --git a/fw/rtl/memory/memory_sdram.sv b/fw/rtl/memory/memory_sdram.sv
index 06e3e51..fce983a 100644
--- a/fw/rtl/memory/memory_sdram.sv
+++ b/fw/rtl/memory/memory_sdram.sv
@@ -1,48 +1,41 @@
module memory_sdram (
- if_system sys,
+ input clk,
+ input reset,
- input request,
- output ack,
- input write,
- input [25:0] address,
- output [15:0] rdata,
- input [15:0] wdata,
+ mem_bus.memory mem_bus,
- output sdram_cs,
- output sdram_ras,
- output sdram_cas,
- output sdram_we,
- output [1:0] sdram_ba,
- output [12:0] sdram_a,
+ output logic sdram_cs,
+ output logic sdram_ras,
+ output logic sdram_cas,
+ output logic sdram_we,
+ output logic [1:0] sdram_ba,
+ output logic [12:0] sdram_a,
+ output logic [1:0] sdram_dqm,
inout [15:0] sdram_dq
);
- parameter [2:0] CAS_LATENCY = 3'd2;
+ localparam [2:0] CAS_LATENCY = 3'd2;
- parameter real T_INIT = 100_000.0;
- parameter real T_RC = 60.0;
- parameter real T_RP = 15.0;
- parameter real T_RCD = 15.0;
- // parameter real T_RAS = 37.0; //TODO: handle this timing
- // parameter real T_WR = T_RAS - T_RCD; //TODO: handle this timing
- parameter real T_MRD = 14.0;
- parameter real T_REF = 7_800.0;
+ localparam real T_INIT = 100_000.0;
+ localparam real T_RC = 60.0;
+ localparam real T_RP = 15.0;
+ localparam real T_RCD = 15.0;
+ localparam real T_MRD = 14.0;
+ localparam real T_REF = 7_800.0;
- localparam real T_CLK = (1.0 / sc64::CLOCK_FREQUENCY) * 1_000_000_000.0;
+ localparam real T_CLK = (1.0 / 100_000_000) * 1_000_000_000.0;
localparam int C_INIT = int'((T_INIT + T_CLK - 1) / T_CLK);
localparam int C_RC = int'((T_RC + T_CLK - 1) / T_CLK);
localparam int C_RP = int'((T_RP + T_CLK - 1) / T_CLK);
localparam int C_RCD = int'((T_RCD + T_CLK - 1) / T_CLK);
- // localparam int C_RAS = int'((T_RAS + T_CLK - 1) / T_CLK);
- // localparam int C_WR = int'((T_WR + T_CLK - 1) / T_CLK);
localparam int C_MRD = int'((T_MRD + T_CLK - 1) / T_CLK);
localparam int C_REF = int'((T_REF + T_CLK - 1) / T_CLK);
- localparam INIT_PRECHARGE = C_INIT;
- localparam INIT_REFRESH_1 = C_INIT + C_RP;
- localparam INIT_REFRESH_2 = C_INIT + C_RP + C_RC;
- localparam INIT_MODE_REG = C_INIT + C_RP + (2 * C_RC);
- localparam INIT_DONE = C_INIT + C_RP + (2 * C_RC) + C_MRD;
+ localparam INIT_PRECHARGE = 4'd0;
+ localparam INIT_REFRESH_1 = C_RP;
+ localparam INIT_REFRESH_2 = C_RP + C_RC;
+ localparam INIT_MODE_REG = C_RP + (2 * C_RC);
+ localparam INIT_DONE = C_RP + (2 * C_RC) + C_MRD;
typedef enum bit [3:0] {
CMD_DESL = 4'b1111,
@@ -63,37 +56,51 @@ module memory_sdram (
logic [14:0] current_active_bank_row;
logic request_in_current_active_bank_row;
- always_ff @(posedge sys.clk) begin
+ always_ff @(posedge clk) begin
{sdram_cs, sdram_ras, sdram_cas, sdram_we} <= 4'(sdram_next_cmd);
{sdram_ba, sdram_a} <= 15'd0;
+ sdram_dqm <= 2'b00;
sdram_dq_input <= sdram_dq;
- sdram_dq_output <= wdata;
+ sdram_dq_output <= mem_bus.wdata;
sdram_dq_output_enable <= 1'b0;
case (sdram_next_cmd)
CMD_READ, CMD_WRITE: begin
- {sdram_ba, sdram_a} <= {address[25:24], 3'b000, address[10:1]};
- sdram_dq_output_enable <= sdram_next_cmd == CMD_WRITE;
+ {sdram_ba, sdram_a} <= {mem_bus.address[25:24], 3'b000, mem_bus.address[10:1]};
+ sdram_dqm <= (sdram_next_cmd == CMD_WRITE) ? (~mem_bus.wmask) : 2'b00;
+ sdram_dq_output_enable <= (sdram_next_cmd == CMD_WRITE);
end
+
CMD_ACT: begin
- {sdram_ba, sdram_a} <= address[25:11];
- current_active_bank_row <= address[25:11];
+ {sdram_ba, sdram_a} <= mem_bus.address[25:11];
+ sdram_dqm <= 2'b00;
+ current_active_bank_row <= mem_bus.address[25:11];
+ end
+
+ CMD_PRE: begin
+ {sdram_ba, sdram_a} <= {2'b00, 2'b00, 1'b1, 10'd0};
+ sdram_dqm <= 2'b00;
+ end
+
+ CMD_MRS: begin
+ {sdram_ba, sdram_a} <= {2'b00, 1'b0, 1'b0, 2'b00, CAS_LATENCY, 1'b0, 3'b000};
+ sdram_dqm <= 2'b00;
end
- CMD_PRE: {sdram_ba, sdram_a} <= {2'b00, 2'b00, 1'b1, 10'd0};
- CMD_MRS: {sdram_ba, sdram_a} <= {2'b00, 1'b0, 1'b0, 2'b00, CAS_LATENCY, 1'b0, 3'b000};
endcase
end
+ assign sdram_dq = sdram_dq_output_enable ? sdram_dq_output : 16'hZZZZ;
+
always_comb begin
- rdata = sdram_dq_input;
- sdram_dq = sdram_dq_output_enable ? sdram_dq_output : 16'hZZZZ;
- request_in_current_active_bank_row = address[25:11] == current_active_bank_row;
+ mem_bus.rdata = sdram_dq_input;
+ request_in_current_active_bank_row = mem_bus.address[25:11] == current_active_bank_row;
end
typedef enum bit [2:0] {
+ S_POWERUP,
S_INIT,
S_IDLE,
S_ACTIVATING,
@@ -106,44 +113,54 @@ module memory_sdram (
e_state state;
e_state next_state;
- always_ff @(posedge sys.clk) begin
- if (sys.reset) begin
- state <= S_INIT;
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ state <= S_POWERUP;
end else begin
state <= next_state;
end
end
- logic [13:0] wait_counter;
+ logic [13:0] powerup_coutner;
+ logic powerup_done;
+ logic [4:0] wait_counter;
logic [9:0] refresh_counter;
logic pending_refresh;
- always_ff @(posedge sys.clk) begin
- if (sys.reset || state != next_state) begin
- wait_counter <= 14'd0;
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ powerup_coutner <= 14'd0;
+ powerup_done <= 1'b0;
+ end else if (powerup_coutner < C_INIT) begin
+ powerup_coutner <= powerup_coutner + 1'd1;
+ end else begin
+ powerup_done <= 1'b1;
+ end
+
+ if (reset || state != next_state) begin
+ wait_counter <= 5'd0;
end else begin
wait_counter <= wait_counter + 1'd1;
end
if (sdram_next_cmd == CMD_REF) begin
refresh_counter <= 10'd0;
- end else if (refresh_counter < 10'h3FF) begin
+ pending_refresh <= 1'b0;
+ end else if (refresh_counter < C_REF) begin
refresh_counter <= refresh_counter + 1'd1;
+ end else begin
+ pending_refresh <= 1'b1;
end
end
- always_comb begin
- pending_refresh = refresh_counter >= C_REF;
- end
-
logic [(CAS_LATENCY):0] read_cmd_ack_delay;
- always_ff @(posedge sys.clk) begin
- ack <= 1'b0;
+ always_ff @(posedge clk) begin
+ mem_bus.ack <= 1'b0;
read_cmd_ack_delay <= {sdram_next_cmd == CMD_READ, read_cmd_ack_delay[(CAS_LATENCY):1]};
if (sdram_next_cmd == CMD_WRITE || read_cmd_ack_delay[0]) begin
- ack <= 1'b1;
+ mem_bus.ack <= 1'b1;
end
end
@@ -152,10 +169,14 @@ module memory_sdram (
next_state = state;
case (state)
- S_INIT: begin
- if (wait_counter < INIT_PRECHARGE) begin
- sdram_next_cmd = CMD_DESL;
+ S_POWERUP: begin
+ sdram_next_cmd = CMD_DESL;
+ if (powerup_done) begin
+ next_state = S_INIT;
end
+ end
+
+ S_INIT: begin
if (wait_counter == INIT_PRECHARGE) begin
sdram_next_cmd = CMD_PRE;
end
@@ -174,7 +195,7 @@ module memory_sdram (
if (pending_refresh) begin
next_state = S_REFRESH;
sdram_next_cmd = CMD_REF;
- end else if (request) begin
+ end else if (mem_bus.request) begin
next_state = S_ACTIVATING;
sdram_next_cmd = CMD_ACT;
end
@@ -190,10 +211,10 @@ module memory_sdram (
if (pending_refresh) begin
next_state = S_PRECHARGE;
sdram_next_cmd = CMD_PRE;
- end else if (request) begin
+ end else if (mem_bus.request) begin
if (request_in_current_active_bank_row) begin
next_state = S_BUSY;
- sdram_next_cmd = write ? CMD_WRITE : CMD_READ;
+ sdram_next_cmd = mem_bus.write ? CMD_WRITE : CMD_READ;
end else begin
next_state = S_PRECHARGE;
sdram_next_cmd = CMD_PRE;
@@ -202,7 +223,7 @@ module memory_sdram (
end
S_BUSY: begin
- if (ack) begin
+ if (mem_bus.ack) begin
next_state = S_ACTIVE;
end
end
diff --git a/fw/rtl/n64/n64_bootloader.sv b/fw/rtl/n64/n64_bootloader.sv
deleted file mode 100644
index 52cde36..0000000
--- a/fw/rtl/n64/n64_bootloader.sv
+++ /dev/null
@@ -1,94 +0,0 @@
-module n64_bootloader (
- if_system.sys sys,
- if_n64_bus bus,
- if_config.flash cfg,
- if_flash.flash flash
-);
-
- typedef enum bit [0:0] {
- S_IDLE,
- S_WAIT
- } e_state;
-
- typedef enum bit [0:0] {
- T_N64,
- T_CPU
- } e_source_request;
-
- e_state state;
- e_source_request source_request;
-
- logic request;
- logic ack;
- logic write;
- logic [31:0] address;
- logic [31:0] wdata;
- logic [31:0] rdata;
-
- always_ff @(posedge sys.clk) begin
- if (sys.reset) begin
- state <= S_IDLE;
- request <= 1'b0;
- end else begin
- case (state)
- S_IDLE: begin
- if (bus.request || flash.request) begin
- state <= S_WAIT;
- request <= 1'b1;
- if (bus.request) begin
- write <= 1'b0;
- address <= bus.address;
- wdata <= bus.wdata;
- source_request <= T_N64;
- end else if (flash.request) begin
- write <= flash.write;
- address <= flash.address;
- wdata <= flash.wdata;
- source_request <= T_CPU;
- end
- end
- end
-
- S_WAIT: begin
- if (ack) begin
- state <= S_IDLE;
- request <= 1'b0;
- end
- end
- endcase
- end
- end
-
- always_comb begin
- bus.ack = source_request == T_N64 && ack;
- bus.rdata = 16'd0;
- if (bus.ack && bus.address < 32'h00010000) begin
- if (bus.address[1]) bus.rdata = {rdata[23:16], rdata[31:24]};
- else bus.rdata = {rdata[7:0], rdata[15:8]};
- end
-
- flash.ack = source_request == T_CPU && ack;
- flash.rdata = 32'd0;
- if (flash.ack) begin
- flash.rdata = rdata;
- end
- end
-
- vendor_flash vendor_flash_inst (
- .clk(sys.clk),
- .reset(sys.reset),
-
- .erase_start(cfg.flash_erase_start),
- .erase_busy(cfg.flash_erase_busy),
- .wp_enable(cfg.flash_wp_enable),
- .wp_disable(cfg.flash_wp_disable),
-
- .request(request),
- .ack(ack),
- .write(write),
- .address(address),
- .wdata(wdata),
- .rdata(rdata)
- );
-
-endmodule
diff --git a/fw/rtl/n64/n64_bus.sv b/fw/rtl/n64/n64_bus.sv
deleted file mode 100644
index d85be7f..0000000
--- a/fw/rtl/n64/n64_bus.sv
+++ /dev/null
@@ -1,69 +0,0 @@
-interface if_n64_bus ();
-
- localparam sc64::e_n64_id NUM_DEVICES = sc64::__ID_N64_END;
-
- sc64::e_n64_id id;
- logic request;
- logic ack;
- logic write;
- logic [31:0] address;
- logic [15:0] wdata;
- logic [15:0] rdata;
- logic [31:0] real_address;
- logic read_op;
- logic write_op;
-
- logic device_ack [(NUM_DEVICES - 1):0];
- logic [15:0] device_rdata [(NUM_DEVICES - 1):0];
-
- always_comb begin
- ack = 1'b0;
- rdata = 16'd0;
-
- for (integer i = 0; i < NUM_DEVICES; i++) begin
- ack = ack | device_ack[i];
- rdata = rdata | device_rdata[i];
- end
-
- if (id >= NUM_DEVICES) begin
- ack = request;
- end
- end
-
- modport n64 (
- output id,
- output request,
- input ack,
- output write,
- output address,
- output wdata,
- input rdata,
- output real_address,
- output read_op,
- output write_op
- );
-
- genvar n;
- generate
- for (n = 0; n < NUM_DEVICES; n++) begin : at
- logic device_request;
-
- always_comb begin
- device_request = request && id == sc64::e_n64_id'(n);
- end
-
- modport device (
- input .request(device_request),
- output .ack(device_ack[n]),
- input .write(write),
- input .address(address),
- input .wdata(wdata),
- output .rdata(device_rdata[n]),
- input .real_address(real_address),
- input .read_op(read_op),
- input .write_op(write_op)
- );
- end
- endgenerate
-
-endinterface
diff --git a/fw/rtl/n64/n64_cfg.sv b/fw/rtl/n64/n64_cfg.sv
index 8f7dc3f..ea8f1d9 100644
--- a/fw/rtl/n64/n64_cfg.sv
+++ b/fw/rtl/n64/n64_cfg.sv
@@ -1,84 +1,68 @@
module n64_cfg (
- if_system sys,
- if_n64_bus bus,
- if_config.n64 cfg
+ input clk,
+ input reset,
+
+ n64_reg_bus.cfg reg_bus,
+
+ n64_scb.cfg n64_scb,
+
+ output logic irq
);
typedef enum bit [2:0] {
- R_SR,
- R_COMMAND,
- R_DATA_0_H,
- R_DATA_0_L,
- R_DATA_1_H,
- R_DATA_1_L,
- R_VERSION_H,
- R_VERSION_L
- } e_reg_id;
-
- typedef enum bit [0:0] {
- S_IDLE,
- S_WAIT
- } e_state;
-
- e_state state;
+ REG_STATUS,
+ REG_COMMAND,
+ REG_DATA_0_H,
+ REG_DATA_0_L,
+ REG_DATA_1_H,
+ REG_DATA_1_L,
+ REG_VERSION_H,
+ REG_VERSION_L
+ } e_reg;
always_comb begin
- bus.rdata = 16'd0;
- if (bus.ack) begin
- case (bus.address[3:1])
- R_SR: bus.rdata = {
- cfg.cpu_ready,
- cfg.cpu_busy,
- 1'b0,
- cfg.cmd_error,
- 12'd0
- };
- R_COMMAND: bus.rdata = {8'd0, cfg.cmd};
- R_DATA_0_H: bus.rdata = cfg.data[0][31:16];
- R_DATA_0_L: bus.rdata = cfg.data[0][15:0];
- R_DATA_1_H: bus.rdata = cfg.data[1][31:16];
- R_DATA_1_L: bus.rdata = cfg.data[1][15:0];
- R_VERSION_H: bus.rdata = sc64::SC64_VER[31:16];
- R_VERSION_L: bus.rdata = sc64::SC64_VER[15:0];
- default: bus.rdata = 16'd0;
- endcase
- end
+ reg_bus.rdata = 16'd0;
+ case (reg_bus.address[3:1])
+ REG_STATUS: reg_bus.rdata = {
+ n64_scb.cfg_pending,
+ n64_scb.cfg_error,
+ 14'd0
+ };
+ REG_DATA_0_H: reg_bus.rdata = n64_scb.cfg_wdata[0][31:16];
+ REG_DATA_0_L: reg_bus.rdata = n64_scb.cfg_wdata[0][15:0];
+ REG_DATA_1_H: reg_bus.rdata = n64_scb.cfg_wdata[1][31:16];
+ REG_DATA_1_L: reg_bus.rdata = n64_scb.cfg_wdata[1][15:0];
+ REG_VERSION_H: reg_bus.rdata = n64_scb.cfg_version[31:16];
+ REG_VERSION_L: reg_bus.rdata = n64_scb.cfg_version[15:0];
+ endcase
end
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
- cfg.cmd_request <= 1'b0;
-
- if (cfg.data_write[0]) cfg.data[0] <= cfg.wdata;
- if (cfg.data_write[1]) cfg.data[1] <= cfg.wdata;
-
- if (sys.reset) begin
- state <= S_IDLE;
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ n64_scb.cfg_pending <= 1'b0;
+ irq <= 1'b0;
end else begin
- case (state)
- S_IDLE: begin
- if (bus.request) begin
- state <= S_WAIT;
- bus.ack <= 1'b1;
- if (bus.write) begin
- case (bus.address[3:1])
- R_COMMAND: begin
- cfg.cmd <= bus.wdata[7:0];
- cfg.cmd_request <= 1'b1;
- end
- R_DATA_0_H: cfg.data[0][31:16] <= bus.wdata;
- R_DATA_0_L: cfg.data[0][15:0] <= bus.wdata;
- R_DATA_1_H: cfg.data[1][31:16] <= bus.wdata;
- R_DATA_1_L: cfg.data[1][15:0] <= bus.wdata;
- endcase
- end
- end
- end
+ if (n64_scb.cfg_done) begin
+ n64_scb.cfg_pending <= 1'b0;
+ end
- S_WAIT: begin
- state <= S_IDLE;
- end
- endcase
+ if (n64_scb.cfg_irq) begin
+ irq <= 1'b1;
+ end
+
+ if (reg_bus.write) begin
+ case (reg_bus.address[3:1])
+ REG_COMMAND: begin
+ n64_scb.cfg_pending <= 1'b1;
+ n64_scb.cfg_cmd <= reg_bus.wdata[7:0];
+ end
+ REG_DATA_0_H: n64_scb.cfg_rdata[0][31:16] <= reg_bus.wdata;
+ REG_DATA_0_L: n64_scb.cfg_rdata[0][15:0] <= reg_bus.wdata;
+ REG_DATA_1_H: n64_scb.cfg_rdata[1][31:16] <= reg_bus.wdata;
+ REG_DATA_1_L: n64_scb.cfg_rdata[1][15:0] <= reg_bus.wdata;
+ REG_VERSION_L: irq <= 1'b0;
+ endcase
+ end
end
end
diff --git a/fw/rtl/n64/n64_dd.sv b/fw/rtl/n64/n64_dd.sv
index 2c36d48..b21cba9 100644
--- a/fw/rtl/n64/n64_dd.sv
+++ b/fw/rtl/n64/n64_dd.sv
@@ -1,172 +1,16 @@
-interface if_dd (
- output dd_interrupt
-);
-
- // Sector buffer regs
-
- logic [6:0] n64_sector_address;
- logic n64_sector_address_valid;
- logic n64_sector_write;
- logic [15:0] n64_sector_wdata;
-
- logic [5:0] cpu_sector_address;
- logic cpu_sector_address_valid;
- logic cpu_sector_write;
- logic [31:0] cpu_sector_wdata;
-
- logic [31:0] sector_rdata;
-
-
- // N64 controlled regs
-
- logic hard_reset;
- logic [15:0] data;
- logic [7:0] cmd;
- logic cmd_pending;
- logic cmd_interrupt;
- logic bm_start_pending;
- logic bm_stop_pending;
- logic bm_transfer_mode;
- logic bm_transfer_blocks;
- logic bm_pending;
- logic bm_interrupt;
- logic bm_interrupt_ack;
- logic [7:0] sector_num;
- logic [7:0] sector_size;
- logic [7:0] sector_size_full;
- logic [7:0] sectors_in_block;
-
-
- // CPU controlled regs
-
- logic hard_reset_clear;
- logic [15:0] cmd_data;
- logic cmd_ready;
- logic bm_start_clear;
- logic bm_stop_clear;
- logic bm_transfer_c2;
- logic bm_transfer_data;
- logic bm_micro_error;
- logic bm_clear;
- logic bm_ready;
- logic disk_inserted;
- logic disk_changed;
- logic index_lock;
- logic [12:0] head_track;
- logic [15:0] drive_id;
-
-
- always_comb begin
- dd_interrupt = cmd_interrupt || bm_interrupt;
- end
-
-
- modport dd (
- output hard_reset,
- output data,
- output cmd,
- output cmd_pending,
- output cmd_interrupt,
- output bm_start_pending,
- output bm_stop_pending,
- output bm_transfer_mode,
- output bm_transfer_blocks,
- output bm_pending,
- output bm_interrupt,
- output bm_interrupt_ack,
- output sector_num,
- output sector_size,
- output sector_size_full,
- output sectors_in_block,
-
- input hard_reset_clear,
- input cmd_data,
- input cmd_ready,
- input bm_start_clear,
- input bm_stop_clear,
- input bm_transfer_c2,
- input bm_transfer_data,
- input bm_micro_error,
- input bm_clear,
- input bm_ready,
- input disk_inserted,
- input disk_changed,
- input index_lock,
- input head_track,
- input drive_id,
-
- output .sector_address(n64_sector_address),
- output .sector_address_valid(n64_sector_address_valid),
- output .sector_write(n64_sector_write),
- output .sector_wdata(n64_sector_wdata),
- input sector_rdata
- );
-
- modport cpu (
- input hard_reset,
- input data,
- input cmd,
- input cmd_pending,
- input bm_start_pending,
- input bm_stop_pending,
- input bm_transfer_mode,
- input bm_transfer_blocks,
- input bm_pending,
- input bm_interrupt_ack,
- input sector_num,
- input sector_size,
- input sector_size_full,
- input sectors_in_block,
-
- output hard_reset_clear,
- output cmd_data,
- output cmd_ready,
- output bm_start_clear,
- output bm_stop_clear,
- output bm_transfer_c2,
- output bm_transfer_data,
- output bm_micro_error,
- output bm_ready,
- output bm_clear,
- output disk_inserted,
- output disk_changed,
- output index_lock,
- output head_track,
- output drive_id,
-
- output .sector_address(cpu_sector_address),
- output .sector_address_valid(cpu_sector_address_valid),
- output .sector_write(cpu_sector_write),
- output .sector_wdata(cpu_sector_wdata),
- input sector_rdata
- );
-
- modport sector_buffer (
- input n64_sector_address,
- input n64_sector_address_valid,
- input n64_sector_write,
- input n64_sector_wdata,
-
- input cpu_sector_address,
- input cpu_sector_address_valid,
- input cpu_sector_write,
- input cpu_sector_wdata,
-
- output sector_rdata
- );
-
-endinterface
-
-
module n64_dd (
- if_system.sys sys,
- if_n64_bus bus,
- if_dd.dd dd
+ input clk,
+ input reset,
+
+ n64_reg_bus.dd reg_bus,
+
+ n64_scb.dd n64_scb,
+
+ output logic irq
);
- const bit [31:0] M_BASE = 32'h0500_0000;
- const bit [31:0] M_C2_BUFFER = M_BASE + 11'h000;
- const bit [31:0] M_SECTOR_BUFFER = M_BASE + 11'h400;
+ const bit [10:0] M_C2_BUFFER = 11'h000;
+ const bit [10:0] M_SECTOR_BUFFER = 11'h400;
typedef enum bit [10:0] {
R_DATA = 11'h500,
@@ -187,19 +31,19 @@ module n64_dd (
BM_CONTROL_MECHANIC_INTERRUPT_RESET = 4'd8
} e_bm_control_id;
- typedef enum bit [0:0] {
- S_IDLE,
- S_WAIT
- } e_state;
+ // typedef enum bit [0:0] {
+ // S_IDLE,
+ // S_WAIT
+ // } e_state;
- e_state state;
+ // e_state state;
- always_comb begin
- dd.sector_address = bus.address[7:1];
- dd.sector_address_valid = bus.request && bus.address[11:8] == M_SECTOR_BUFFER[11:8];
- dd.sector_write = bus.write && dd.sector_address_valid;
- dd.sector_wdata = bus.wdata;
- end
+ // always_comb begin
+ // dd.sector_address = bus.address[7:1];
+ // dd.sector_address_valid = bus.request && bus.address[11:8] == M_SECTOR_BUFFER[11:8];
+ // dd.sector_write = bus.write && dd.sector_address_valid;
+ // dd.sector_wdata = bus.wdata;
+ // end
always_comb begin
bus.rdata = 16'd0;
@@ -240,6 +84,38 @@ module n64_dd (
end
end
+ always_comb begin
+ reg_bus.rdata = 16'd0;
+ if (reg_bus.address[10:8] == M_SECTOR_BUFFER[10:8]) begin
+ end else begin
+ case (reg_bus.address[10:0])
+ R_DATA: reg_bus.rdata = dd.data;
+ R_CMD_SR: reg_bus.rdata = {
+ 1'b0,
+ dd.bm_transfer_data,
+ 1'b0,
+ dd.bm_transfer_c2,
+ 1'b0,
+ dd.bm_interrupt,
+ dd.cmd_interrupt,
+ dd.disk_inserted,
+ dd.cmd_pending,
+ dd.hard_reset,
+ 1'b0,
+ 1'b0,
+ 1'b0,
+ 1'b0,
+ 1'b0,
+ dd.disk_changed
+ };
+ R_TRK_CUR: reg_bus.rdata = {1'd0, {2{dd.index_lock}}, dd.head_track};
+ R_BM_SCR: reg_bus.rdata = {6'd0, dd.bm_micro_error, 9'd0};
+ R_ID: reg_bus.rdata = {dd.drive_id};
+ default: reg_bus.rdata = 16'd0;
+ endcase
+ end
+ end
+
always_ff @(posedge sys.clk) begin
bus.ack <= 1'b0;
dd.bm_interrupt_ack <= 1'b0;
@@ -354,51 +230,5 @@ module n64_dd (
end
end
-endmodule
-
-
-module n64_dd_sector_buffer (
- if_system.sys sys,
- if_dd.sector_buffer dd
-);
-
- logic [5:0] sector_address;
- logic [31:0] sector_buffer [0:63];
- logic [15:0] sector_high_buffer;
- logic sector_write;
- logic [31:0] sector_wdata;
-
- always_comb begin
- sector_address = 6'd0;
- sector_write = 1'b0;
- sector_wdata = 32'd0;
-
- if (dd.n64_sector_address_valid) begin
- sector_address = dd.n64_sector_address[6:1];
- end else if (dd.cpu_sector_address_valid) begin
- sector_address = dd.cpu_sector_address;
- end
-
- if (dd.n64_sector_write && dd.n64_sector_address[0]) begin
- sector_write = 1'b1;
- sector_wdata = {sector_high_buffer, dd.n64_sector_wdata};
- end else if (dd.cpu_sector_write) begin
- sector_write = 1'b1;
- sector_wdata = dd.cpu_sector_wdata;
- end
- end
-
- always_ff @(posedge sys.clk) begin
- if (dd.n64_sector_write && !dd.n64_sector_address[0]) begin
- sector_high_buffer <= dd.n64_sector_wdata;
- end
- end
-
- always_ff @(posedge sys.clk) begin
- dd.sector_rdata <= sector_buffer[sector_address];
- if (sector_write) begin
- sector_buffer[sector_address] <= sector_wdata;
- end
- end
endmodule
diff --git a/fw/rtl/n64/n64_flashram.sv b/fw/rtl/n64/n64_flashram.sv
index 8ca686f..79199c7 100644
--- a/fw/rtl/n64/n64_flashram.sv
+++ b/fw/rtl/n64/n64_flashram.sv
@@ -1,188 +1,153 @@
module n64_flashram (
- if_system.sys sys,
- if_n64_bus bus,
- if_config.flashram cfg,
- if_flashram.flashram flashram
+ input clk,
+ input reset,
+
+ n64_reg_bus.flashram reg_bus,
+
+ n64_scb.flashram n64_scb
);
localparam [31:0] FLASH_TYPE_ID = 32'h1111_8001;
localparam [31:0] FLASH_MODEL_ID = 32'h00C2_001D;
typedef enum bit [7:0] {
- CMD_STATUS_MODE = 8'hD2,
- CMD_READID_MODE = 8'hE1,
- CMD_READ_MODE = 8'hF0,
- CMD_ERASE_SECTOR = 8'h4B,
- CMD_ERASE_CHIP = 8'h3C,
- CMD_BUFFER_MODE = 8'hB4,
- CMD_ERASE_START = 8'h78,
- CMD_WRITE_START = 8'hA5
+ CMD_STATUS_MODE = 8'hD2,
+ CMD_READID_MODE = 8'hE1,
+ CMD_READ_MODE = 8'hF0,
+ CMD_ERASE_SECTOR = 8'h4B,
+ CMD_ERASE_CHIP = 8'h3C,
+ CMD_BUFFER_MODE = 8'hB4,
+ CMD_ERASE_START = 8'h78,
+ CMD_WRITE_START = 8'hA5
} e_cmd;
- typedef enum bit [0:0] {
- S_IDLE,
- S_WAIT
- } e_bus_state;
+ typedef enum bit [1:0] {
+ STATE_STATUS,
+ STATE_ID,
+ STATE_READ,
+ STATE_BUFFER
+ } e_state;
typedef enum bit [1:0] {
- FS_STATUS,
- FS_ID,
- FS_READ,
- FS_BUFFER
- } e_flashram_state;
+ WRITE_BUSY,
+ ERASE_BUSY,
+ WRITE_DONE,
+ ERASE_DONE
+ } e_status_bits;
- typedef enum bit [1:0] {
- B_WRITE_BUSY,
- B_ERASE_BUSY,
- B_WRITE_DONE,
- B_ERASE_DONE
- } e_flashram_status;
+ e_state state;
+ logic [3:0] status;
+ logic [7:0] cmd;
+ logic erase_enabled;
- e_bus_state bus_state;
- e_flashram_state flashram_state;
- logic [3:0] flashram_status;
- logic [7:0] flashram_command;
- logic flashram_erase_enabled;
+ logic [15:0] write_buffer [0:63];
- logic [31:0] write_buffer [0:31];
- logic [1:0] write_buffer_wmask;
- logic [15:0] high_buffer;
-
- always_comb begin
- write_buffer_wmask = 2'b00;
- if (bus.request && bus.write && !bus.address[16] && flashram_state == FS_BUFFER) begin
- write_buffer_wmask[0] = !bus.address[1];
- write_buffer_wmask[1] = bus.address[1];
- end
- end
-
- always_ff @(posedge sys.clk) begin
- if (write_buffer_wmask[0]) high_buffer <= bus.wdata;
- end
-
- always_ff @(posedge sys.clk) begin
- flashram.rdata <= write_buffer[flashram.address];
- if (write_buffer_wmask[1]) write_buffer[bus.address[6:2]] <= {high_buffer, bus.wdata};
+ always_ff @(posedge clk) begin
+ n64_scb.flashram_buffer_rdata <= write_buffer[n64_scb.flashram_buffer_address];
end
always_comb begin
- bus.rdata = 16'd0;
- if (bus.ack) begin
- if (bus.address[1]) begin
- bus.rdata = {12'd0, flashram_status};
- end
- if (flashram_state == FS_ID) begin
- case (bus.address[2:1])
- 0: bus.rdata = FLASH_TYPE_ID[31:16];
- 1: bus.rdata = FLASH_TYPE_ID[15:0];
- 2: bus.rdata = FLASH_MODEL_ID[31:16];
- 3: bus.rdata = FLASH_MODEL_ID[15:0];
- endcase
- end
- end
+ n64_scb.flashram_read_mode = (state == STATE_READ);
- cfg.flashram_read_mode = flashram_state == FS_READ;
+ reg_bus.rdata = 16'd0;
+ if (state == STATE_ID) begin
+ case (reg_bus.address[2:1])
+ 0: reg_bus.rdata = FLASH_TYPE_ID[31:16];
+ 1: reg_bus.rdata = FLASH_TYPE_ID[15:0];
+ 2: reg_bus.rdata = FLASH_MODEL_ID[31:16];
+ 3: reg_bus.rdata = FLASH_MODEL_ID[15:0];
+ endcase
+ end else if (reg_bus.address[1]) begin
+ reg_bus.rdata = {12'd0, status};
+ end
end
- always_ff @(posedge sys.clk) begin
- bus.ack <= 1'b0;
-
- if (sys.reset) begin
- bus_state <= S_IDLE;
- flashram_state <= FS_STATUS;
- flashram_status <= 4'b0000;
- flashram_erase_enabled <= 1'b0;
- flashram.operation_pending <= 1'b0;
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ state <= STATE_STATUS;
+ status <= 4'b0000;
+ erase_enabled <= 1'b0;
+ n64_scb.flashram_pending <= 1'b0;
end else begin
- if (flashram.operation_done) begin
- flashram.operation_pending <= 1'b0;
- if (flashram.write_or_erase) begin
- flashram_status[B_ERASE_BUSY] <= 1'b0;
- flashram_status[B_ERASE_DONE] <= 1'b1;
+ if (n64_scb.flashram_done) begin
+ n64_scb.flashram_pending <= 1'b0;
+ if (n64_scb.flashram_write_or_erase) begin
+ status[ERASE_BUSY] <= 1'b0;
+ status[ERASE_DONE] <= 1'b1;
end else begin
- flashram_status[B_WRITE_BUSY] <= 1'b0;
- flashram_status[B_WRITE_DONE] <= 1'b1;
+ status[WRITE_BUSY] <= 1'b0;
+ status[WRITE_DONE] <= 1'b1;
end
end
- case (bus_state)
- S_IDLE: begin
- if (bus.request) begin
- bus_state <= S_WAIT;
- bus.ack <= 1'b1;
- if (bus.write && !flashram.operation_pending) begin
- if (bus.address[16]) begin
- if (!bus.address[1]) begin
- flashram_command <= bus.wdata[15:8];
- end else begin
- flashram_erase_enabled <= 1'b0;
+ if (reg_bus.write && !n64_scb.flashram_pending) begin
+ if (reg_bus.address[16]) begin
+ if (!reg_bus.address[1]) begin
+ cmd <= reg_bus.wdata[15:8];
+ end else begin
+ erase_enabled <= 1'b0;
- case (flashram_command)
- CMD_STATUS_MODE: begin
- flashram_state <= FS_STATUS;
- end
+ case (cmd)
+ CMD_STATUS_MODE: begin
+ state <= STATE_STATUS;
+ end
- CMD_READID_MODE: begin
- flashram_state <= FS_ID;
- end
+ CMD_READID_MODE: begin
+ state <= STATE_ID;
+ end
- CMD_READ_MODE: begin
- flashram_state <= FS_READ;
- end
+ CMD_READ_MODE: begin
+ state <= STATE_READ;
+ end
- CMD_ERASE_SECTOR: begin
- flashram_state <= FS_STATUS;
- flashram_erase_enabled <= 1'b1;
- flashram.sector <= bus.wdata[9:0];
- flashram.sector_or_all <= 1'b0;
- end
+ CMD_ERASE_SECTOR: begin
+ state <= STATE_STATUS;
+ erase_enabled <= 1'b1;
+ n64_scb.flashram_sector <= reg_bus.wdata[9:0];
+ n64_scb.flashram_sector_or_all <= 1'b0;
+ end
- CMD_ERASE_CHIP: begin
- flashram_state <= FS_STATUS;
- flashram_erase_enabled <= 1'b1;
- flashram.sector <= 10'd0;
- flashram.sector_or_all <= 1'b1;
- end
+ CMD_ERASE_CHIP: begin
+ state <= STATE_STATUS;
+ erase_enabled <= 1'b1;
+ n64_scb.flashram_sector <= 10'd0;
+ n64_scb.flashram_sector_or_all <= 1'b1;
+ end
- CMD_BUFFER_MODE: begin
- flashram_state <= FS_BUFFER;
- end
+ CMD_BUFFER_MODE: begin
+ state <= STATE_BUFFER;
+ end
- CMD_ERASE_START: begin
- flashram_state <= FS_STATUS;
- if (flashram_erase_enabled) begin
- flashram_status[B_ERASE_BUSY] <= 1'b1;
- flashram_status[B_ERASE_DONE] <= 1'b0;
- flashram.operation_pending <= 1'b1;
- flashram.write_or_erase <= 1'b1;
- end
- end
-
- CMD_WRITE_START: begin
- flashram_state <= FS_STATUS;
- flashram_status[B_WRITE_BUSY] <= 1'b1;
- flashram_status[B_WRITE_DONE] <= 1'b0;
- flashram.sector <= bus.wdata[9:0];
- flashram.operation_pending <= 1'b1;
- flashram.write_or_erase <= 1'b0;
- flashram.sector_or_all <= 1'b0;
- end
- endcase
- end
- end else begin
- if (bus.address[1] && flashram_state == FS_STATUS) begin
- flashram_status[B_ERASE_BUSY] <= bus.wdata[B_ERASE_BUSY];
- flashram_status[B_WRITE_BUSY] <= bus.wdata[B_WRITE_BUSY];
+ CMD_ERASE_START: begin
+ state <= STATE_STATUS;
+ if (erase_enabled) begin
+ status[ERASE_BUSY] <= 1'b1;
+ status[ERASE_DONE] <= 1'b0;
+ n64_scb.flashram_pending <= 1'b1;
+ n64_scb.flashram_write_or_erase <= 1'b1;
end
end
- end
+
+ CMD_WRITE_START: begin
+ state <= STATE_STATUS;
+ status[WRITE_BUSY] <= 1'b1;
+ status[WRITE_DONE] <= 1'b0;
+ n64_scb.flashram_sector <= reg_bus.wdata[9:0];
+ n64_scb.flashram_pending <= 1'b1;
+ n64_scb.flashram_write_or_erase <= 1'b0;
+ n64_scb.flashram_sector_or_all <= 1'b0;
+ end
+ endcase
+ end
+ end else begin
+ if (state == STATE_BUFFER) begin
+ write_buffer[reg_bus.address[6:1]] <= reg_bus.wdata;
+ end else if (reg_bus.address[1]) begin
+ status[ERASE_BUSY] <= reg_bus.wdata[ERASE_BUSY];
+ status[WRITE_BUSY] <= reg_bus.wdata[WRITE_BUSY];
end
end
-
- S_WAIT: begin
- bus_state <= S_IDLE;
- end
- endcase
+ end
end
end
diff --git a/fw/rtl/n64/n64_pi.sv b/fw/rtl/n64/n64_pi.sv
index 517cf77..fdd096e 100644
--- a/fw/rtl/n64/n64_pi.sv
+++ b/fw/rtl/n64/n64_pi.sv
@@ -1,8 +1,14 @@
module n64_pi (
- if_system.sys sys,
- if_config.pi cfg,
- if_n64_bus.n64 bus,
+ input clk,
+ input reset,
+ mem_bus.controller mem_bus,
+ n64_reg_bus.controller reg_bus,
+
+ n64_scb.pi n64_scb,
+
+ input n64_reset,
+ input n64_nmi,
input n64_pi_alel,
input n64_pi_aleh,
input n64_pi_read,
@@ -10,79 +16,34 @@ module n64_pi (
inout [15:0] n64_pi_ad
);
- // FIFOs
-
- logic read_fifo_flush;
-
- logic read_fifo_full;
- logic read_fifo_write;
- logic [15:0] read_fifo_wdata;
-
- logic read_fifo_empty;
- logic read_fifo_read;
- logic [15:0] read_fifo_rdata;
-
- n64_pi_fifo read_fifo_inst (
- .sys(sys),
-
- .flush(read_fifo_flush),
-
- .full(read_fifo_full),
- .write(read_fifo_write),
- .wdata(read_fifo_wdata),
-
- .empty(read_fifo_empty),
- .read(read_fifo_read),
- .rdata(read_fifo_rdata)
- );
-
- logic write_fifo_flush;
-
- logic write_fifo_full;
- logic write_fifo_write;
- logic [15:0] write_fifo_wdata;
-
- logic write_fifo_empty;
- logic write_fifo_read;
- logic [15:0] write_fifo_rdata;
-
- n64_pi_fifo write_fifo_inst (
- .sys(sys),
-
- .flush(write_fifo_flush),
-
- .full(write_fifo_full),
- .write(write_fifo_write),
- .wdata(write_fifo_wdata),
-
- .empty(write_fifo_empty),
- .read(write_fifo_read),
- .rdata(write_fifo_rdata)
- );
-
-
// Control signals and input synchronization
+ logic [1:0] n64_reset_ff;
+ logic [1:0] n64_nmi_ff;
logic [2:0] n64_pi_alel_ff;
logic [2:0] n64_pi_aleh_ff;
- logic [2:0] n64_pi_read_ff;
+ logic [1:0] n64_pi_read_ff;
logic [2:0] n64_pi_write_ff;
- always_ff @(posedge sys.clk) begin
+ always_ff @(posedge clk) begin
+ n64_reset_ff <= {n64_reset_ff[0], n64_reset};
+ n64_nmi_ff <= {n64_nmi_ff[0], n64_nmi};
n64_pi_aleh_ff <= {n64_pi_aleh_ff[1:0], n64_pi_aleh};
n64_pi_alel_ff <= {n64_pi_alel_ff[1:0], n64_pi_alel};
- n64_pi_read_ff <= {n64_pi_read_ff[1:0], n64_pi_read};
+ n64_pi_read_ff <= {n64_pi_read_ff[0], n64_pi_read};
n64_pi_write_ff <= {n64_pi_write_ff[1:0], n64_pi_write};
end
logic pi_reset;
+ logic pi_nmi;
logic pi_aleh;
logic pi_alel;
logic pi_read;
logic pi_write;
always_comb begin
- pi_reset = sys.n64_hard_reset;
+ pi_reset = n64_reset_ff[1];
+ pi_nmi = n64_nmi_ff[1];
pi_aleh = n64_pi_aleh_ff[2];
pi_alel = n64_pi_alel_ff[2];
pi_read = n64_pi_read_ff[1];
@@ -99,16 +60,30 @@ module n64_pi (
PI_MODE_VALID = 2'b00
} e_pi_mode;
+ typedef enum bit [1:0] {
+ PORT_NONE,
+ PORT_MEM,
+ PORT_REG
+ } e_port;
+
e_pi_mode pi_mode;
- e_pi_mode last_pi_mode;
- logic last_read;
- logic last_write;
+
+ e_port read_port;
+ e_port write_port;
always_comb begin
pi_mode = e_pi_mode'({pi_aleh, pi_alel});
end
- always_ff @(posedge sys.clk) begin
+ logic last_reset;
+ logic last_nmi;
+ e_pi_mode last_pi_mode;
+ logic last_read;
+ logic last_write;
+
+ always_ff @(posedge clk) begin
+ last_reset <= pi_reset;
+ last_nmi <= pi_nmi;
last_pi_mode <= pi_mode;
last_read <= pi_read;
last_write <= pi_write;
@@ -121,236 +96,339 @@ module n64_pi (
logic end_op;
always_comb begin
- aleh_op = !pi_reset && last_pi_mode != PI_MODE_HIGH && pi_mode == PI_MODE_HIGH;
- alel_op = !pi_reset && last_pi_mode == PI_MODE_HIGH && pi_mode == PI_MODE_LOW;
- read_op = !pi_reset && pi_mode == PI_MODE_VALID && last_read && !pi_read;
- write_op = !pi_reset && pi_mode == PI_MODE_VALID && last_write && !pi_write;
- end_op = !pi_reset && last_pi_mode == PI_MODE_VALID && pi_mode != PI_MODE_VALID;
+ n64_scb.n64_reset = !last_reset && pi_reset;
+ n64_scb.n64_nmi = !last_nmi && pi_nmi;
+ aleh_op = pi_reset && (last_pi_mode != PI_MODE_HIGH) && (pi_mode == PI_MODE_HIGH);
+ alel_op = pi_reset && (last_pi_mode == PI_MODE_HIGH) && (pi_mode == PI_MODE_LOW);
+ read_op = pi_reset && (pi_mode == PI_MODE_VALID) && (read_port != PORT_NONE) && (last_read && !pi_read);
+ write_op = pi_reset && (pi_mode == PI_MODE_VALID) && (write_port != PORT_NONE) && (last_write && !pi_write);
+ end_op = pi_reset && (last_pi_mode == PI_MODE_VALID) && (pi_mode != PI_MODE_VALID);
end
// Input and output data sampling
- logic [15:0] n64_pi_ad_input;
- logic [15:0] n64_pi_ad_output;
- logic [15:0] n64_pi_ad_output_data;
- logic n64_pi_ad_output_enable;
- logic n64_pi_ad_output_enable_data;
-
- logic n64_pi_address_valid;
- logic pending_operation;
- logic pending_write;
+ logic n64_pi_ad_oe;
+ logic [15:0] n64_pi_ad_out;
+ logic [15:0] n64_pi_dq_in;
+ logic [15:0] n64_pi_dq_out;
- always_comb begin
- n64_pi_ad = n64_pi_ad_output_enable ? n64_pi_ad_output : 16'hZZZZ;
- n64_pi_ad_output_enable_data = !pi_reset && pi_mode == PI_MODE_VALID && n64_pi_address_valid && !n64_pi_read_ff[2];
- end
+ assign n64_pi_ad = n64_pi_ad_oe ? n64_pi_ad_out : 16'hZZZZ;
- always_ff @(posedge sys.clk) begin
- n64_pi_ad_input <= n64_pi_ad;
- n64_pi_ad_output <= n64_pi_ad_output_data;
- n64_pi_ad_output_enable <= n64_pi_ad_output_enable_data;
- end
-
- logic wait_for_read_fifo;
- logic wait_for_write_fifo;
-
- always_comb begin
- read_fifo_write = bus.ack && !bus.write;
- read_fifo_wdata = bus.rdata;
-
- write_fifo_wdata = n64_pi_ad_input;
- end
-
- always_ff @(posedge sys.clk) begin
- read_fifo_read <= 1'b0;
- write_fifo_write <= 1'b0;
-
- if (sys.reset || sys.n64_hard_reset) begin
- wait_for_read_fifo <= 1'b0;
- wait_for_write_fifo <= 1'b0;
- end else if (n64_pi_address_valid) begin
- if (read_op || wait_for_read_fifo) begin
- if (read_fifo_empty) begin
- wait_for_read_fifo <= 1'b1;
- end else begin
- n64_pi_ad_output_data <= read_fifo_rdata;
- read_fifo_read <= 1'b1;
- wait_for_read_fifo <= 1'b0;
- end
- end
- if (write_op || wait_for_write_fifo) begin
- if (write_fifo_full) begin
- wait_for_write_fifo <= 1'b1;
- end else begin
- write_fifo_write <= 1'b1;
- wait_for_write_fifo <= 1'b0;
- end
- end
- end
- end
-
- always_comb begin
- bus.read_op = read_op;
- bus.write_op = write_op;
- end
-
- always_ff @(posedge sys.clk) begin
- if (aleh_op) begin
- bus.real_address[31:16] <= n64_pi_ad_input;
- end
- if (alel_op) begin
- bus.real_address[15:0] <= {n64_pi_ad_input[15:1], 1'b0};
- end
- if (read_op || write_op) begin
- bus.real_address <= bus.real_address + 2'd2;
- end
+ always_ff @(posedge clk) begin
+ n64_pi_ad_oe <= pi_reset && (pi_mode == PI_MODE_VALID) && !last_read && (read_port != PORT_NONE);
+ n64_pi_ad_out <= n64_pi_dq_out;
+ n64_pi_dq_in <= n64_pi_ad;
end
// Address decoding
- const bit [31:0] DDIPL_OFFSET = 32'h0780_0000;
- const bit [31:0] BUFFERS_OFFSET = 32'h07C0_0000;
- const bit [31:0] SAVE_OFFSET = 32'h07EE_0000;
+ const bit [31:0] DDIPL_OFFSET = 32'h03BC_0000;
+ const bit [31:0] SAVE_OFFSET = 32'h03FC_0000;
+ const bit [31:0] BUFFER_OFFSET = 32'h03FE_0000;
+ const bit [31:0] FLASH_OFFSET = 32'h0400_0000;
+ const bit [31:0] BOOTLOADER_OFFSET = 32'h04E0_0000;
+ const bit [31:0] SHADOW_OFFSET = 32'h04FC_0000;
- sc64::e_n64_id next_id;
- logic [31:0] next_offset;
- logic sram_selected;
+ logic [31:0] mem_offset;
- always_ff @(posedge sys.clk) begin
- if (aleh_op) begin
- n64_pi_address_valid <= 1'b0;
- next_id <= sc64::__ID_N64_END;
- next_offset <= 32'd0;
- sram_selected <= 1'b0;
- if (cfg.dd_enabled) begin
- if (n64_pi_ad_input == 16'h0500) begin
- n64_pi_address_valid <= 1'b1;
- next_id <= sc64::ID_N64_DD;
- next_offset <= (-32'h0500_0000);
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ read_port <= PORT_NONE;
+ write_port <= PORT_NONE;
+ reg_bus.dd_select <= 1'b0;
+ reg_bus.flashram_select <= 1'b0;
+ reg_bus.cfg_select <= 1'b0;
+ end else if (aleh_op) begin
+ read_port <= PORT_NONE;
+ write_port <= PORT_NONE;
+ mem_offset <= 32'd0;
+ reg_bus.dd_select <= 1'b0;
+ reg_bus.flashram_select <= 1'b0;
+ reg_bus.cfg_select <= 1'b0;
+
+ if (n64_scb.dd_enabled) begin
+ if (n64_pi_dq_in == 16'h0500) begin
+ read_port <= PORT_REG;
+ write_port <= PORT_REG;
+ reg_bus.dd_select <= 1'b1;
end
- if (n64_pi_ad_input >= 16'h0600 && n64_pi_ad_input < 16'h0640) begin
- n64_pi_address_valid <= 1'b1;
- next_id <= sc64::ID_N64_SDRAM;
- next_offset <= (-32'h0600_0000) + DDIPL_OFFSET;
+ if (n64_pi_dq_in >= 16'h0600 && n64_pi_dq_in < 16'h0640) begin
+ read_port <= PORT_MEM;
+ write_port <= PORT_NONE;
+ mem_offset <= (-32'h0600_0000) + DDIPL_OFFSET;
end
end
- if (cfg.flashram_enabled) begin
- if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0802) begin
- n64_pi_address_valid <= 1'b1;
- next_id <= sc64::ID_N64_FLASHRAM;
- if (cfg.flashram_read_mode) begin
- next_offset <= (-32'h0800_0000) + SAVE_OFFSET;
+
+ if (n64_scb.flashram_enabled) begin
+ if (n64_pi_dq_in >= 16'h0800 && n64_pi_dq_in < 16'h0802) begin
+ read_port <= PORT_REG;
+ write_port <= PORT_REG;
+ mem_offset <= (-32'h0800_0000) + SAVE_OFFSET;
+ reg_bus.flashram_select <= 1'b1;
+ if (n64_scb.flashram_read_mode) begin
+ read_port <= PORT_MEM;
end
end
- end else if (cfg.sram_enabled) begin
- if (cfg.sram_banked) begin
- if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0810) begin
- if (n64_pi_ad_input[3:2] != 2'b11 && n64_pi_ad_input[1:0] == 2'b00) begin
- n64_pi_address_valid <= 1'b1;
- next_id <= sc64::ID_N64_SDRAM;
- next_offset <= (-32'h0800_0000) - {n64_pi_ad_input[3:2], 18'd0} + {n64_pi_ad_input[3:2], 15'd0} + SAVE_OFFSET;
- sram_selected <= 1'b1;
+ end else if (n64_scb.sram_enabled) begin
+ if (n64_scb.sram_banked) begin
+ if (n64_pi_dq_in >= 16'h0800 && n64_pi_dq_in < 16'h0810) begin
+ if (n64_pi_dq_in[3:2] != 2'b11 && n64_pi_dq_in[1:0] == 2'b00) begin
+ read_port <= PORT_MEM;
+ write_port <= PORT_MEM;
+ mem_offset <= (-32'h0800_0000) - {n64_pi_dq_in[3:2], 18'd0} + {n64_pi_dq_in[3:2], 15'd0} + SAVE_OFFSET;
end
end
end else begin
- if (n64_pi_ad_input == 16'h0800) begin
- n64_pi_address_valid <= 1'b1;
- next_id <= sc64::ID_N64_SDRAM;
- next_offset <= (-32'h0800_0000) + SAVE_OFFSET;
- sram_selected <= 1'b1;
+ if (n64_pi_dq_in >= 16'h0800 && n64_pi_dq_in < 16'h0802) begin
+ read_port <= PORT_MEM;
+ write_port <= PORT_MEM;
+ mem_offset <= (-32'h0800_0000) + SAVE_OFFSET;
end
end
end
- if (n64_pi_ad_input >= 16'h1000 && n64_pi_ad_input < 16'h1800) begin
- n64_pi_address_valid <= 1'b1;
- next_id <= cfg.sdram_switch ? sc64::ID_N64_SDRAM : sc64::ID_N64_BOOTLOADER;
- next_offset <= (-32'h1000_0000);
+
+ if (n64_scb.bootloader_enabled) begin
+ if (n64_pi_dq_in >= 16'h1000 && n64_pi_dq_in < 16'h101C) begin
+ read_port <= PORT_MEM;
+ write_port <= PORT_NONE;
+ mem_offset <= (-32'h1000_0000) + BOOTLOADER_OFFSET;
+ end
+ end else begin
+ if (n64_pi_dq_in >= 16'h1000 && n64_pi_dq_in < 16'h1400) begin
+ read_port <= PORT_MEM;
+ write_port <= n64_scb.rom_write_enabled ? PORT_MEM : PORT_NONE;
+ mem_offset <= (-32'h1000_0000);
+ end
end
- if (n64_pi_ad_input >= 16'h1F80 && n64_pi_ad_input < 16'h1FC0) begin
- n64_pi_address_valid <= 1'b1;
- next_id <= sc64::ID_N64_SDRAM;
- next_offset <= (-32'h1F80_0000) + BUFFERS_OFFSET;
+
+ if (n64_scb.rom_shadow_enabled) begin
+ if (n64_pi_dq_in >= 16'h13FC && n64_pi_dq_in < 16'h1400) begin
+ read_port <= PORT_MEM;
+ write_port <= PORT_NONE;
+ mem_offset <= (-32'h13FC_0000) + SHADOW_OFFSET;
+ end
end
- if (n64_pi_ad_input == 16'h1FFF) begin
- n64_pi_address_valid <= 1'b1;
- next_id <= sc64::ID_N64_CFG;
+
+ if (n64_pi_dq_in >= 16'h1400 && n64_pi_dq_in < 16'h14E0) begin
+ read_port <= PORT_MEM;
+ write_port <= PORT_NONE;
+ mem_offset <= (-32'h1400_0000) + FLASH_OFFSET;
+ end
+
+ if (n64_pi_dq_in >= 16'h1FFC && n64_pi_dq_in < 16'h1FFE) begin
+ read_port <= PORT_MEM;
+ write_port <= PORT_MEM;
+ mem_offset <= (-32'h1FFC_0000) + BUFFER_OFFSET;
+ end
+
+ if (n64_pi_dq_in >= 16'h1FFE && n64_pi_dq_in < 16'h2000) begin
+ read_port <= PORT_REG;
+ write_port <= PORT_REG;
+ reg_bus.cfg_select <= 1'b1;
end
end
end
- // Bus controller
+ // Mem bus read FIFO controller
+
+ logic read_fifo_full;
+ logic read_fifo_write;
+ logic [15:0] read_fifo_wdata;
+
+ logic read_fifo_empty;
+ logic read_fifo_read;
+ logic [15:0] read_fifo_rdata;
+
+ logic read_fifo_wait;
+
+ n64_pi_fifo read_fifo_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .flush(reset || !pi_reset || alel_op),
+
+ .full(read_fifo_full),
+ .write(read_fifo_write),
+ .wdata(read_fifo_wdata),
+
+ .empty(read_fifo_empty),
+ .read(read_fifo_read),
+ .rdata(read_fifo_rdata)
+ );
+
+ always_ff @(posedge clk) begin
+ read_fifo_read <= 1'b0;
+
+ if (reset || !pi_reset || alel_op) begin
+ read_fifo_wait <= 1'b0;
+ end
+
+ if (read_port == PORT_MEM) begin
+ if (read_op) begin
+ if (read_fifo_empty) begin
+ read_fifo_wait <= 1'b1;
+ end else begin
+ read_fifo_read <= 1'b1;
+ n64_pi_dq_out <= read_fifo_rdata;
+ end
+ end
+
+ if (!read_fifo_empty && read_fifo_wait) begin
+ read_fifo_read <= 1'b1;
+ read_fifo_wait <= 1'b0;
+ n64_pi_dq_out <= read_fifo_rdata;
+ end
+ end
+
+ if (read_port == PORT_REG) begin
+ if (read_op) begin
+ n64_pi_dq_out <= reg_bus.rdata;
+ end
+ end
+ end
+
+
+ // Mem bus write FIFO controller
+
+ logic write_fifo_full;
+ logic write_fifo_write;
+ logic [15:0] write_fifo_wdata;
+
+ logic write_fifo_empty;
+ logic write_fifo_read;
+ logic [15:0] write_fifo_rdata;
+
+ logic write_fifo_wait;
+
+ n64_pi_fifo write_fifo_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .flush(reset),
+
+ .full(write_fifo_full),
+ .write(write_fifo_write),
+ .wdata(write_fifo_wdata),
+
+ .empty(write_fifo_empty),
+ .read(write_fifo_read),
+ .rdata(write_fifo_rdata)
+ );
+
+ always_ff @(posedge clk) begin
+ write_fifo_write <= 1'b0;
+
+ if (reset) begin
+ write_fifo_wait <= 1'b0;
+ end
+
+ if (write_port == PORT_MEM) begin
+ if (write_op) begin
+ if (write_fifo_full) begin
+ write_fifo_wait <= 1'b1;
+ end else begin
+ write_fifo_write <= 1'b1;
+ write_fifo_wdata <= n64_pi_dq_in;
+ end
+ end
+
+ if (!write_fifo_full && write_fifo_wait) begin
+ write_fifo_write <= 1'b1;
+ write_fifo_wait <= 1'b0;
+ write_fifo_wdata <= n64_pi_dq_in;
+ end
+ end
+ end
+
+
+ // Mem bus controller
- logic can_read;
- logic first_write_op;
- logic load_starting_address;
- sc64::e_n64_id starting_id;
logic [31:0] starting_address;
+ logic load_starting_address;
+ logic read_enabled;
+ logic first_write_op;
- always_ff @(posedge sys.clk) begin
- read_fifo_flush <= 1'b0;
-
+ always_ff @(posedge clk) begin
write_fifo_read <= 1'b0;
+ load_starting_address <= 1'b0;
- if (sys.reset || sys.n64_hard_reset) begin
- bus.request <= 1'b0;
- read_fifo_flush <= 1'b1;
- write_fifo_flush <= 1'b1;
+ if (reset || !pi_reset) begin
+ mem_bus.request <= 1'b0;
+ read_enabled <= 1'b0;
end else begin
- write_fifo_flush <= starting_id == sc64::ID_N64_SDRAM && !cfg.sdram_writable && !sram_selected;
-
if (aleh_op) begin
- starting_address[31:16] <= n64_pi_ad_input;
+ starting_address[31:16] <= n64_pi_dq_in;
end
if (alel_op) begin
- read_fifo_flush <= 1'b1;
- can_read <= 1'b1;
- first_write_op <= 1'b1;
+ starting_address <= {starting_address[31:16], n64_pi_dq_in} + mem_offset;
load_starting_address <= 1'b1;
- starting_id <= next_id;
- starting_address <= {starting_address[31:16], n64_pi_ad_input[15:1], 1'b0};
+ read_enabled <= 1'b1;
+ first_write_op <= 1'b1;
end
- if (write_op) begin
- can_read <= 1'b0;
- if (first_write_op) begin
- first_write_op <= 1'b0;
- load_starting_address <= 1'b1;
- end
+ if (load_starting_address) begin
+ mem_bus.address <= starting_address;
end
- if (!bus.request) begin
- if (!write_fifo_empty) begin
- bus.request <= 1'b1;
- bus.write <= 1'b1;
- if (load_starting_address) begin
- bus.id <= starting_id;
- bus.address <= starting_address + next_offset;
- load_starting_address <= 1'b0;
- end
- bus.wdata <= write_fifo_rdata;
+ if (!mem_bus.request) begin
+ if ((write_port == PORT_MEM) && !write_fifo_empty) begin
+ mem_bus.request <= 1'b1;
+ mem_bus.write <= 1'b1;
+ mem_bus.wdata <= write_fifo_rdata;
write_fifo_read <= 1'b1;
- end else if (!read_fifo_full && can_read) begin
- bus.request <= 1'b1;
- bus.write <= 1'b0;
- if (load_starting_address) begin
- bus.id <= (starting_id == sc64::ID_N64_FLASHRAM && cfg.flashram_read_mode) ? sc64::ID_N64_SDRAM : starting_id;
- bus.address <= starting_address + next_offset;
- load_starting_address <= 1'b0;
+ read_enabled <= 1'b0;
+ if (first_write_op) begin
+ mem_bus.address <= starting_address;
+ first_write_op <= 1'b0;
end
+ end else if ((read_port == PORT_MEM) && !read_fifo_full && read_enabled) begin
+ mem_bus.request <= 1'b1;
+ mem_bus.write <= 1'b0;
end
- end else if (bus.ack) begin
- bus.request <= 1'b0;
- bus.address <= bus.address + 2'd2;
+ end
+
+ if (mem_bus.ack) begin
+ mem_bus.request <= 1'b0;
+ mem_bus.address[16:0] <= mem_bus.address[16:0] + 2'd2;
end
if (end_op) begin
- can_read <= 1'b0;
+ read_enabled <= 1'b0;
end
end
end
+ always_comb begin
+ read_fifo_write = !mem_bus.write && mem_bus.ack;
+ read_fifo_wdata = mem_bus.rdata;
+ mem_bus.wmask = 2'b11;
+ end
+
+
+ // Reg bus controller
+
+ always_ff @(posedge clk) begin
+ if (aleh_op) begin
+ reg_bus.address[16] <= n64_pi_dq_in[0];
+ end
+
+ if (alel_op) begin
+ reg_bus.address[15:0] <= n64_pi_dq_in;
+ end
+
+ if (read_op || write_op) begin
+ reg_bus.address <= reg_bus.address + 2'd2;
+ end
+ end
+
+ always_comb begin
+ reg_bus.read = read_op && (read_port == PORT_REG);
+ reg_bus.write = write_op && (write_port == PORT_REG);
+ reg_bus.wdata = n64_pi_dq_in;
+ end
+
endmodule
diff --git a/fw/rtl/n64/n64_pi_fifo.sv b/fw/rtl/n64/n64_pi_fifo.sv
index 63dde9e..80c27bd 100644
--- a/fw/rtl/n64/n64_pi_fifo.sv
+++ b/fw/rtl/n64/n64_pi_fifo.sv
@@ -1,5 +1,6 @@
module n64_pi_fifo (
- if_system.sys sys,
+ input clk,
+ input reset,
input flush,
@@ -18,15 +19,13 @@ module n64_pi_fifo (
logic empty_or_full;
- always_comb begin
- rdata = fifo_mem[fifo_rd_ptr[1:0]];
- empty_or_full = fifo_wr_ptr[1:0] == fifo_rd_ptr[1:0];
- empty = empty_or_full && fifo_wr_ptr[2] == fifo_rd_ptr[2];
- full = empty_or_full && fifo_wr_ptr[2] != fifo_rd_ptr[2];
- end
+ assign rdata = fifo_mem[fifo_rd_ptr[1:0]];
+ assign empty_or_full = fifo_wr_ptr[1:0] == fifo_rd_ptr[1:0];
+ assign empty = empty_or_full && fifo_wr_ptr[2] == fifo_rd_ptr[2];
+ assign full = empty_or_full && fifo_wr_ptr[2] != fifo_rd_ptr[2];
- always_ff @(posedge sys.clk) begin
- if (sys.reset || flush) begin
+ always_ff @(posedge clk) begin
+ if (reset || flush) begin
fifo_wr_ptr <= 3'd0;
fifo_rd_ptr <= 3'd0;
end else begin
diff --git a/fw/rtl/n64/n64_reg_bus.sv b/fw/rtl/n64/n64_reg_bus.sv
new file mode 100644
index 0000000..7e59f42
--- /dev/null
+++ b/fw/rtl/n64/n64_reg_bus.sv
@@ -0,0 +1,66 @@
+interface n64_reg_bus ();
+
+ logic dd_select;
+ logic flashram_select;
+ logic cfg_select;
+
+ logic read;
+ logic write;
+ logic [16:0] address;
+ logic [15:0] rdata;
+ logic [15:0] wdata;
+
+ logic [15:0] dd_rdata;
+ logic [15:0] flashram_rdata;
+ logic [15:0] cfg_rdata;
+
+ modport controller (
+ output dd_select,
+ output flashram_select,
+ output cfg_select,
+
+ output read,
+ output write,
+ output address,
+ input rdata,
+ output wdata
+ );
+
+ always_comb begin
+ rdata = 16'd0;
+ if (dd_select) begin
+ rdata = dd_rdata;
+ end
+ if (flashram_select) begin
+ rdata = flashram_rdata;
+ end
+ if (cfg_select) begin
+ rdata = cfg_rdata;
+ end
+ end
+
+ modport dd (
+ input .read(read && dd_select),
+ input .write(write && dd_select),
+ input address,
+ output .rdata(dd_rdata),
+ input wdata
+ );
+
+ modport flashram (
+ input .read(read && flashram_select),
+ input .write(write && flashram_select),
+ input address,
+ output .rdata(flashram_rdata),
+ input wdata
+ );
+
+ modport cfg (
+ input .read(read && cfg_select),
+ input .write(write && cfg_select),
+ input address,
+ output .rdata(cfg_rdata),
+ input wdata
+ );
+
+endinterface
diff --git a/fw/rtl/n64/n64_scb.sv b/fw/rtl/n64/n64_scb.sv
new file mode 100644
index 0000000..2bed127
--- /dev/null
+++ b/fw/rtl/n64/n64_scb.sv
@@ -0,0 +1,141 @@
+interface n64_scb ();
+
+ logic n64_reset;
+ logic n64_nmi;
+
+ logic bootloader_enabled;
+ logic rom_write_enabled;
+ logic rom_shadow_enabled;
+ logic sram_enabled;
+ logic sram_banked;
+ logic flashram_enabled;
+ logic flashram_read_mode;
+ logic dd_enabled;
+ logic eeprom_enabled;
+ logic eeprom_16k_mode;
+
+ logic flashram_pending;
+ logic flashram_done;
+ logic [9:0] flashram_sector;
+ logic flashram_sector_or_all;
+ logic flashram_write_or_erase;
+ logic [5:0] flashram_buffer_address;
+ logic [15:0] flashram_buffer_rdata;
+
+ logic cfg_pending;
+ logic cfg_done;
+ logic cfg_error;
+ logic cfg_irq;
+ logic [7:0] cfg_cmd;
+ logic [31:0] cfg_rdata [0:1];
+ logic [31:0] cfg_wdata [0:1];
+ logic [31:0] cfg_version;
+
+ logic eeprom_write;
+ logic [10:0] eeprom_address;
+ logic [7:0] eeprom_rdata;
+ logic [7:0] eeprom_wdata;
+
+ logic rtc_pending;
+ logic rtc_done;
+ logic [41:0] rtc_rdata;
+ logic [41:0] rtc_wdata;
+
+ modport controller (
+ input n64_reset,
+ input n64_nmi,
+
+ output bootloader_enabled,
+ output rom_write_enabled,
+ output rom_shadow_enabled,
+ output sram_enabled,
+ output sram_banked,
+ output flashram_enabled,
+ output dd_enabled,
+ output eeprom_enabled,
+ output eeprom_16k_mode,
+
+ input flashram_pending,
+ output flashram_done,
+ input flashram_sector,
+ input flashram_sector_or_all,
+ input flashram_write_or_erase,
+ output flashram_buffer_address,
+ input flashram_buffer_rdata,
+
+ input cfg_pending,
+ output cfg_done,
+ output cfg_error,
+ output cfg_irq,
+ input cfg_cmd,
+ input cfg_rdata,
+ output cfg_wdata,
+ output cfg_version,
+
+ output eeprom_write,
+ output eeprom_address,
+ input eeprom_rdata,
+ output eeprom_wdata,
+
+ input rtc_pending,
+ output rtc_done,
+ input rtc_rdata,
+ output rtc_wdata
+ );
+
+ modport pi (
+ output n64_reset,
+ output n64_nmi,
+
+ input bootloader_enabled,
+ input rom_write_enabled,
+ input rom_shadow_enabled,
+ input sram_enabled,
+ input sram_banked,
+ input flashram_enabled,
+ input flashram_read_mode,
+ input dd_enabled
+ );
+
+ // modport dd (
+
+ // );
+
+ modport flashram (
+ output flashram_read_mode,
+ output flashram_pending,
+ input flashram_done,
+ output flashram_sector,
+ output flashram_sector_or_all,
+ output flashram_write_or_erase,
+ input flashram_buffer_address,
+ output flashram_buffer_rdata
+ );
+
+ modport cfg (
+ output cfg_pending,
+ input cfg_done,
+ input cfg_error,
+ input cfg_irq,
+ output cfg_cmd,
+ output cfg_rdata,
+ input cfg_wdata,
+ input cfg_version
+ );
+
+ modport si (
+ input eeprom_enabled,
+ input eeprom_16k_mode,
+
+ input eeprom_write,
+ input eeprom_address,
+ output eeprom_rdata,
+ input eeprom_wdata,
+
+ output rtc_pending,
+ input rtc_done,
+ output rtc_rdata,
+ input rtc_wdata
+ );
+
+endinterface
diff --git a/fw/rtl/n64/n64_sdram.sv b/fw/rtl/n64/n64_sdram.sv
deleted file mode 100644
index e95eb2e..0000000
--- a/fw/rtl/n64/n64_sdram.sv
+++ /dev/null
@@ -1,90 +0,0 @@
-module n64_sdram (
- if_system sys,
- if_n64_bus bus,
- if_memory_dma.memory usb_dma,
- if_sdram.memory sdram,
-
- output sdram_cs,
- output sdram_ras,
- output sdram_cas,
- output sdram_we,
- output [1:0] sdram_ba,
- output [12:0] sdram_a,
- inout [15:0] sdram_dq
-);
-
- logic mem_request;
- logic mem_ack;
- logic mem_write;
- logic [31:0] mem_address;
- logic [15:0] mem_rdata;
- logic [15:0] mem_wdata;
-
- typedef enum bit [1:0] {
- T_BUS,
- T_SDRAM,
- T_USB_DMA
- } e_source_request;
-
- e_source_request source_request;
-
- always_ff @(posedge sys.clk) begin
- if (sys.reset) begin
- mem_request <= 1'b0;
- end else begin
- if (!mem_request && (bus.request || sdram.request || usb_dma.request)) begin
- mem_request <= 1'b1;
- if (bus.request) begin
- mem_write <= bus.write;
- mem_address <= bus.address;
- mem_wdata <= bus.wdata;
- source_request <= T_BUS;
- end else if (sdram.request) begin
- mem_write <= sdram.write;
- mem_address <= sdram.address;
- mem_wdata <= sdram.wdata;
- source_request <= T_SDRAM;
- end else if (usb_dma.request) begin
- mem_write <= usb_dma.write;
- mem_address <= usb_dma.address;
- mem_wdata <= usb_dma.wdata;
- source_request <= T_USB_DMA;
- end
- end
- if (mem_ack) begin
- mem_request <= 1'b0;
- end
- end
- end
-
- always_comb begin
- bus.ack = source_request == T_BUS && mem_ack;
- bus.rdata = bus.ack ? mem_rdata : 16'd0;
-
- sdram.ack = source_request == T_SDRAM && mem_ack;
- sdram.rdata = mem_rdata;
-
- usb_dma.ack = source_request == T_USB_DMA && mem_ack;
- usb_dma.rdata = mem_rdata;
- end
-
- memory_sdram memory_sdram_inst (
- .sys(sys),
-
- .request(mem_request),
- .ack(mem_ack),
- .write(mem_write),
- .address(mem_address[25:0]),
- .rdata(mem_rdata),
- .wdata(mem_wdata),
-
- .sdram_cs(sdram_cs),
- .sdram_ras(sdram_ras),
- .sdram_cas(sdram_cas),
- .sdram_we(sdram_we),
- .sdram_ba(sdram_ba),
- .sdram_a(sdram_a),
- .sdram_dq(sdram_dq)
- );
-
-endmodule
diff --git a/fw/rtl/n64/n64_si.sv b/fw/rtl/n64/n64_si.sv
index 6ecac5d..abac4e3 100644
--- a/fw/rtl/n64/n64_si.sv
+++ b/fw/rtl/n64/n64_si.sv
@@ -1,164 +1,253 @@
-interface if_si ();
-
- logic rx_reset;
- logic rx_ready;
- logic [6:0] rx_length;
- logic [80:0] rx_data;
-
- logic tx_reset;
- logic tx_start;
- logic tx_busy;
- logic [2:0] tx_wmask;
- logic [6:0] tx_length;
- logic [31:0] tx_data;
-
- modport si (
- input rx_reset,
- output rx_ready,
- output rx_length,
- output rx_data,
- input tx_reset,
- input tx_start,
- output tx_busy,
- input tx_wmask,
- input tx_length,
- input tx_data
- );
-
- modport cpu (
- output rx_reset,
- input rx_ready,
- input rx_length,
- input rx_data,
- output tx_reset,
- output tx_start,
- input tx_busy,
- output tx_wmask,
- output tx_length,
- output tx_data
- );
-
-endinterface
-
module n64_si (
- if_system.sys sys,
- if_si.si si,
+ input clk,
+ input reset,
+ n64_scb.si n64_scb,
+
+ input n64_reset,
input n64_si_clk,
inout n64_si_dq
);
- // Control signals and input synchronization
+ // Input/output synchronization
+ logic [1:0] n64_reset_ff;
logic [1:0] n64_si_clk_ff;
- always_ff @(posedge sys.clk) begin
+ always_ff @(posedge clk) begin
+ n64_reset_ff <= {n64_reset_ff[0], n64_reset};
n64_si_clk_ff <= {n64_si_clk_ff[0], n64_si_clk};
end
logic si_reset;
logic si_clk;
- logic si_dq;
always_comb begin
- si_reset = sys.n64_hard_reset;
+ si_reset = n64_reset_ff[1];
si_clk = n64_si_clk_ff[1];
- si_dq = n64_si_dq;
end
+ logic si_dq_oe;
+ logic si_dq_out;
+ logic si_dq_in;
+
+ assign n64_si_dq = si_dq_oe ? 1'b0 : 1'bZ;
+
+ always_ff @(posedge clk) begin
+ si_dq_oe <= ~si_dq_out;
+ si_dq_in <= n64_si_dq;
+ end
+
+
+ // Clock falling/rising event generator
+
logic last_si_clk;
- always_ff @(posedge sys.clk) begin
+ always_ff @(posedge clk) begin
last_si_clk <= si_clk;
end
- logic si_clk_rising_edge;
logic si_clk_falling_edge;
+ logic si_clk_rising_edge;
always_comb begin
- si_clk_rising_edge = !si_reset && !last_si_clk && si_clk;
- si_clk_falling_edge = !si_reset && last_si_clk && !si_clk;
- end
-
- logic si_dq_output_enable;
- logic si_dq_output_enable_data;
-
- always_ff @(posedge sys.clk) begin
- si_dq_output_enable <= si_dq_output_enable_data;
- end
-
- always_comb begin
- n64_si_dq = si_dq_output_enable ? 1'b0 : 1'bZ;
+ si_clk_falling_edge = si_reset && last_si_clk && !si_clk;
+ si_clk_rising_edge = si_reset && !last_si_clk && si_clk;
end
- // Data register and shifter
+ // Data falling/rising event generator
- logic [80:0] trx_data;
- logic rx_shift;
- logic tx_shift;
+ logic last_si_dq_in;
- always_comb begin
- si.rx_data = trx_data;
- end
-
- always_ff @(posedge sys.clk) begin
- if (si.tx_wmask[0]) trx_data[80:49] <= si.tx_data;
- if (si.tx_wmask[1]) trx_data[48:17] <= si.tx_data;
- if (si.tx_wmask[2]) trx_data[16:0] <= si.tx_data[16:0];
-
- if (rx_shift || tx_shift) begin
- trx_data <= {trx_data[79:0], rx_sub_bit_counter < 2'd2};
+ always_ff @(posedge clk) begin
+ if (si_clk_rising_edge) begin
+ last_si_dq_in <= si_dq_in;
end
end
+ logic si_dq_falling_edge;
+ logic si_dq_rising_edge;
+
+ always_comb begin
+ si_dq_falling_edge = si_clk_rising_edge && last_si_dq_in && !si_dq_in;
+ si_dq_rising_edge = si_clk_rising_edge && !last_si_dq_in && si_dq_in;
+ end
+
+
+ // RX bit generator
+
+ logic [3:0] rx_sub_bit_counter;
+ logic rx_timeout;
+ logic rx_bit_valid;
+ logic rx_bit_data;
+
+ always_ff @(posedge clk) begin
+ if (si_clk_rising_edge && !(&rx_sub_bit_counter)) begin
+ rx_sub_bit_counter <= rx_sub_bit_counter + 1'd1;
+ end
+ if (si_dq_falling_edge) begin
+ rx_sub_bit_counter <= 4'd0;
+ end
+ end
+
+ always_comb begin
+ rx_timeout = si_clk_rising_edge && si_dq_in && (&rx_sub_bit_counter);
+ rx_bit_valid = si_dq_rising_edge;
+ rx_bit_data = (rx_sub_bit_counter >= 4'd3) ? 1'b0 : 1'b1;
+ end
+
+
+ // RX byte generator
+
+ logic [2:0] rx_bit_counter;
+ logic rx_byte_valid;
+ logic [7:0] rx_byte_data;
+
+ always_ff @(posedge clk) begin
+ rx_byte_valid <= 1'b0;
+ if (rx_timeout) begin
+ rx_bit_counter <= 3'd0;
+ end
+ if (rx_bit_valid) begin
+ rx_bit_counter <= rx_bit_counter + 1'd1;
+ rx_byte_data <= {rx_byte_data[6:0], rx_bit_data};
+ if (&rx_bit_counter) begin
+ rx_byte_valid <= 1'b1;
+ end
+ end
+ end
+
+
+ // RX stop generator
+
+ logic rx_stop;
+
+ always_comb begin
+ rx_stop = si_clk_rising_edge && si_dq_in && (rx_sub_bit_counter == 4'd7) && (rx_bit_counter == 3'd1);
+ end
+
+
+ // TX byte/stop generator
+
+ logic tx_busy;
+ logic [2:0] tx_sub_bit_counter;
+ logic [2:0] tx_bit_counter;
+ logic [7:0] tx_shift;
+ logic tx_start;
+ logic tx_stop;
+ logic tx_byte_valid;
+ logic [7:0] tx_byte_data;
+
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ si_dq_out <= 1'b1;
+ tx_busy <= 1'b0;
+ end else begin
+ if (tx_busy) begin
+ if (si_clk_falling_edge) begin
+ tx_sub_bit_counter <= tx_sub_bit_counter + 1'd1;
+ if (&tx_sub_bit_counter) begin
+ tx_bit_counter <= tx_bit_counter + 1'd1;
+ tx_shift <= {tx_shift[6:0], 1'bX};
+ if (&tx_bit_counter) begin
+ tx_busy <= 1'b0;
+ end
+ end
+ if (tx_shift[7]) begin
+ si_dq_out <= !(tx_sub_bit_counter < 3'd2);
+ end else begin
+ si_dq_out <= !(tx_sub_bit_counter < 3'd6);
+ end
+ end
+ end else begin
+ if (tx_byte_valid) begin
+ tx_busy <= 1'b1;
+ tx_sub_bit_counter <= 3'd0;
+ tx_bit_counter <= 3'd0;
+ tx_shift <= tx_byte_data;
+ end else if (tx_stop) begin
+ tx_busy <= 1'b1;
+ tx_sub_bit_counter <= 3'd0;
+ tx_bit_counter <= 3'd7;
+ tx_shift <= 8'hFF;
+ end
+ end
+ end
+ end
+
+
+ // Joybus CMDs
+
+ typedef enum bit [7:0] {
+ CMD_EEPROM_STATUS = 8'h00,
+ CMD_EEPROM_READ = 8'h04,
+ CMD_EEPROM_WRITE = 8'h05,
+ CMD_RTC_STATUS = 8'h06,
+ CMD_RTC_READ = 8'h07,
+ CMD_RTC_WRITE = 8'h08
+ } e_cmd;
+
+ e_cmd cmd;
+
// RX path
- typedef enum bit [0:0] {
- S_RX_IDLE,
- S_RX_WAITING
+ typedef enum bit [1:0] {
+ RX_STATE_IDLE,
+ RX_STATE_DATA,
+ RX_STATE_IGNORE
} e_rx_state;
e_rx_state rx_state;
+ logic [3:0] rx_byte_counter;
+ logic rx_data_valid;
- logic [1:0] rx_sub_bit_counter;
- logic [3:0] rx_timeout_counter;
+ always_comb begin
+ rx_data_valid = rx_byte_valid && (rx_state == RX_STATE_DATA);
+ end
- always_ff @(posedge sys.clk) begin
- rx_shift <= 1'b0;
+ always_ff @(posedge clk) begin
+ tx_start <= 1'b0;
- if (si_clk_rising_edge) begin
- if (rx_timeout_counter < 4'd8) begin
- rx_timeout_counter <= rx_timeout_counter + 1'd1;
- end else if (si.rx_length > 7'd0) begin
- si.rx_ready <= 1'b1;
- end
+ if (rx_byte_valid) begin
+ rx_byte_counter <= rx_byte_counter + 1'd1;
end
- if (sys.reset || si.rx_reset) begin
- rx_state <= S_RX_IDLE;
- si.rx_ready <= 1'b0;
- si.rx_length <= 7'd0;
- end else if (!si.tx_busy) begin
+ if (reset || rx_timeout) begin
+ rx_state <= RX_STATE_IDLE;
+ end else begin
case (rx_state)
- S_RX_IDLE: begin
- if (si_clk_rising_edge && !si_dq) begin
- rx_state <= S_RX_WAITING;
- rx_sub_bit_counter <= 2'd0;
- rx_timeout_counter <= 3'd0;
+ RX_STATE_IDLE: begin
+ if (rx_byte_valid) begin
+ cmd <= e_cmd'(rx_byte_data);
+ rx_byte_counter <= 4'd0;
+ rx_state <= RX_STATE_IGNORE;
+ case (rx_byte_data)
+ CMD_EEPROM_STATUS,
+ CMD_EEPROM_READ,
+ CMD_EEPROM_WRITE: begin
+ rx_state <= n64_scb.eeprom_enabled ? RX_STATE_DATA : RX_STATE_IGNORE;
+ end
+ CMD_RTC_STATUS,
+ CMD_RTC_READ,
+ CMD_RTC_WRITE: begin
+ rx_state <= RX_STATE_DATA;
+ end
+ endcase
end
end
- S_RX_WAITING: begin
- if (si_clk_rising_edge) begin
- if (si_dq) begin
- rx_state <= S_RX_IDLE;
- rx_shift <= 1'b1;
- si.rx_length <= si.rx_length + 1'd1;
- end else if (rx_sub_bit_counter < 2'd3) begin
- rx_sub_bit_counter <= rx_sub_bit_counter + 1'd1;
- end
+ RX_STATE_DATA: begin
+ if (rx_stop) begin
+ tx_start <= 1'b1;
+ rx_state <= RX_STATE_IGNORE;
+ end
+ end
+
+ RX_STATE_IGNORE: begin
+ if (rx_stop) begin
+ rx_state <= RX_STATE_IDLE;
end
end
endcase
@@ -168,57 +257,227 @@ module n64_si (
// TX path
- typedef enum bit [0:0] {
- S_TX_IDLE,
- S_TX_SENDING
+ typedef enum bit [1:0] {
+ TX_STATE_IDLE,
+ TX_STATE_DATA,
+ TX_STATE_STOP
} e_tx_state;
e_tx_state tx_state;
- logic [2:0] tx_sub_bit_counter;
- logic [6:0] tx_bit_counter;
+ logic [3:0] tx_byte_counter;
+ logic [3:0] tx_length;
- always_ff @(posedge sys.clk) begin
- tx_shift <= 1'b0;
+ always_ff @(posedge clk) begin
+ tx_byte_valid <= 1'b0;
+ tx_stop <= 1'b0;
- if (sys.reset || si.tx_reset) begin
- tx_state <= S_TX_IDLE;
- si_dq_output_enable_data <= 1'b0;
- si.tx_busy <= 1'b0;
+ if (!tx_busy && tx_byte_valid) begin
+ tx_byte_counter <= tx_byte_counter + 1'd1;
+ end
+
+ if (reset) begin
+ tx_state <= TX_STATE_IDLE;
end else begin
case (tx_state)
- S_TX_IDLE: begin
- if (si.tx_start) begin
- tx_state <= S_TX_SENDING;
- tx_sub_bit_counter <= 3'd0;
- tx_bit_counter <= si.tx_length;
- si.tx_busy <= 1'b1;
+ TX_STATE_IDLE: begin
+ if (tx_start) begin
+ tx_byte_counter <= 4'd0;
+ tx_state <= TX_STATE_DATA;
end
end
- S_TX_SENDING: begin
- if (si_clk_falling_edge) begin
- tx_sub_bit_counter <= tx_sub_bit_counter + 1'd1;
- if (tx_sub_bit_counter == 3'd7) begin
- tx_shift <= 1'b1;
- if (tx_bit_counter >= 7'd1) begin
- tx_bit_counter <= tx_bit_counter - 1'd1;
- end else begin
- tx_state <= S_TX_IDLE;
- si.tx_busy <= 1'b0;
- end
- end
- if (tx_bit_counter == 7'd0) begin
- si_dq_output_enable_data <= tx_sub_bit_counter < 3'd4;
- end else if (trx_data[80]) begin
- si_dq_output_enable_data <= tx_sub_bit_counter < 3'd2;
- end else begin
- si_dq_output_enable_data <= tx_sub_bit_counter < 3'd6;
+ TX_STATE_DATA: begin
+ tx_byte_valid <= 1'b1;
+ if (!tx_busy && tx_byte_valid) begin
+ if (tx_byte_counter == tx_length) begin
+ tx_state <= TX_STATE_STOP;
end
end
end
+
+ TX_STATE_STOP: begin
+ tx_stop <= 1'b1;
+ if (!tx_busy && tx_stop) begin
+ tx_state <= TX_STATE_IDLE;
+ end
+ end
endcase
end
end
+
+ // Joybus address latching
+
+ logic [7:0] joybus_address;
+ logic [2:0] joybus_subaddress;
+ logic [10:0] joybus_full_address;
+
+ always_comb begin
+ joybus_full_address = {joybus_address, joybus_subaddress};
+ end
+
+ always_ff @(posedge clk) begin
+ if (rx_data_valid || (!tx_busy && tx_byte_valid)) begin
+ joybus_subaddress <= joybus_subaddress + 1'd1;
+ end
+ if (rx_data_valid) begin
+ if (rx_byte_counter == 4'd0) begin
+ joybus_address <= rx_byte_data;
+ joybus_subaddress <= 3'd0;
+ end
+ end
+ end
+
+
+ // EEPROM controller
+
+ logic [7:0] eeprom_memory [0:2047];
+ logic [7:0] eeprom_data;
+
+ always_ff @(posedge clk) begin
+ eeprom_data <= eeprom_memory[joybus_full_address];
+ n64_scb.eeprom_rdata <= eeprom_memory[n64_scb.eeprom_address];
+ if (rx_data_valid && (cmd == CMD_EEPROM_WRITE)) begin
+ if (rx_byte_counter > 4'd0) begin
+ eeprom_memory[joybus_full_address] <= rx_byte_data;
+ end
+ end
+ if (n64_scb.eeprom_write) begin
+ eeprom_memory[n64_scb.eeprom_address] <= n64_scb.eeprom_wdata;
+ end
+ end
+
+
+ // RTC controller
+
+ logic rtc_backup_wp;
+ logic rtc_time_wp;
+ logic rtc_stopped;
+ logic [6:0] rtc_time_second;
+ logic [6:0] rtc_time_minute;
+ logic [5:0] rtc_time_hour;
+ logic [5:0] rtc_time_day;
+ logic [2:0] rtc_time_weekday;
+ logic [4:0] rtc_time_month;
+ logic [7:0] rtc_time_year;
+
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ rtc_backup_wp <= 1'b1;
+ rtc_time_wp <= 1'b1;
+ rtc_stopped <= 1'b0;
+ n64_scb.rtc_pending <= 1'b0;
+ end
+
+ if (n64_scb.rtc_done) begin
+ n64_scb.rtc_pending <= 1'b0;
+ end
+
+ if (!rtc_stopped && !n64_scb.rtc_pending && (tx_state != TX_STATE_DATA)) begin
+ {
+ rtc_time_year,
+ rtc_time_month,
+ rtc_time_weekday,
+ rtc_time_day,
+ rtc_time_hour,
+ rtc_time_minute,
+ rtc_time_second
+ } <= n64_scb.rtc_wdata;
+ end
+
+ if (rx_data_valid && (cmd == CMD_RTC_WRITE)) begin
+ if (joybus_address[1:0] == 2'd0) begin
+ case (rx_byte_counter)
+ 4'd1: {rtc_time_wp, rtc_backup_wp} <= rx_byte_data[1:0];
+ 4'd2: begin
+ rtc_stopped <= rx_byte_data[2];
+ if (!rx_byte_data[2]) begin
+ n64_scb.rtc_pending <= 1'b1;
+ end
+ end
+ endcase
+ end
+ if ((joybus_address[1:0] == 2'd2) && !rtc_time_wp) begin
+ case (rx_byte_counter)
+ 4'd1: rtc_time_second <= rx_byte_data[6:0];
+ 4'd2: rtc_time_minute <= rx_byte_data[6:0];
+ 4'd3: rtc_time_hour <= rx_byte_data[5:0];
+ 4'd4: rtc_time_day <= rx_byte_data[5:0];
+ 4'd5: rtc_time_weekday <= rx_byte_data[2:0];
+ 4'd6: rtc_time_month <= rx_byte_data[4:0];
+ 4'd7: rtc_time_year <= rx_byte_data;
+ endcase
+ end
+ end
+ end
+
+ always_comb begin
+ n64_scb.rtc_rdata = {
+ rtc_time_year,
+ rtc_time_month,
+ rtc_time_weekday,
+ rtc_time_day,
+ rtc_time_hour,
+ rtc_time_minute,
+ rtc_time_second
+ };
+ end
+
+
+ // TX data multiplexer
+
+ always_comb begin
+ tx_length = 4'd0;
+ tx_byte_data = 8'h00;
+ case (cmd)
+ CMD_EEPROM_STATUS: begin
+ tx_length = 4'd2;
+ case (tx_byte_counter)
+ 4'd1: tx_byte_data = {1'b1, n64_scb.eeprom_16k_mode, 6'd0};
+ endcase
+ end
+ CMD_EEPROM_READ: begin
+ tx_length = 4'd7;
+ tx_byte_data = eeprom_data;
+ end
+ CMD_EEPROM_WRITE: begin
+ tx_length = 4'd0;
+ end
+ CMD_RTC_STATUS: begin
+ tx_length = 4'd2;
+ case (tx_byte_counter)
+ 4'd1: tx_byte_data = 8'h10;
+ 4'd2: tx_byte_data = {rtc_stopped, 7'd0};
+ endcase
+ end
+ CMD_RTC_READ: begin
+ tx_length = 4'd8;
+ if (joybus_address[1:0] == 2'd0) begin
+ case (tx_byte_counter)
+ 4'd0: tx_byte_data = {6'd0, rtc_time_wp, rtc_backup_wp};
+ 4'd1: tx_byte_data = {5'd0, rtc_stopped, 2'd0};
+ 4'd8: tx_byte_data = {rtc_stopped, 7'd0};
+ endcase
+ end else if (joybus_address[1:0] == 2'd2) begin
+ case (tx_byte_counter)
+ 4'd0: tx_byte_data = {1'd0, rtc_time_second};
+ 4'd1: tx_byte_data = {1'd0, rtc_time_minute};
+ 4'd2: tx_byte_data = {2'b10, rtc_time_hour};
+ 4'd3: tx_byte_data = {2'd0, rtc_time_day};
+ 4'd4: tx_byte_data = {5'd0, rtc_time_weekday};
+ 4'd5: tx_byte_data = {3'd0, rtc_time_month};
+ 4'd6: tx_byte_data = rtc_time_year;
+ 4'd7: tx_byte_data = 8'h01;
+ 4'd8: tx_byte_data = {rtc_stopped, 7'd0};
+ endcase
+ end
+ end
+ CMD_RTC_WRITE: begin
+ tx_length = 4'd0;
+ tx_byte_data = {rtc_stopped, 7'd0};
+ end
+ endcase
+ end
+
endmodule
diff --git a/fw/rtl/n64/n64_soc.sv b/fw/rtl/n64/n64_soc.sv
deleted file mode 100644
index 52447b4..0000000
--- a/fw/rtl/n64/n64_soc.sv
+++ /dev/null
@@ -1,97 +0,0 @@
-module n64_soc (
- if_system sys,
- if_config cfg,
- if_memory_dma.memory usb_dma,
- if_sdram.memory sdram,
- if_flashram.flashram flashram,
- if_si.si si,
- if_flash.flash flash,
- if_dd dd,
-
- input n64_pi_alel,
- input n64_pi_aleh,
- input n64_pi_read,
- input n64_pi_write,
- inout [15:0] n64_pi_ad,
-
- input n64_si_clk,
- inout n64_si_dq,
-
- output sdram_cs,
- output sdram_ras,
- output sdram_cas,
- output sdram_we,
- output [1:0] sdram_ba,
- output [12:0] sdram_a,
- inout [15:0] sdram_dq
-);
-
- if_n64_bus bus ();
-
- n64_pi n64_pi_inst (
- .sys(sys),
- .cfg(cfg),
- .bus(bus),
-
- .n64_pi_alel(n64_pi_alel),
- .n64_pi_aleh(n64_pi_aleh),
- .n64_pi_read(n64_pi_read),
- .n64_pi_write(n64_pi_write),
- .n64_pi_ad(n64_pi_ad)
- );
-
- n64_si n64_si_inst (
- .sys(sys),
- .si(si),
-
- .n64_si_clk(n64_si_clk),
- .n64_si_dq(n64_si_dq)
- );
-
- n64_sdram n64_sdram_inst (
- .sys(sys),
- .bus(bus.at[sc64::ID_N64_SDRAM].device),
- .usb_dma(usb_dma),
- .sdram(sdram),
-
- .sdram_cs(sdram_cs),
- .sdram_ras(sdram_ras),
- .sdram_cas(sdram_cas),
- .sdram_we(sdram_we),
- .sdram_ba(sdram_ba),
- .sdram_a(sdram_a),
- .sdram_dq(sdram_dq)
- );
-
- n64_bootloader n64_bootloader_inst (
- .sys(sys),
- .bus(bus.at[sc64::ID_N64_BOOTLOADER].device),
- .cfg(cfg),
- .flash(flash)
- );
-
- n64_flashram n64_flashram_inst (
- .sys(sys),
- .bus(bus.at[sc64::ID_N64_FLASHRAM].device),
- .cfg(cfg),
- .flashram(flashram)
- );
-
- n64_dd n64_dd_inst (
- .sys(sys),
- .bus(bus.at[sc64::ID_N64_DD].device),
- .dd(dd)
- );
-
- n64_dd_sector_buffer n64_dd_sector_buffer_inst (
- .sys(sys),
- .dd(dd)
- );
-
- n64_cfg n64_cfg_inst (
- .sys(sys),
- .bus(bus.at[sc64::ID_N64_CFG].device),
- .cfg(cfg)
- );
-
-endmodule
diff --git a/fw/rtl/n64/n64_top.sv b/fw/rtl/n64/n64_top.sv
new file mode 100644
index 0000000..8fc6017
--- /dev/null
+++ b/fw/rtl/n64/n64_top.sv
@@ -0,0 +1,92 @@
+module n64_top (
+ input clk,
+ input reset,
+
+ mem_bus.controller mem_bus,
+
+ n64_scb n64_scb,
+
+ input n64_reset,
+ input n64_nmi,
+ output n64_irq,
+
+ input n64_pi_alel,
+ input n64_pi_aleh,
+ input n64_pi_read,
+ input n64_pi_write,
+ inout [15:0] n64_pi_ad,
+
+ input n64_si_clk,
+ inout n64_si_dq
+);
+
+ logic n64_dd_irq;
+ logic n64_cfg_irq;
+
+ assign n64_irq = (n64_dd_irq || n64_cfg_irq) ? 1'b0 : 1'bZ;
+
+ n64_reg_bus reg_bus ();
+
+ n64_pi n64_pi_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .mem_bus(mem_bus),
+ .reg_bus(reg_bus),
+
+ .n64_scb(n64_scb),
+
+ .n64_reset(n64_reset),
+ .n64_nmi(n64_nmi),
+ .n64_pi_alel(n64_pi_alel),
+ .n64_pi_aleh(n64_pi_aleh),
+ .n64_pi_read(n64_pi_read),
+ .n64_pi_write(n64_pi_write),
+ .n64_pi_ad(n64_pi_ad)
+ );
+
+ assign n64_dd_irq = 1'b0;
+
+ // n64_dd n64_dd_inst (
+ // .clk(clk),
+ // .reset(reset),
+
+ // .reg_bus(reg_bus),
+
+ // .n64_scb(n64_scb),
+
+ // .irq(n64_dd_irq)
+ // );
+
+ n64_flashram n64_flashram_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .reg_bus(reg_bus),
+
+ .n64_scb(n64_scb)
+ );
+
+ n64_cfg n64_cfg_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .reg_bus(reg_bus),
+
+ .n64_scb(n64_scb),
+
+ .irq(n64_cfg_irq)
+ );
+
+ n64_si n64_si_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .n64_scb(n64_scb),
+
+ .n64_reset(n64_reset),
+ .n64_si_clk(n64_si_clk),
+ .n64_si_dq(n64_si_dq)
+ );
+
+endmodule
diff --git a/fw/rtl/sd/sd_clk.sv b/fw/rtl/sd/sd_clk.sv
new file mode 100644
index 0000000..1818bd5
--- /dev/null
+++ b/fw/rtl/sd/sd_clk.sv
@@ -0,0 +1,46 @@
+module sd_clk (
+ input clk,
+ input reset,
+
+ sd_scb.clk sd_scb,
+
+ output logic sd_clk_rising,
+ output logic sd_clk_falling,
+
+ output logic sd_clk
+);
+
+ logic [7:0] clock_divider;
+
+ always_ff @(posedge clk) begin
+ clock_divider <= clock_divider + 1'd1;
+ end
+
+ logic selected_clock;
+
+ always_comb begin
+ selected_clock = 1'b0;
+ case (sd_scb.clock_mode)
+ 2'd0: selected_clock = 1'b0;
+ 2'd1: selected_clock = clock_divider[7];
+ 2'd2: selected_clock = clock_divider[1];
+ 2'd3: selected_clock = clock_divider[0];
+ endcase
+ end
+
+ logic last_selected_clock;
+
+ always_ff @(posedge clk) begin
+ last_selected_clock <= selected_clock;
+ end
+
+ always_comb begin
+ sd_clk_rising = !last_selected_clock && selected_clock;
+ sd_clk_falling = last_selected_clock && !selected_clock;
+ end
+
+ always_ff @(posedge clk) begin
+ sd_clk <= last_selected_clock;
+ end
+
+endmodule
diff --git a/fw/rtl/sd/sd_cmd.sv b/fw/rtl/sd/sd_cmd.sv
new file mode 100644
index 0000000..661102f
--- /dev/null
+++ b/fw/rtl/sd/sd_cmd.sv
@@ -0,0 +1,15 @@
+module sd_cmd (
+ input clk,
+ input reset,
+
+ sd_scb.cmd sd_scb,
+
+ input sd_clk_rising,
+ input sd_clk_falling,
+
+ inout sd_cmd
+);
+
+ assign sd_cmd = 1'bZ;
+
+endmodule
diff --git a/fw/rtl/sd/sd_crc_7.sv b/fw/rtl/sd/sd_crc_7.sv
new file mode 100644
index 0000000..bfee1a8
--- /dev/null
+++ b/fw/rtl/sd/sd_crc_7.sv
@@ -0,0 +1,28 @@
+module sd_crc_7 (
+ input clk,
+ input reset,
+
+ input enable,
+ input data,
+
+ output logic [6:0] result
+);
+
+ logic crc_inv;
+
+ assign crc_inv = result[6] ^ data;
+
+ always_ff @(posedge clk) begin
+ if (reset) begin
+ result <= 7'd0;
+ end else if (enable) begin
+ result <= {
+ result[5:3],
+ result[2] ^ crc_inv,
+ result[1:0],
+ crc_inv
+ };
+ end
+ end
+
+endmodule
diff --git a/fw/rtl/sd/sd_scb.sv b/fw/rtl/sd/sd_scb.sv
new file mode 100644
index 0000000..1a4d37a
--- /dev/null
+++ b/fw/rtl/sd/sd_scb.sv
@@ -0,0 +1,21 @@
+interface sd_scb ();
+
+ logic [1:0] clock_mode;
+
+ logic [5:0] index;
+
+ modport controller (
+ output clock_mode,
+
+ output index
+ );
+
+ modport clk (
+ input clock_mode
+ );
+
+ modport cmd (
+ input index
+ );
+
+endinterface
diff --git a/fw/rtl/sd/sd_top.sv b/fw/rtl/sd/sd_top.sv
new file mode 100644
index 0000000..42b2e46
--- /dev/null
+++ b/fw/rtl/sd/sd_top.sv
@@ -0,0 +1,43 @@
+module sd_top (
+ input clk,
+ input reset,
+
+ sd_scb sd_scb,
+
+ fifo_bus.fifo fifo_bus,
+
+ output sd_clk,
+ inout sd_cmd,
+ inout [3:0] sd_dat
+);
+
+ assign sd_dat = 4'hZ;
+
+ logic sd_clk_rising;
+ logic sd_clk_falling;
+
+ sd_clk sd_clk_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .sd_scb(sd_scb),
+
+ .sd_clk_rising(sd_clk_rising),
+ .sd_clk_falling(sd_clk_falling),
+
+ .sd_clk(sd_clk)
+ );
+
+ sd_cmd sd_cmd_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .sd_scb(sd_scb),
+
+ .sd_clk_rising(sd_clk_rising),
+ .sd_clk_falling(sd_clk_falling),
+
+ .sd_cmd(sd_cmd)
+ );
+
+endmodule
diff --git a/fw/rtl/system/config.sv b/fw/rtl/system/config.sv
deleted file mode 100644
index 01652c8..0000000
--- a/fw/rtl/system/config.sv
+++ /dev/null
@@ -1,76 +0,0 @@
-interface if_config ();
-
- logic cpu_ready;
- logic cpu_busy;
- logic cmd_error;
- logic cmd_request;
- logic [7:0] cmd;
- logic [31:0] data [0:1];
- logic [1:0] data_write;
- logic [31:0] wdata;
- logic sdram_switch;
- logic sdram_writable;
- logic dd_enabled;
- logic sram_enabled;
- logic sram_banked;
- logic flashram_enabled;
- logic flashram_read_mode;
- logic flash_erase_start;
- logic flash_erase_busy;
- logic flash_wp_enable;
- logic flash_wp_disable;
-
- modport pi (
- input sdram_switch,
- input sdram_writable,
- input dd_enabled,
- input sram_enabled,
- input sram_banked,
- input flashram_enabled,
- input flashram_read_mode
- );
-
- modport flashram (
- output flashram_read_mode
- );
-
- modport flash (
- input flash_erase_start,
- output flash_erase_busy,
- input flash_wp_enable,
- input flash_wp_disable
- );
-
- modport n64 (
- input cpu_ready,
- input cpu_busy,
- input cmd_error,
- output cmd_request,
- output cmd,
- output data,
- input data_write,
- input wdata
- );
-
- modport cpu (
- output cpu_ready,
- output cpu_busy,
- output cmd_error,
- input cmd_request,
- input cmd,
- input data,
- output data_write,
- output wdata,
- output sdram_switch,
- output sdram_writable,
- output dd_enabled,
- output sram_enabled,
- output sram_banked,
- output flashram_enabled,
- output flash_erase_start,
- input flash_erase_busy,
- output flash_wp_enable,
- output flash_wp_disable
- );
-
-endinterface
diff --git a/fw/rtl/system/sc64.sv b/fw/rtl/system/sc64.sv
deleted file mode 100644
index 1e0dd73..0000000
--- a/fw/rtl/system/sc64.sv
+++ /dev/null
@@ -1,22 +0,0 @@
-package sc64;
-
- typedef enum bit [2:0] {
- ID_N64_SDRAM,
- ID_N64_BOOTLOADER,
- ID_N64_FLASHRAM,
- ID_N64_DD,
- ID_N64_CFG,
- __ID_N64_END
- } e_n64_id;
-
- parameter bit [31:0] SC64_VER = 32'h53437632;
- parameter int CLOCK_FREQUENCY = 32'd100_000_000;
- parameter int UART_BAUD_RATE = 32'd1_000_000;
-
-`ifdef DEBUG
- parameter bit CPU_HAS_UART = 1'b1;
-`else
- parameter bit CPU_HAS_UART = 1'b0;
-`endif
-
-endpackage
diff --git a/fw/rtl/system/system.sv b/fw/rtl/system/system.sv
deleted file mode 100644
index a439629..0000000
--- a/fw/rtl/system/system.sv
+++ /dev/null
@@ -1,62 +0,0 @@
-interface if_system (
- input in_clk,
- input n64_reset,
- input n64_nmi
-);
-
- logic clk;
- logic sdram_clk;
- logic reset;
- logic n64_soft_reset;
- logic n64_hard_reset;
-
- modport internal (
- input in_clk,
- input n64_reset,
- input n64_nmi,
- output clk,
- output sdram_clk,
- output reset,
- output n64_soft_reset,
- output n64_hard_reset
- );
-
- modport sys (
- input clk,
- input reset,
- input n64_soft_reset,
- input n64_hard_reset
- );
-
- modport sdram (
- input sdram_clk
- );
-
-endinterface
-
-
-module system (if_system.internal sys);
-
- logic locked;
- logic [1:0] n64_reset_ff;
- logic [1:0] n64_nmi_ff;
-
- intel_pll intel_pll_inst (
- .inclk0(sys.in_clk),
- .c0(sys.clk),
- .c1(sys.sdram_clk),
- .locked(locked)
- );
-
- always_ff @(posedge sys.clk) begin
- n64_reset_ff <= {n64_reset_ff[0], sys.n64_reset};
- n64_nmi_ff <= {n64_nmi_ff[0], sys.n64_nmi};
- end
-
- always_comb begin
- sys.reset = ~locked;
- sys.n64_hard_reset = ~n64_reset_ff[1];
- sys.n64_soft_reset = ~n64_nmi_ff[1];
- end
-
-endmodule
diff --git a/fw/rtl/top.sv b/fw/rtl/top.sv
new file mode 100644
index 0000000..d0031e1
--- /dev/null
+++ b/fw/rtl/top.sv
@@ -0,0 +1,240 @@
+module top (
+ input inclk,
+
+ input n64_reset,
+ input n64_nmi,
+ output n64_irq,
+
+ input n64_pi_alel,
+ input n64_pi_aleh,
+ input n64_pi_read,
+ input n64_pi_write,
+ inout [15:0] n64_pi_ad,
+
+ input n64_si_clk,
+ inout n64_si_dq,
+
+ input usb_pwrsav,
+ output usb_clk,
+ output usb_cs,
+ input usb_miso,
+ inout [7:0] usb_miosi,
+
+ input sd_det,
+ output sd_clk,
+ inout sd_cmd,
+ inout [3:0] sd_dat,
+
+ output sdram_clk,
+ output sdram_cs,
+ output sdram_ras,
+ output sdram_cas,
+ output sdram_we,
+ output [1:0] sdram_ba,
+ output [12:0] sdram_a,
+ output [1:0] sdram_dqm,
+ inout [15:0] sdram_dq,
+
+ output flash_clk,
+ output flash_cs,
+ inout [3:0] flash_dq,
+
+ input button,
+
+ output mcu_int,
+ input mcu_clk,
+ input mcu_cs,
+ input mcu_mosi,
+ output mcu_miso
+);
+
+ logic clk;
+ logic reset;
+
+ n64_scb n64_scb ();
+ usb_scb usb_scb ();
+ dma_scb usb_dma_scb ();
+ sd_scb sd_scb ();
+ dma_scb sd_dma_scb ();
+ flash_scb flash_scb ();
+
+ fifo_bus usb_cfg_fifo_bus ();
+ fifo_bus usb_dma_fifo_bus ();
+ fifo_bus usb_fifo_bus ();
+ fifo_bus sd_fifo_bus ();
+
+ mem_bus n64_mem_bus ();
+ mem_bus cfg_mem_bus ();
+ mem_bus usb_dma_mem_bus ();
+ mem_bus sd_dma_mem_bus ();
+ mem_bus sdram_mem_bus ();
+ mem_bus flash_mem_bus ();
+
+ pll pll_inst (
+ .inclk(inclk),
+ .clk(clk),
+ .sdram_clk(sdram_clk),
+ .reset(reset)
+ );
+
+
+ // MCU controller
+
+ mcu_top mcu_top_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .n64_scb(n64_scb),
+ .usb_scb(usb_scb),
+ .usb_dma_scb(usb_dma_scb),
+ .sd_scb(sd_scb),
+ .sd_dma_scb(sd_dma_scb),
+ .flash_scb(flash_scb),
+
+ .fifo_bus(usb_cfg_fifo_bus),
+ .mem_bus(cfg_mem_bus),
+
+ .sd_det(sd_det),
+ .button(button),
+
+ .mcu_int(mcu_int),
+ .mcu_clk(mcu_clk),
+ .mcu_cs(mcu_cs),
+ .mcu_mosi(mcu_mosi),
+ .mcu_miso(mcu_miso)
+ );
+
+
+ // N64 controller
+
+ n64_top n64_top_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .n64_scb(n64_scb),
+
+ .mem_bus(n64_mem_bus),
+
+ .n64_reset(n64_reset),
+ .n64_nmi(n64_nmi),
+ .n64_irq(n64_irq),
+
+ .n64_pi_alel(n64_pi_alel),
+ .n64_pi_aleh(n64_pi_aleh),
+ .n64_pi_read(n64_pi_read),
+ .n64_pi_write(n64_pi_write),
+ .n64_pi_ad(n64_pi_ad),
+
+ .n64_si_clk(n64_si_clk),
+ .n64_si_dq(n64_si_dq)
+ );
+
+
+ // USB
+
+ usb_ft1248 usb_ft1248_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .usb_scb(usb_scb),
+
+ .fifo_bus(usb_fifo_bus),
+
+ .usb_pwrsav(usb_pwrsav),
+ .usb_clk(usb_clk),
+ .usb_cs(usb_cs),
+ .usb_miso(usb_miso),
+ .usb_miosi(usb_miosi)
+ );
+
+ memory_dma memory_usb_dma_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .dma_scb(usb_dma_scb),
+
+ .fifo_bus(usb_dma_fifo_bus),
+ .mem_bus(usb_dma_mem_bus)
+ );
+
+ fifo_junction usb_fifo_junction_inst (
+ .cfg_bus(usb_cfg_fifo_bus),
+ .dma_bus(usb_dma_fifo_bus),
+ .dev_bus(usb_fifo_bus)
+ );
+
+
+ // SD card
+
+ sd_top sd_top_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .sd_scb(sd_scb),
+
+ .fifo_bus(sd_fifo_bus),
+
+ .sd_clk(sd_clk),
+ .sd_cmd(sd_cmd),
+ .sd_dat(sd_dat)
+ );
+
+ memory_dma memory_sd_dma_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .dma_scb(sd_dma_scb),
+
+ .fifo_bus(sd_fifo_bus),
+ .mem_bus(sd_dma_mem_bus)
+ );
+
+
+ // Memory bus arbiter
+
+ memory_arbiter memory_arbiter_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .n64_bus(n64_mem_bus),
+ .cfg_bus(cfg_mem_bus),
+ .usb_dma_bus(usb_dma_mem_bus),
+ .sd_dma_bus(sd_dma_mem_bus),
+
+ .sdram_mem_bus(sdram_mem_bus),
+ .flash_mem_bus(flash_mem_bus)
+ );
+
+
+ // Memory controllers
+
+ memory_sdram memory_sdram_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .mem_bus(sdram_mem_bus),
+
+ .sdram_cs(sdram_cs),
+ .sdram_ras(sdram_ras),
+ .sdram_cas(sdram_cas),
+ .sdram_we(sdram_we),
+ .sdram_ba(sdram_ba),
+ .sdram_a(sdram_a),
+ .sdram_dqm(sdram_dqm),
+ .sdram_dq(sdram_dq)
+ );
+
+ memory_flash memory_flash_inst (
+ .clk(clk),
+ .reset(reset),
+
+ .flash_scb(flash_scb),
+
+ .mem_bus(flash_mem_bus),
+
+ .flash_clk(flash_clk),
+ .flash_cs(flash_cs),
+ .flash_dq(flash_dq)
+ );
+
+endmodule
diff --git a/fw/rtl/usb/usb_ft1248.sv b/fw/rtl/usb/usb_ft1248.sv
index 9a86de8..aad5b0f 100644
--- a/fw/rtl/usb/usb_ft1248.sv
+++ b/fw/rtl/usb/usb_ft1248.sv
@@ -1,27 +1,40 @@
+interface usb_scb ();
+
+ logic fifo_flush;
+ logic reset_pending;
+ logic reset_ack;
+ logic write_buffer_flush;
+
+ modport controller (
+ output fifo_flush,
+ input reset_pending,
+ output reset_ack,
+ output write_buffer_flush
+ );
+
+ modport usb (
+ input fifo_flush,
+ output reset_pending,
+ input reset_ack,
+ input write_buffer_flush
+ );
+
+endinterface
+
+
module usb_ft1248 (
input clk,
input reset,
- output usb_clk,
- output usb_cs,
+ usb_scb.usb usb_scb,
+
+ fifo_bus.fifo fifo_bus,
+
+ input usb_pwrsav,
+ output logic usb_clk,
+ output logic usb_cs,
input usb_miso,
- inout [7:0] usb_miosi,
-
- output reset_pending,
- input reset_ack,
- input write_buffer_flush,
-
- input rx_flush,
- output rx_empty,
- output rx_almost_empty,
- input rx_read,
- output [7:0] rx_rdata,
-
- input tx_flush,
- output tx_full,
- output tx_almost_full,
- input tx_write,
- input [7:0] tx_wdata
+ inout [7:0] usb_miosi
);
logic rx_full;
@@ -34,39 +47,41 @@ module usb_ft1248 (
logic tx_read;
logic [7:0] tx_rdata;
- intel_fifo_8 fifo_8_rx_inst (
- .clock(clk),
- .sclr(reset || rx_flush),
+ fifo_8kb fifo_8kb_rx_inst (
+ .clk(clk),
+ .reset(reset || usb_scb.fifo_flush),
- .empty(rx_empty),
- .almost_empty(rx_almost_empty),
- .rdreq(rx_read),
- .q(rx_rdata),
+ .empty(fifo_bus.rx_empty),
+ .almost_empty(fifo_bus.rx_almost_empty),
+ .read(fifo_bus.rx_read),
+ .rdata(fifo_bus.rx_rdata),
.full(rx_full),
.almost_full(rx_almost_full),
- .wrreq(rx_write),
- .data(rx_wdata)
+ .write(rx_write),
+ .wdata(rx_wdata)
);
- intel_fifo_8 fifo_8_tx_inst (
- .clock(clk),
- .sclr(reset || tx_flush),
+ fifo_8kb fifo_8kb_tx_inst (
+ .clk(clk),
+ .reset(reset || usb_scb.fifo_flush),
.empty(tx_empty),
.almost_empty(tx_almost_empty),
- .rdreq(tx_read),
- .q(tx_rdata),
+ .read(tx_read),
+ .rdata(tx_rdata),
- .full(tx_full),
- .almost_full(tx_almost_full),
- .wrreq(tx_write),
- .data(tx_wdata)
+ .full(fifo_bus.tx_full),
+ .almost_full(fifo_bus.tx_almost_full),
+ .write(fifo_bus.tx_write),
+ .wdata(fifo_bus.tx_wdata)
);
+ logic [1:0] usb_pwrsav_ff;
logic [7:0] usb_miosi_out;
logic usb_oe;
+ logic ft_pwrsav;
logic ft_clk;
logic ft_cs;
logic ft_miso;
@@ -75,6 +90,8 @@ module usb_ft1248 (
logic ft_oe;
always_ff @(posedge clk) begin
+ usb_pwrsav_ff <= {usb_pwrsav_ff[0], usb_pwrsav};
+ ft_pwrsav <= usb_pwrsav_ff[1];
usb_clk <= ft_clk;
usb_cs <= ft_cs;
ft_miso <= usb_miso;
@@ -83,9 +100,7 @@ module usb_ft1248 (
usb_oe <= ft_oe;
end
- always_comb begin
- usb_miosi = usb_oe ? usb_miosi_out : 8'hZZ;
- end
+ assign usb_miosi = usb_oe ? usb_miosi_out : 8'hZZ;
typedef enum bit [2:0] {
STATE_IDLE,
@@ -102,13 +117,14 @@ module usb_ft1248 (
CMD_READ_MODEM_STATUS = 8'h20,
CMD_WRITE_MODEM_STATUS = 8'h60,
CMD_WRITE_BUFFER_FLUSH = 8'h08
- } e_command;
+ } e_cmd;
e_state state;
e_state next_state;
- e_command cmd;
- e_command next_cmd;
+ e_cmd cmd;
+ e_cmd next_cmd;
logic [3:0] phase;
+ logic last_tx_failed;
logic reset_reply;
logic last_reset_status;
logic [4:0] modem_status_counter;
@@ -125,19 +141,20 @@ module usb_ft1248 (
end
if (reset) begin
- reset_pending <= 1'b0;
+ last_tx_failed <= 1'b0;
+ usb_scb.reset_pending <= 1'b0;
last_reset_status <= 1'b0;
modem_status_counter <= 5'd0;
write_modem_status_pending <= 1'b0;
write_buffer_flush_pending <= 1'b0;
end else begin
- if (reset_ack) begin
- reset_pending <= 1'b0;
+ if (usb_scb.reset_ack) begin
+ usb_scb.reset_pending <= 1'b0;
reset_reply <= 1'b1;
write_modem_status_pending <= 1'b1;
end
- if (write_buffer_flush) begin
+ if (usb_scb.write_buffer_flush) begin
write_buffer_flush_pending <= 1'b1;
end
@@ -145,11 +162,15 @@ module usb_ft1248 (
modem_status_counter <= modem_status_counter + 1'd1;
end
+ if ((state == STATE_DATA) && (cmd == CMD_WRITE) && phase[3]) begin
+ last_tx_failed <= ft_miso;
+ end
+
if (!ft_miso && (state == STATE_DATA) && phase[3]) begin
if (cmd == CMD_READ_MODEM_STATUS) begin
last_reset_status <= ft_miosi_in[0];
if (!last_reset_status && ft_miosi_in[0]) begin
- reset_pending <= 1'b1;
+ usb_scb.reset_pending <= 1'b1;
end
if (last_reset_status && !ft_miosi_in[0]) begin
reset_reply <= 1'b0;
@@ -214,13 +235,23 @@ module usb_ft1248 (
rx_wdata = ft_miosi_in;
- if (!ft_miso && (state == STATE_DATA) && phase[3]) begin
- if (cmd == CMD_READ) begin
- rx_write = 1'b1;
- end
- if (cmd == CMD_WRITE) begin
- tx_read = 1'b1;
- end
+ if (!ft_miso && phase[3]) begin
+ case (state)
+ STATE_STATUS: begin
+ if (cmd == CMD_WRITE && !last_tx_failed) begin
+ tx_read = 1'b1;
+ end
+ end
+
+ STATE_DATA: begin
+ if (cmd == CMD_READ) begin
+ rx_write = 1'b1;
+ end
+ if (cmd == CMD_WRITE && !tx_empty) begin
+ tx_read = 1'b1;
+ end
+ end
+ endcase
end
end
@@ -233,21 +264,23 @@ module usb_ft1248 (
end else begin
case (state)
STATE_IDLE: begin
- if (write_modem_status_pending) begin
- next_state = STATE_SELECT;
- next_cmd = CMD_WRITE_MODEM_STATUS;
- end else if (&modem_status_counter) begin
- next_state = STATE_SELECT;
- next_cmd = CMD_READ_MODEM_STATUS;
- end else if (!tx_empty) begin
- next_state = STATE_SELECT;
- next_cmd = CMD_WRITE;
- end else if (write_buffer_flush_pending) begin
- next_state = STATE_SELECT;
- next_cmd = CMD_WRITE_BUFFER_FLUSH;
- end else if (!rx_full) begin
- next_state = STATE_SELECT;
- next_cmd = CMD_READ;
+ if (ft_pwrsav) begin
+ if (write_modem_status_pending) begin
+ next_state = STATE_SELECT;
+ next_cmd = CMD_WRITE_MODEM_STATUS;
+ end else if (&modem_status_counter) begin
+ next_state = STATE_SELECT;
+ next_cmd = CMD_READ_MODEM_STATUS;
+ end else if (!tx_empty || last_tx_failed) begin
+ next_state = STATE_SELECT;
+ next_cmd = CMD_WRITE;
+ end else if (write_buffer_flush_pending) begin
+ next_state = STATE_SELECT;
+ next_cmd = CMD_WRITE_BUFFER_FLUSH;
+ end else if (!rx_full) begin
+ next_state = STATE_SELECT;
+ next_cmd = CMD_READ;
+ end
end
end
@@ -282,7 +315,7 @@ module usb_ft1248 (
next_state = STATE_DESELECT;
end
end else if (cmd == CMD_WRITE) begin
- if (tx_almost_empty) begin
+ if (tx_empty) begin
next_state = STATE_DESELECT;
end
end else begin
diff --git a/fw/rtl/vendor/intel/generated/intel_flash.qsys b/fw/rtl/vendor/intel/generated/intel_flash.qsys
deleted file mode 100644
index 5759c65..0000000
--- a/fw/rtl/vendor/intel/generated/intel_flash.qsys
+++ /dev/null
@@ -1,90 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- Single Compressed Image
- Internal Configuration
-
-
-
-
-
- Read and write,Read and write,Hidden,Read and write,Read and write
- $${FILENAME}_onchip_flash_0
-
-
-
-
-
-
-
-
-
-
diff --git a/fw/rtl/vendor/intel/generated/intel_gpio_ddro.qip b/fw/rtl/vendor/intel/generated/intel_gpio_ddro.qip
deleted file mode 100644
index 2cd6c78..0000000
--- a/fw/rtl/vendor/intel/generated/intel_gpio_ddro.qip
+++ /dev/null
@@ -1,77 +0,0 @@
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_NAME "altera_gpio_lite"
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_VERSION "21.1"
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_ENV "mwpim"
-set_global_assignment -library "intel_gpio_ddro" -name MISC_FILE [file join $::quartus(qip_path) "intel_gpio_ddro.cmp"]
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_QSYS_MODE "UNKNOWN"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_NAME "aW50ZWxfZ3Bpb19kZHJv"
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_VERSION "MjEuMQ=="
-set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_VERSION "MjEuMQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::b3V0cHV0::RGF0YSBkaXJlY3Rpb24="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3RydWVfZGlmZl9idWY=::ZmFsc2U=::VXNlIHRydWUgZGlmZmVyZW50aWFsIGJ1ZmZlcg=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3BzZXVkb19kaWZmX2J1Zg==::ZmFsc2U=::VXNlIHBzZXVkbyBkaWZmZXJlbnRpYWwgYnVmZmVy"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX29wZW5fZHJhaW4=::ZmFsc2U=::VXNlIG9wZW4gZHJhaW4gb3V0cHV0"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9wb3J0::ZmFsc2U=::RW5hYmxlIG9lIHBvcnQ="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::ZGRy::UmVnaXN0ZXIgbW9kZQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIGFjbHIgcG9ydA=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hc2V0X3BvcnQ=::ZmFsc2U=::RW5hYmxlIGFzZXQgcG9ydA=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9zY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIHNjbHIgcG9ydA=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3NldF9yZWdpc3RlcnNfdG9fcG93ZXJfdXBfaGlnaA==::ZmFsc2U=::U2V0IHJlZ2lzdGVycyB0byBwb3dlciB1cCBoaWdoICh3aGVuIGFjbHIsIHNjbHIgYW5kIGFzZXQgcG9ydHMgYXJlIG5vdCB1c2VkKQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2Nsb2NrX2VuYWJsZQ==::ZmFsc2U=::RW5hYmxlIGluY2xvY2tlbi9vdXRjbG9ja2VuIHBvcnRz"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXQ=::ZmFsc2U=::SW52ZXJ0IGRpbg=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9yZWdpc3Rlcl90b19kcml2ZV9vYnVmX29l::ZmFsc2U=::VXNlIGEgc2luZ2xlIHJlZ2lzdGVyIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9kZGlvX3JlZ190b19kcml2ZV9vZQ==::ZmFsc2U=::VXNlIERESU8gcmVnaXN0ZXJzIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hZHZhbmNlZF9kZHJfZmVhdHVyZXM=::ZmFsc2U=::RW5hYmxlIGFkdmFuY2VkIEREUiBmZWF0dXJlcw=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9waGFzZV9kZXRlY3Rvcl9mb3JfY2s=::ZmFsc2U=::RW5hYmxlIFBoYXNlIERldGVjdG9yIGZyb20gQ0sgbG9vcGJhY2sgc2lnbmFs"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9oYWxmX2N5Y2xlX2RlbGF5::dHJ1ZQ==::QWRkIGhhbGYtY3ljbGUgZGVsYXkgdG8gT0Ugc2lnbmFs"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ocl9jbG9jaw==::ZmFsc2U=::RW5hYmxlIGhhbGYtcmF0ZSBjbG9jayBwb3J0"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9pbnZlcnRfaHJfY2xvY2tfcG9ydA==::ZmFsc2U=::RW5hYmxlIGludmVydF9ocl9jbG9jayBwb3J0"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9jbGtkaXZfaW5wdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IGNsb2NrIGRpdmlkZXIgaW5wdXQgY2xvY2s="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IERESU8gb3V0Y2xvY2s="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vZV9pbmNsb2Nr::ZmFsc2U=::SW52ZXJ0IG91dHB1dCBlbmFibGUgKG9lKSByZWdpc3RlciBpbmNsb2Nr"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::ZGRy::UkVHSVNURVJfTU9ERQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "QVNZTkNfTU9ERQ==::bm9uZQ==::QVNZTkNfTU9ERQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "U1lOQ19NT0RF::bm9uZQ==::U1lOQ19NT0RF"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTl9PVVRQVVQ=::ZmFsc2U=::T1BFTl9EUkFJTl9PVVRQVVQ="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX1BPUlQ=::ZmFsc2U=::RU5BQkxFX09FX1BPUlQ="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05TTEVFUF9QT1JU::ZmFsc2U=::RU5BQkxFX05TTEVFUF9QT1JU"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMT0NLX0VOQV9QT1JU::ZmFsc2U=::RU5BQkxFX0NMT0NLX0VOQV9QT1JU"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==::ZmFsc2U=::U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVA==::ZmFsc2U=::SU5WRVJUX09VVFBVVA=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0lOUFVUX0NMT0NL::ZmFsc2U=::SU5WRVJUX0lOUFVUX0NMT0NL"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=::ZmFsc2U=::VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F::ZmFsc2U=::VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=::dHJ1ZQ==::RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=::ZmFsc2U=::RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hSX0NMT0NL::ZmFsc2U=::RU5BQkxFX0hSX0NMT0NL"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX09VVFBVVF9DTE9DSw=="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09FX0lOQ0xPQ0s=::ZmFsc2U=::SU5WRVJUX09FX0lOQ0xPQ0s="
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==::ZmFsc2U=::RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw=="
-
-set_global_assignment -library "intel_gpio_ddro" -name VERILOG_FILE [file join $::quartus(qip_path) "intel_gpio_ddro.v"]
-set_global_assignment -library "intel_gpio_ddro" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_gpio_ddro/altera_gpio_lite.sv"]
-
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_NAME "altera_gpio_lite"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_VERSION "21.1"
-set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_ENV "mwpim"
diff --git a/fw/rtl/vendor/intel/generated/intel_gpio_ddro.v b/fw/rtl/vendor/intel/generated/intel_gpio_ddro.v
deleted file mode 100644
index 66bf848..0000000
--- a/fw/rtl/vendor/intel/generated/intel_gpio_ddro.v
+++ /dev/null
@@ -1,123 +0,0 @@
-// megafunction wizard: %GPIO Lite Intel FPGA IP v21.1%
-// GENERATION: XML
-// intel_gpio_ddro.v
-
-// Generated using ACDS version 21.1 842
-
-`timescale 1 ps / 1 ps
-module intel_gpio_ddro (
- input wire outclock, // outclock.export
- input wire [1:0] din, // din.export
- output wire [0:0] pad_out // pad_out.export
- );
-
- altera_gpio_lite #(
- .PIN_TYPE ("output"),
- .SIZE (1),
- .REGISTER_MODE ("ddr"),
- .BUFFER_TYPE ("single-ended"),
- .ASYNC_MODE ("none"),
- .SYNC_MODE ("none"),
- .BUS_HOLD ("false"),
- .OPEN_DRAIN_OUTPUT ("false"),
- .ENABLE_OE_PORT ("false"),
- .ENABLE_NSLEEP_PORT ("false"),
- .ENABLE_CLOCK_ENA_PORT ("false"),
- .SET_REGISTER_OUTPUTS_HIGH ("false"),
- .INVERT_OUTPUT ("false"),
- .INVERT_INPUT_CLOCK ("false"),
- .USE_ONE_REG_TO_DRIVE_OE ("false"),
- .USE_DDIO_REG_TO_DRIVE_OE ("false"),
- .USE_ADVANCED_DDR_FEATURES ("false"),
- .USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
- .ENABLE_OE_HALF_CYCLE_DELAY ("true"),
- .INVERT_CLKDIV_INPUT_CLOCK ("false"),
- .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
- .ENABLE_HR_CLOCK ("false"),
- .INVERT_OUTPUT_CLOCK ("false"),
- .INVERT_OE_INCLOCK ("false"),
- .ENABLE_PHASE_DETECTOR_FOR_CK ("false")
- ) intel_gpio_ddro_inst (
- .outclock (outclock), // outclock.export
- .din (din), // din.export
- .pad_out (pad_out), // pad_out.export
- .outclocken (1'b1), // (terminated)
- .inclock (1'b0), // (terminated)
- .inclocken (1'b0), // (terminated)
- .fr_clock (), // (terminated)
- .hr_clock (), // (terminated)
- .invert_hr_clock (1'b0), // (terminated)
- .phy_mem_clock (1'b0), // (terminated)
- .mimic_clock (), // (terminated)
- .dout (), // (terminated)
- .pad_io (), // (terminated)
- .pad_io_b (), // (terminated)
- .pad_in (1'b0), // (terminated)
- .pad_in_b (1'b0), // (terminated)
- .pad_out_b (), // (terminated)
- .aset (1'b0), // (terminated)
- .aclr (1'b0), // (terminated)
- .sclr (1'b0), // (terminated)
- .nsleep (1'b0), // (terminated)
- .oe (1'b0) // (terminated)
- );
-
-endmodule
-// Retrieval info:
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-// IPFS_FILES : intel_gpio_ddro.vo
-// RELATED_FILES: intel_gpio_ddro.v, altera_gpio_lite.sv
diff --git a/fw/rtl/vendor/intel/generated/intel_gpio_ddro/altera_gpio_lite.sv b/fw/rtl/vendor/intel/generated/intel_gpio_ddro/altera_gpio_lite.sv
deleted file mode 100644
index 4c06935..0000000
--- a/fw/rtl/vendor/intel/generated/intel_gpio_ddro/altera_gpio_lite.sv
+++ /dev/null
@@ -1,1200 +0,0 @@
-// (C) 2001-2021 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions and other
-// software and tools, and its AMPP partner logic functions, and any output
-// files from any of the foregoing (including device programming or simulation
-// files), and any associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License Subscription
-// Agreement, Intel FPGA IP License Agreement, or other applicable
-// license agreement, including, without limitation, that your use is for the
-// sole purpose of programming logic devices manufactured by Intel and sold by
-// Intel or its authorized distributors. Please refer to the applicable
-// agreement for further details.
-
-
-`timescale 1 ps / 1 ps
-
-module altgpio_one_bit(
- inclock,
- outclock,
- phy_mem_clock,
- inclocken,
- outclocken,
- oe,
- din,
- dout,
- pad,
- pad_b,
- aset,
- sclr,
- hr_clock,
- fr_clock,
- mimic_clock,
- nsleep
-);
-
- parameter PIN_TYPE = "output";
- parameter BUFFER_TYPE = "single-ended";
- parameter REGISTER_MODE = "bypass";
- parameter ASYNC_MODE = "none";
- parameter SYNC_MODE = "none";
- parameter BUS_HOLD = "false";
- parameter SET_REGISTER_OUTPUTS_HIGH = "false";
- parameter USE_ENHANCED_DDR_HIO_REGISTER = "false";
- parameter BYPASS_THREE_QUARTER_REGISTER = "true";
- parameter INVERT_OUTPUT = "false";
- parameter INVERT_INPUT_CLOCK = "false";
- parameter INVERT_OUTPUT_CLOCK = "false";
- parameter INVERT_OE_INCLOCK = "false";
- parameter USE_ONE_REG_TO_DRIVE_OE = "false";
- parameter USE_DDIO_REG_TO_DRIVE_OE = "false";
- parameter OPEN_DRAIN_OUTPUT = "false";
- parameter ENABLE_OE_HALF_CYCLE_DELAY = "true";
- parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false";
- parameter ENABLE_CLOCK_ENA_PORT = "false";
- parameter ENABLE_HR_CLOCK = "false";
- parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false";
- parameter ENABLE_NSLEEP_PORT = "false";
-
- localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1;
- localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low";
-
- input inclock;
- input outclock;
- input inclocken;
- input outclocken;
- input oe;
- input nsleep;
- input [DATA_SIZE - 1:0] din;
- output [DATA_SIZE - 1:0] dout;
- inout pad;
- inout pad_b;
- input aset;
- input sclr;
- input phy_mem_clock;
- input hr_clock;
- (* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock;
- output mimic_clock;
-
- wire din_ddr;
- wire buf_in;
-
- wire oe_out;
- wire nsleep_in;
-
- generate
- if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
- begin
- wire [1:0] din_fr;
- if (INVERT_OUTPUT == "false")
- begin
- assign din_fr = din;
- end
- else
- begin
- assign din_fr = ~din;
- end
-
- wire outclock_wire;
- if (REGISTER_MODE != "bypass")
- begin
- if (INVERT_OUTPUT_CLOCK == "false")
- begin: normal_input_clock
- assign outclock_wire = outclock;
- end
- else
- begin: inverted_output_clock
- assign outclock_wire = ~outclock;
- end
- end
-
- wire outclocken_wire;
- assign outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
-
- if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
- begin
- if (ASYNC_MODE != "none")
- begin: async_mode_out_path_enhanced_ddr
- fiftyfivenm_ddio_out
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
- .power_up(DDIO_REG_POWER_UP),
- .use_new_clocking_model("true")
- ) fr_out_data_ddio (
- .datainhi(din_fr[0]),
- .datainlo(din_fr[1]),
- .dataout(din_ddr),
- .clkhi(outclock_wire),
- .clklo(outclock_wire),
- .muxsel(outclock_wire),
- .areset(aset),
- .ena(outclocken_wire),
- .phymemclock(phy_mem_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .clk (outclock_wire),
- .sreset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else if (SYNC_MODE != "none")
- begin: sync_mode_out_path_enhanced_ddr
- fiftyfivenm_ddio_out
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
- .power_up(DDIO_REG_POWER_UP),
- .use_new_clocking_model("true")
- ) fr_out_data_ddio (
- .datainhi(din_fr[0]),
- .datainlo(din_fr[1]),
- .dataout(din_ddr),
- .clkhi(outclock_wire),
- .clklo(outclock_wire),
- .muxsel(outclock_wire),
- .sreset(sclr),
- .ena(outclocken_wire),
- .phymemclock(phy_mem_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .clk (outclock_wire),
- .areset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else
- begin: out_path_enhanced_ddr
- fiftyfivenm_ddio_out
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
- .power_up(DDIO_REG_POWER_UP),
- .use_new_clocking_model("true")
- ) fr_out_data_ddio (
- .datainhi(din_fr[0]),
- .datainlo(din_fr[1]),
- .dataout(din_ddr),
- .clkhi(outclock_wire),
- .clklo(outclock_wire),
- .muxsel(outclock_wire),
- .ena(outclocken_wire),
- .phymemclock(phy_mem_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .clk(1'b0),
- .sreset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- end
- else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
- begin
- if (ASYNC_MODE != "none")
- begin: async_mode_out_path_ddr
- fiftyfivenm_ddio_out
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .use_new_clocking_model("true"),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
- ) fr_out_data_ddio (
- .datainhi(din_fr[0]),
- .datainlo(din_fr[1]),
- .dataout(din_ddr),
- .clkhi(outclock_wire),
- .clklo(outclock_wire),
- .muxsel(outclock_wire),
- .areset(aset),
- .ena(outclocken_wire)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .clk(1'b0),
- .phymemclock(1'b0),
- .sreset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else if (SYNC_MODE != "none")
- begin: sync_mode_out_path_ddr
- fiftyfivenm_ddio_out
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .use_new_clocking_model("true"),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
- ) fr_out_data_ddio (
- .datainhi(din_fr[0]),
- .datainlo(din_fr[1]),
- .dataout(din_ddr),
- .clkhi(outclock_wire),
- .clklo(outclock_wire),
- .muxsel(outclock_wire),
- .sreset(sclr),
- .ena(outclocken_wire)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .clk(1'b0),
- .phymemclock(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else
- begin: out_path_ddr
- fiftyfivenm_ddio_out
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .use_new_clocking_model("true"),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
- ) fr_out_data_ddio (
- .datainhi(din_fr[0]),
- .datainlo(din_fr[1]),
- .dataout(din_ddr),
- .clkhi(outclock_wire),
- .clklo(outclock_wire),
- .muxsel(outclock_wire),
- .ena(outclocken_wire)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .clk(1'b0),
- .phymemclock(1'b0),
- .sreset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- end
- else if (REGISTER_MODE == "single-register")
- begin: out_path_sdr
- reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */;
- always @(posedge outclock_wire)
- reg_data_out <= din_fr[0];
-
- assign din_ddr = reg_data_out;
- end
- else
- begin: out_path_reg_none
- assign din_ddr = din_fr[0];
- end
- end
- endgenerate
-
- generate
-
- if (PIN_TYPE == "bidir" || PIN_TYPE == "output")
- begin
- wire oe_inclk_wire;
- if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true")
- begin
- if (INVERT_OE_INCLOCK == "false")
- begin: normal_oe_inclock
- assign oe_inclk_wire = outclock;
- end
- else
- begin: inverted_oe_inclock
- assign oe_inclk_wire = ~outclock;
- end
- end
-
- wire oe_outclocken_wire;
- assign oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
-
- if (USE_DDIO_REG_TO_DRIVE_OE == "true")
- begin
- if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
- begin
- if (ASYNC_MODE != "none")
- begin: async_mode_oe_path_enhanced_ddr
- fiftyfivenm_ddio_oe
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
- .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
- .power_up(DDIO_REG_POWER_UP)
- ) fr_oe_data_ddio (
- .oe(~oe),
- .dataout(oe_out),
- .clk(oe_inclk_wire),
- .areset(aset),
- .ena(oe_outclocken_wire),
- .phymemclock(phy_mem_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .sreset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else if (SYNC_MODE != "none")
- begin: sync_mode_oe_path_enhanced_ddr
- fiftyfivenm_ddio_oe
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
- .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
- .power_up(DDIO_REG_POWER_UP)
- ) fr_oe_data_ddio (
- .oe(~oe),
- .dataout(oe_out),
- .clk(oe_inclk_wire),
- .sreset(sclr),
- .ena(oe_outclocken_wire),
- .phymemclock(phy_mem_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else
- begin: oe_path_enhanced_ddr
- fiftyfivenm_ddio_oe
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
- .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
- .power_up(DDIO_REG_POWER_UP)
- ) fr_oe_data_ddio (
- .oe(~oe),
- .dataout(oe_out),
- .clk(oe_inclk_wire),
- .ena(oe_outclocken_wire),
- .phymemclock(phy_mem_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .sreset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- end
- else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
- begin
- if (ASYNC_MODE != "none")
- begin: async_mode_oe_path_ddr
- fiftyfivenm_ddio_oe
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
- .power_up(DDIO_REG_POWER_UP),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
- ) fr_oe_data_ddio (
- .oe(~oe),
- .dataout(oe_out),
- .clk(oe_inclk_wire),
- .areset(aset),
- .ena(oe_outclocken_wire)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .phymemclock(1'b0),
- .sreset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else if (SYNC_MODE != "none")
- begin: sync_mode_oe_path_ddr
- fiftyfivenm_ddio_oe
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
- .power_up(DDIO_REG_POWER_UP),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
- ) fr_oe_data_ddio (
- .oe(~oe),
- .dataout(oe_out),
- .clk(oe_inclk_wire),
- .sreset(sclr),
- .ena(oe_outclocken_wire)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .phymemclock(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else
- begin: oe_path_ddr
- fiftyfivenm_ddio_oe
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
- .power_up(DDIO_REG_POWER_UP),
- .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
- ) fr_oe_data_ddio (
- .oe(~oe),
- .dataout(oe_out),
- .clk(oe_inclk_wire),
- .ena(oe_outclocken_wire)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .phymemclock(1'b0),
- .sreset(1'b0),
- .dfflo(),
- .dffhi(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- end
- end
- else if (USE_ONE_REG_TO_DRIVE_OE == "true")
- begin: oe_path_sdr
- fiftyfivenm_ff oe_reg (
- .clk(oe_inclk_wire),
- .d(~oe),
- .clrn(1'b1),
- .ena(1'b1),
- .q(oe_out)
- );
- end
- else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false")
- begin: oe_path_reg_none
- assign oe_out = ~oe;
- end
- end
- endgenerate
-
- generate
- if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
- begin
- wire [1:0] ddr_input;
- wire inclock_wire;
-
- if (REGISTER_MODE != "bypass")
- begin
- if (INVERT_INPUT_CLOCK == "false")
- begin: normal_input_clock
- assign inclock_wire = inclock;
- end
- else
- begin: inverted_input_clock
- assign inclock_wire = ~inclock;
- end
- end
-
- wire inclocken_wire;
- assign inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1;
-
- if (REGISTER_MODE == "ddr")
- begin
- if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true")
- begin
- if (ENABLE_HR_CLOCK == "true")
- begin
- if (ASYNC_MODE != "none")
- begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk
- fiftyfivenm_ddio_in
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .invert_input_clock(INVERT_INPUT_CLOCK)
- ) fr_in_ddio (
- .datain(buf_in),
- .clk(inclock_wire),
- .ena(inclocken_wire),
- .halfrateresyncclk(hr_clock),
- .regouthi(ddr_input[1]),
- .regoutlo(ddr_input[0]),
- .clkout(fr_clock),
- .areset(aset)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .sreset(1'b0),
- .dfflo(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else if (SYNC_MODE != "none")
- begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk
- fiftyfivenm_ddio_in
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .invert_input_clock(INVERT_INPUT_CLOCK)
- ) fr_in_ddio (
- .datain(buf_in),
- .clk (inclock_wire),
- .ena(inclocken_wire),
- .sreset(sclr),
- .halfrateresyncclk(hr_clock),
- .regouthi(ddr_input[1]),
- .regoutlo(ddr_input[0]),
- .clkout(fr_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .dfflo(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- else
- begin:in_path_enhanced_ddr_with_halfrateresyncclk
- fiftyfivenm_ddio_in
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .invert_input_clock(INVERT_INPUT_CLOCK)
- ) fr_in_ddio (
- .datain(buf_in),
- .clk (inclock_wire),
- .ena(inclocken_wire),
- .halfrateresyncclk(hr_clock),
- .regouthi(ddr_input[1]),
- .regoutlo(ddr_input[0]),
- .clkout(fr_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .sreset(1'b0),
- .areset(1'b0),
- .dfflo(),
- .devpor(1'b1),
- .devclrn(1'b1)
- `endif
- );
- end
- end
- else
- begin
- if (ASYNC_MODE != "none")
- begin: async_mode_in_path_enhanced_ddr
- fiftyfivenm_ddio_in
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .invert_input_clock(INVERT_INPUT_CLOCK)
- ) fr_in_ddio (
- .datain(buf_in),
- .clk(inclock_wire),
- .ena(inclocken_wire),
- .regouthi(ddr_input[1]),
- .regoutlo(ddr_input[0]),
- .clkout(fr_clock),
- .areset(aset)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .sreset(1'b0),
- .dfflo(),
- .devpor(1'b1),
- .devclrn(1'b1),
- .halfrateresyncclk(1'b0)
- `endif
- );
- end
- else if (SYNC_MODE != "none")
- begin:sync_mode_in_path_enhanced_ddr
- fiftyfivenm_ddio_in
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .invert_input_clock(INVERT_INPUT_CLOCK)
- ) fr_in_ddio (
- .datain(buf_in),
- .clk (inclock_wire),
- .ena(inclocken_wire),
- .sreset(sclr),
- .regouthi(ddr_input[1]),
- .regoutlo(ddr_input[0]),
- .clkout(fr_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .areset(1'b0),
- .dfflo(),
- .devpor(1'b1),
- .devclrn(1'b1),
- .halfrateresyncclk(1'b0)
- `endif
- );
- end
- else
- begin:in_path_enhanced_ddr
- fiftyfivenm_ddio_in
- #(
- .async_mode(ASYNC_MODE),
- .sync_mode(SYNC_MODE),
- .power_up(DDIO_REG_POWER_UP),
- .invert_input_clock(INVERT_INPUT_CLOCK)
- ) fr_in_ddio (
- .datain(buf_in),
- .clk (inclock_wire),
- .ena(inclocken_wire),
- .regouthi(ddr_input[1]),
- .regoutlo(ddr_input[0]),
- .clkout(fr_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .sreset(1'b0),
- .areset(1'b0),
- .dfflo(),
- .devpor(1'b1),
- .devclrn(1'b1),
- .halfrateresyncclk(1'b0)
- `endif
- );
- end
- end
- end
- else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true")
- begin
- assign mimic_clock = buf_in;
- end
- else
- begin: in_path_ddr
- wire input_cell_l_q;
- wire input_aset;
-
- assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset;
-
- fiftyfivenm_ff input_cell_l (
- .clk(inclock_wire),
- .d(buf_in),
- .clrn(input_aset),
- .ena(inclocken_wire),
- .q(input_cell_l_q)
- );
-
- fiftyfivenm_ff input_latch_l (
- .clk(~inclock_wire),
- .d(input_cell_l_q),
- .clrn(input_aset),
- .ena(inclocken_wire),
- .q(ddr_input[0])
- );
-
- fiftyfivenm_ff input_cell_h (
- .clk(~inclock_wire),
- .d(buf_in),
- .clrn(input_aset),
- .ena(inclocken_wire),
- .q(ddr_input[1])
- );
-
- end
- end
- else if (REGISTER_MODE == "single-register")
- begin: in_path_sdr
- reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */;
- always @(posedge inclock_wire) begin
- reg_data_in <= buf_in;
- end
- assign ddr_input[0] = reg_data_in;
- end
- else
- begin: in_path_reg_none
- assign ddr_input[0] = buf_in;
- end
-
- assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0];
-
- end
- endgenerate
-
- generate
- if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
- begin
- if(BUFFER_TYPE == "pseudo_differential")
- begin: pseudo_diff_output_buf
-
- wire wire_pseudo_diff_o;
- wire wire_pseudo_diff_o_bar;
-
- fiftyfivenm_io_obuf
- #(
- .bus_hold(BUS_HOLD),
- .open_drain_output(OPEN_DRAIN_OUTPUT)
- ) obuf_a (
- .i(wire_pseudo_diff_o),
- .oe(~oe_out),
- .o(pad),
- .obar()
- `ifndef ALTERA_RESERVED_QIS
- ,
- .seriesterminationcontrol(16'b0),
- .devoe(1'b1)
- `endif
- );
-
- fiftyfivenm_io_obuf
- #(
- .bus_hold(BUS_HOLD),
- .open_drain_output(OPEN_DRAIN_OUTPUT)
- ) obuf_a_bar (
- .i(wire_pseudo_diff_o_bar),
- .oe(~oe_out),
- .o(pad_b),
- .obar()
- `ifndef ALTERA_RESERVED_QIS
- ,
- .seriesterminationcontrol(16'b0),
- .devoe(1'b1)
- `endif
- );
-
- fiftyfivenm_pseudo_diff_out pseudo_diff_a
- (
- .i(din_ddr),
- .o(wire_pseudo_diff_o),
- .obar(wire_pseudo_diff_o_bar)
- );
-
-
-
- end
- else if (BUFFER_TYPE == "true_differential")
- begin: true_diff_output_buf
- fiftyfivenm_io_obuf
- #(
- .bus_hold(BUS_HOLD),
- .open_drain_output(OPEN_DRAIN_OUTPUT)
- ) obuf (
- .i(din_ddr),
- .oe(~oe_out),
- .o(pad),
- .obar(pad_b)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .seriesterminationcontrol(16'b0),
- .devoe(1'b1)
- `endif
- );
- end
- else
- begin: output_buf
- fiftyfivenm_io_obuf
- #(
- .bus_hold(BUS_HOLD),
- .open_drain_output(OPEN_DRAIN_OUTPUT)
- ) obuf (
- .i(din_ddr),
- .oe(~oe_out),
- .o(pad),
- .obar()
- `ifndef ALTERA_RESERVED_QIS
- ,
- .seriesterminationcontrol(16'b0),
- .devoe(1'b1)
- `endif
- );
- end
- end
- endgenerate
-
- assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1;
-
- generate
- if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
- begin
- if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential")
- begin: diff_input_buf
- if (ENABLE_NSLEEP_PORT == "true")
- begin: diff_input_buf_with_nsleep
- fiftyfivenm_io_ibuf
- #(
- .bus_hold(BUS_HOLD)
- ) ibuf (
- .i(pad),
- .ibar(pad_b),
- .o(buf_in),
- .nsleep(nsleep_in)
- );
- end
- else
- begin: diff_input_buf_without_nsleep
- fiftyfivenm_io_ibuf
- #(
- .bus_hold(BUS_HOLD)
- ) ibuf (
- .i(pad),
- .ibar(pad_b),
- .o(buf_in)
- );
- end
- end
- else
- begin:input_buf
- if (ENABLE_NSLEEP_PORT == "true")
- begin: input_buf_with_nsleep
- fiftyfivenm_io_ibuf
- #(
- .bus_hold(BUS_HOLD)
- ) ibuf (
- .i(pad),
- .o(buf_in),
- .nsleep(nsleep_in)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .ibar(1'b0)
- `endif
- );
- end
- else
- begin: input_buf_without_nsleep
- fiftyfivenm_io_ibuf
- #(
- .bus_hold(BUS_HOLD)
- ) ibuf (
- .i(pad),
- .o(buf_in)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .ibar(1'b0)
- `endif
- );
- end
- end
- end
- endgenerate
-
- generate
- if (PIN_TYPE == "output")
- begin
- assign dout = {DATA_SIZE{1'b0}};
- end
-
- if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false")
- begin
- assign fr_clock = 1'b0;
- end
-
- if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false")
- begin
- assign mimic_clock = 1'b0;
- end
- endgenerate
-
-endmodule
-
-module altera_gpio_lite(
- inclock,
- outclock,
- inclocken,
- outclocken,
- oe,
- din,
- dout,
- pad_io,
- pad_io_b,
- pad_in,
- pad_in_b,
- pad_out,
- pad_out_b,
- aset,
- aclr,
- phy_mem_clock,
- sclr,
- hr_clock,
- fr_clock,
- invert_hr_clock,
- mimic_clock,
- nsleep
-);
-
- parameter PIN_TYPE = "output";
- parameter BUFFER_TYPE = "single-ended";
- parameter REGISTER_MODE = "bypass";
- parameter SIZE = 4;
- parameter ASYNC_MODE = "none";
- parameter SYNC_MODE = "none";
- parameter BUS_HOLD = "false";
- parameter SET_REGISTER_OUTPUTS_HIGH = "false";
- parameter INVERT_OUTPUT = "false";
- parameter INVERT_INPUT_CLOCK = "false";
- parameter INVERT_OUTPUT_CLOCK = "false";
- parameter INVERT_OE_INCLOCK = "false";
- parameter USE_ONE_REG_TO_DRIVE_OE = "false";
- parameter USE_DDIO_REG_TO_DRIVE_OE = "false";
- parameter OPEN_DRAIN_OUTPUT = "false";
- parameter USE_ADVANCED_DDR_FEATURES = "false";
- parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false";
- parameter INVERT_CLKDIV_INPUT_CLOCK = "false";
- parameter ENABLE_HR_CLOCK = "false";
- parameter ENABLE_OE_HALF_CYCLE_DELAY = "true";
- parameter ENABLE_OE_PORT = "false";
- parameter ENABLE_CLOCK_ENA_PORT = "false";
- parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false";
- parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false";
- parameter ENABLE_NSLEEP_PORT = "false";
-
- localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES;
- localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true";
- localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1;
-
- input inclock;
- input outclock;
- input inclocken;
- input outclocken;
- input [SIZE - 1:0] oe;
- input [SIZE - 1:0] nsleep;
- input [SIZE * DATA_SIZE - 1:0] din;
- output [SIZE * DATA_SIZE - 1:0] dout;
- inout [SIZE - 1:0] pad_io;
- inout [SIZE - 1:0] pad_io_b;
- input [SIZE - 1:0] pad_in;
- input [SIZE - 1:0] pad_in_b;
- output [SIZE - 1:0] pad_out;
- output [SIZE - 1:0] pad_out_b;
- input aset;
- input aclr;
- input sclr;
- input phy_mem_clock;
- input invert_hr_clock;
- output [SIZE - 1:0] fr_clock;
- output wire hr_clock;
- output [SIZE - 1:0] mimic_clock;
-
- wire [SIZE * DATA_SIZE - 1:0] din_reordered;
- wire [SIZE * DATA_SIZE - 1:0] dout_reordered;
- wire aclr_aset_wire;
- wire sclr_wire;
- wire [SIZE - 1:0] pad_io;
- wire [SIZE - 1:0] pad_io_b;
-
-
- assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1;
- assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0;
-
- generate
- if (PIN_TYPE == "input")
- begin
- assign pad_io = pad_in;
- assign pad_io_b = pad_in_b;
- assign pad_out = {SIZE{1'b0}};
- assign pad_out_b = {SIZE{1'b0}};
- end
- else if (PIN_TYPE == "output")
- begin
- assign pad_out = pad_io;
- assign pad_out_b = pad_io_b;
- end
- else begin
- assign pad_out = {SIZE{1'b0}};
- assign pad_out_b = {SIZE{1'b0}};
- end
- endgenerate
-
- genvar j, k;
- generate
- begin : reorder
- for(j = 0; j < SIZE ; j = j + 1) begin : j_loop
- for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop
- assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE];
- assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k];
- end
- end
- end
- endgenerate
-
- genvar i;
- generate
- begin : gpio_one_bit
- for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop
- wire oe_wire;
- wire nsleep_wire;
-
-
- assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 :
- (PIN_TYPE == "input") ? 1'b0 : oe[i];
-
-
- assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 :
- (PIN_TYPE == "output") ? 1'b0 : nsleep[i];
-
- altgpio_one_bit #(
- .PIN_TYPE(PIN_TYPE),
- .BUFFER_TYPE(BUFFER_TYPE),
- .REGISTER_MODE(REGISTER_MODE),
- .ASYNC_MODE(ASYNC_MODE),
- .SYNC_MODE(SYNC_MODE),
- .BUS_HOLD(BUS_HOLD),
- .SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH),
- .USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER),
- .USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY),
- .BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER),
- .INVERT_OUTPUT(INVERT_OUTPUT),
- .INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK),
- .INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK),
- .INVERT_OE_INCLOCK(INVERT_OE_INCLOCK),
- .USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE),
- .USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE),
- .OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT),
- .ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY),
- .ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT),
- .ENABLE_HR_CLOCK(ENABLE_HR_CLOCK),
- .ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK),
- .ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT)
- ) altgpio_bit_i (
- .inclock(inclock),
- .outclock(outclock),
- .phy_mem_clock(phy_mem_clock),
- .inclocken(inclocken),
- .outclocken(outclocken),
- .oe(oe_wire),
- .din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
- .dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
- .pad(pad_io[i]),
- .pad_b(pad_io_b[i]),
- .aset(aclr_aset_wire),
- .sclr(sclr_wire),
- .fr_clock(fr_clock[i]),
- .hr_clock(hr_clock),
- .mimic_clock(mimic_clock[i]),
- .nsleep(nsleep_wire)
- );
- end
- end
- endgenerate
-
- generate
- if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true"))
- begin
- if (ENABLE_PHASE_INVERT_CTRL_PORT == "true")
- begin
- if (SYNC_MODE == "clear")
- begin : clock_divider_sync_mode_invert_hr_clock
- fiftyfivenm_io_clock_divider
- #(
- .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
- .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
- .sync_mode(SYNC_MODE)
- ) io_clkdiv (
- .clk(inclock),
- .phaseinvertctrl(invert_hr_clock),
- .sreset(sclr_wire),
- .clkout(hr_clock)
- );
- end
- else
- begin : clock_divider_invert_hr_clock
- fiftyfivenm_io_clock_divider
- #(
- .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
- .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
- .sync_mode(SYNC_MODE)
- ) io_clkdiv (
- .clk(inclock),
- .phaseinvertctrl(invert_hr_clock),
- .clkout(hr_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .sreset(1'b0)
- `endif
- );
- end
- end
- else
- begin
- if (SYNC_MODE == "clear")
- begin : clock_divider_sync_mode
- fiftyfivenm_io_clock_divider
- #(
- .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
- .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
- .sync_mode(SYNC_MODE)
- ) io_clkdiv (
- .clk(inclock),
- .sreset(sclr_wire),
- .clkout(hr_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .phaseinvertctrl(1'b0)
- `endif
- );
- end
- else
- begin : clock_divider
- fiftyfivenm_io_clock_divider
- #(
- .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
- .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
- .sync_mode(SYNC_MODE)
- ) io_clkdiv (
- .clk(inclock),
- .clkout(hr_clock)
- `ifndef ALTERA_RESERVED_QIS
- ,
- .sreset(1'b0),
- .phaseinvertctrl(1'b0)
- `endif
- );
- end
- end
- end
- else begin
- assign hr_clock = 1'b0;
- end
- endgenerate
-
-endmodule
diff --git a/fw/rtl/vendor/intel/generated/intel_pll.ppf b/fw/rtl/vendor/intel/generated/intel_pll.ppf
deleted file mode 100644
index bf13a5c..0000000
--- a/fw/rtl/vendor/intel/generated/intel_pll.ppf
+++ /dev/null
@@ -1,11 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
diff --git a/fw/rtl/vendor/intel/generated/intel_pll.qip b/fw/rtl/vendor/intel/generated/intel_pll.qip
deleted file mode 100644
index b7fa58d..0000000
--- a/fw/rtl/vendor/intel/generated/intel_pll.qip
+++ /dev/null
@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_pll.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "intel_pll.ppf"]
diff --git a/fw/rtl/vendor/intel/generated/intel_pll.v b/fw/rtl/vendor/intel/generated/intel_pll.v
deleted file mode 100644
index 3b945a9..0000000
--- a/fw/rtl/vendor/intel/generated/intel_pll.v
+++ /dev/null
@@ -1,341 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: intel_pll.v
-// Megafunction Name(s):
-// altpll
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2021 Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
-//and other software and tools, and any partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors. Please
-//refer to the applicable agreement for further details, at
-//https://fpgasoftware.intel.com/eula.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module intel_pll (
- inclk0,
- c0,
- c1,
- locked);
-
- input inclk0;
- output c0;
- output c1;
- output locked;
-
- wire [0:0] sub_wire2 = 1'h0;
- wire [4:0] sub_wire3;
- wire sub_wire6;
- wire sub_wire0 = inclk0;
- wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
- wire [1:1] sub_wire5 = sub_wire3[1:1];
- wire [0:0] sub_wire4 = sub_wire3[0:0];
- wire c0 = sub_wire4;
- wire c1 = sub_wire5;
- wire locked = sub_wire6;
-
- altpll altpll_component (
- .inclk (sub_wire1),
- .clk (sub_wire3),
- .locked (sub_wire6),
- .activeclock (),
- .areset (1'b0),
- .clkbad (),
- .clkena ({6{1'b1}}),
- .clkloss (),
- .clkswitch (1'b0),
- .configupdate (1'b0),
- .enable0 (),
- .enable1 (),
- .extclk (),
- .extclkena ({4{1'b1}}),
- .fbin (1'b1),
- .fbmimicbidir (),
- .fbout (),
- .fref (),
- .icdrclk (),
- .pfdena (1'b1),
- .phasecounterselect ({4{1'b1}}),
- .phasedone (),
- .phasestep (1'b1),
- .phaseupdown (1'b1),
- .pllena (1'b1),
- .scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
- .scanread (1'b0),
- .scanwrite (1'b0),
- .sclkout0 (),
- .sclkout1 (),
- .vcooverrange (),
- .vcounderrange ());
- defparam
- altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 1,
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 2,
- altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 1,
- altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 2,
- altpll_component.clk1_phase_shift = "-1500",
- altpll_component.compensate_clock = "CLK0",
- altpll_component.inclk0_input_frequency = 20000,
- altpll_component.intended_device_family = "MAX 10",
- altpll_component.lpm_hint = "CBX_MODULE_PREFIX=intel_pll",
- altpll_component.lpm_type = "altpll",
- altpll_component.operation_mode = "NORMAL",
- altpll_component.pll_type = "AUTO",
- altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_UNUSED",
- altpll_component.port_clkbad0 = "PORT_UNUSED",
- altpll_component.port_clkbad1 = "PORT_UNUSED",
- altpll_component.port_clkloss = "PORT_UNUSED",
- altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
- altpll_component.port_fbin = "PORT_UNUSED",
- altpll_component.port_inclk0 = "PORT_USED",
- altpll_component.port_inclk1 = "PORT_UNUSED",
- altpll_component.port_locked = "PORT_USED",
- altpll_component.port_pfdena = "PORT_UNUSED",
- altpll_component.port_phasecounterselect = "PORT_UNUSED",
- altpll_component.port_phasedone = "PORT_UNUSED",
- altpll_component.port_phasestep = "PORT_UNUSED",
- altpll_component.port_phaseupdown = "PORT_UNUSED",
- altpll_component.port_pllena = "PORT_UNUSED",
- altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
- altpll_component.port_scanread = "PORT_UNUSED",
- altpll_component.port_scanwrite = "PORT_UNUSED",
- altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_USED",
- altpll_component.port_clk2 = "PORT_UNUSED",
- altpll_component.port_clk3 = "PORT_UNUSED",
- altpll_component.port_clk4 = "PORT_UNUSED",
- altpll_component.port_clk5 = "PORT_UNUSED",
- altpll_component.port_clkena0 = "PORT_UNUSED",
- altpll_component.port_clkena1 = "PORT_UNUSED",
- altpll_component.port_clkena2 = "PORT_UNUSED",
- altpll_component.port_clkena3 = "PORT_UNUSED",
- altpll_component.port_clkena4 = "PORT_UNUSED",
- altpll_component.port_clkena5 = "PORT_UNUSED",
- altpll_component.port_extclk0 = "PORT_UNUSED",
- altpll_component.port_extclk1 = "PORT_UNUSED",
- altpll_component.port_extclk2 = "PORT_UNUSED",
- altpll_component.port_extclk3 = "PORT_UNUSED",
- altpll_component.self_reset_on_loss_lock = "ON",
- altpll_component.width_clock = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-54.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "intel_pll.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1500"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
-// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/fw/rtl/vendor/intel/vendor_flash.sv b/fw/rtl/vendor/intel/vendor_flash.sv
deleted file mode 100644
index b19f9a2..0000000
--- a/fw/rtl/vendor/intel/vendor_flash.sv
+++ /dev/null
@@ -1,175 +0,0 @@
-module vendor_flash (
- input clk,
- input reset,
-
- input erase_start,
- output erase_busy,
- input wp_enable,
- input wp_disable,
-
- input request,
- output ack,
- input write,
- input [31:0] address,
- input [31:0] wdata,
- output [31:0] rdata
-);
-
- const int FLASH_SECTORS = 3'd4;
-
- typedef enum bit [1:0] {
- STATE_START,
- STATE_PENDING,
- STATE_ERASING
- } e_erase_state;
-
- typedef enum bit [0:0] {
- CSR_STATUS = 1'b0,
- CSR_CONTROL = 1'b1
- } e_flash_csr;
-
- typedef enum bit [1:0] {
- STATUS_IDLE = 2'b00,
- STATUS_BUSY_ERASE = 2'b01,
- STATUS_BUSY_WRITE = 2'b10,
- STATUS_BUSY_READ = 2'b11
- } e_flash_status;
-
- logic csr_read;
- logic csr_write;
- e_flash_csr csr_address;
- logic [31:0] csr_wdata;
- logic [31:0] csr_rdata;
-
- logic wp_setting;
- logic [2:0] erase_sector;
- e_erase_state state;
-
- always_ff @(posedge clk) begin
- csr_read <= 1'b0;
- csr_write <= 1'b0;
- csr_address <= CSR_STATUS;
-
- if (reset) begin
- erase_busy <= 1'b0;
- wp_setting <= 1'b1;
- end else if (!erase_busy) begin
- if (erase_start) begin
- erase_busy <= 1'b1;
- erase_sector <= 3'd1;
- state <= STATE_START;
- end else if (wp_enable) begin
- csr_write <= 1'b1;
- csr_address <= CSR_CONTROL;
- csr_wdata <= 32'hFFFF_FFFF;
- wp_setting <= 1'b1;
- end else if (wp_disable) begin
- csr_write <= 1'b1;
- csr_address <= CSR_CONTROL;
- csr_wdata <= 32'hF07F_FFFF;
- wp_setting <= 1'b0;
- end
- end else begin
- csr_read <= 1'b1;
-
- case (state)
- STATE_START: begin
- if (csr_read && (csr_rdata[1:0] == STATUS_IDLE)) begin
- csr_read <= 1'b0;
- csr_write <= 1'b1;
- csr_address <= CSR_CONTROL;
- csr_wdata <= {4'hF, {5{wp_setting}}, erase_sector, 20'hFFFFF};
- state <= STATE_PENDING;
- end
- end
-
- STATE_PENDING: begin
- if (csr_read && (csr_rdata[1:0] == STATUS_BUSY_ERASE)) begin
- state <= STATE_ERASING;
- end
- end
-
- STATE_ERASING: begin
- if (csr_read && (csr_rdata[1:0] == STATUS_IDLE)) begin
- if (erase_sector == FLASH_SECTORS) begin
- erase_busy <= 1'b0;
- end else begin
- erase_sector <= erase_sector + 1'd1;
- state <= STATE_START;
- end
- end
- end
- endcase
- end
- end
-
- logic data_read;
- logic data_write;
- logic data_busy;
- logic data_ack;
- logic [15:0] data_address;
- logic [31:0] data_wdata;
- logic [31:0] data_rdata;
-
- logic pending;
- logic write_ack;
-
- always_ff @(posedge clk) begin
- write_ack <= 1'b0;
-
- if (reset) begin
- data_read <= 1'b0;
- data_write <= 1'b0;
- pending <= 1'b0;
- end else begin
- if (request && !pending && !erase_busy) begin
- pending <= 1'b1;
- if (write && !wp_setting) begin
- data_write <= 1'b1;
- end else begin
- data_read <= 1'b1;
- end
- end
-
- if (data_read && !data_busy) begin
- data_read <= 1'b0;
- end
-
- if (data_write && !data_busy) begin
- data_write <= 1'b0;
- pending <= 1'b0;
- write_ack <= 1'b1;
- end
-
- if (data_ack) begin
- pending <= 1'b0;
- end
- end
- end
-
- always_comb begin
- ack = data_ack || write_ack;
- data_address = address[17:2];
- end
-
- intel_flash intel_flash_inst (
- .clock(clk),
- .reset_n(~reset),
-
- .avmm_csr_read(csr_read),
- .avmm_csr_write(csr_write),
- .avmm_csr_addr(csr_address),
- .avmm_csr_writedata(csr_wdata),
- .avmm_csr_readdata(csr_rdata),
-
- .avmm_data_read(data_read),
- .avmm_data_write(data_write),
- .avmm_data_waitrequest(data_busy),
- .avmm_data_readdatavalid(data_ack),
- .avmm_data_addr(data_address),
- .avmm_data_writedata(wdata),
- .avmm_data_readdata(rdata),
- .avmm_data_burstcount(2'd1)
- );
-
-endmodule
diff --git a/fw/rtl/vendor/intel/vendor_reconfigure.sv b/fw/rtl/vendor/intel/vendor_reconfigure.sv
deleted file mode 100644
index 70e3f55..0000000
--- a/fw/rtl/vendor/intel/vendor_reconfigure.sv
+++ /dev/null
@@ -1,42 +0,0 @@
-module vendor_reconfigure (
- input clk,
- input reset,
-
- input trigger_reconfiguration
-);
-
- logic [1:0] ru_clk;
- logic ru_rconfig;
- logic ru_regout;
-
- logic pending;
-
- always_ff @(posedge clk) begin
- if (reset) begin
- ru_clk <= 2'd0;
- ru_rconfig <= 1'b0;
- pending <= 1'b0;
- end else begin
- ru_clk <= ru_clk + 1'd1;
-
- if (trigger_reconfiguration) begin
- pending <= 1'b1;
- end
-
- if (ru_clk == 2'd1) begin
- ru_rconfig <= pending;
- end
- end
- end
-
- fiftyfivenm_rublock fiftyfivenm_rublock_inst (
- .clk(ru_clk[1]),
- .shiftnld(1'b0),
- .captnupdt(1'b0),
- .regin(1'b0),
- .rsttimer(1'b0),
- .rconfig(ru_rconfig),
- .regout(ru_regout)
- );
-
-endmodule
diff --git a/fw/rtl/vendor/lcmxo2/fifo_8kb.sv b/fw/rtl/vendor/lcmxo2/fifo_8kb.sv
new file mode 100644
index 0000000..a8ef3a7
--- /dev/null
+++ b/fw/rtl/vendor/lcmxo2/fifo_8kb.sv
@@ -0,0 +1,31 @@
+module fifo_8kb (
+ input clk,
+ input reset,
+
+ output empty,
+ output almost_empty,
+ input read,
+ output [7:0] rdata,
+
+ output full,
+ output almost_full,
+ input write,
+ input [7:0] wdata
+);
+
+ fifo_8kb_lattice_generated fifo_8kb_lattice_generated_inst (
+ .Data(wdata),
+ .WrClock(clk),
+ .RdClock(clk),
+ .WrEn(write),
+ .RdEn(read),
+ .Reset(reset),
+ .RPReset(reset),
+ .Q(rdata),
+ .Empty(empty),
+ .Full(full),
+ .AlmostEmpty(almost_empty),
+ .AlmostFull(almost_full)
+ );
+
+endmodule
diff --git a/fw/rtl/vendor/lcmxo2/generated/fifo_8kb_lattice_generated.v b/fw/rtl/vendor/lcmxo2/generated/fifo_8kb_lattice_generated.v
new file mode 100644
index 0000000..dcf16bd
--- /dev/null
+++ b/fw/rtl/vendor/lcmxo2/generated/fifo_8kb_lattice_generated.v
@@ -0,0 +1,66 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
+/* Module Version: 5.8 */
+/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n fifo_8kb_lattice_generated -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 1024 -width 8 -rwidth 8 -no_enable -pe 1 -pf 1023 */
+/* Sat Mar 19 13:53:20 2022 */
+
+
+`timescale 1 ns / 1 ps
+module fifo_8kb_lattice_generated (Data, WrClock, RdClock, WrEn, RdEn,
+ Reset, RPReset, Q, Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
+ input wire [7:0] Data;
+ input wire WrClock;
+ input wire RdClock;
+ input wire WrEn;
+ input wire RdEn;
+ input wire Reset;
+ input wire RPReset;
+ output wire [7:0] Q;
+ output wire Empty;
+ output wire Full;
+ output wire AlmostEmpty;
+ output wire AlmostFull;
+
+ wire scuba_vhi;
+ wire Empty_int;
+ wire Full_int;
+ wire scuba_vlo;
+
+ VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ defparam fifo_8kb_lattice_generated_0_0.FULLPOINTER1 = "0b01111111111000" ;
+ defparam fifo_8kb_lattice_generated_0_0.FULLPOINTER = "0b10000000000000" ;
+ defparam fifo_8kb_lattice_generated_0_0.AFPOINTER1 = "0b01111111110000" ;
+ defparam fifo_8kb_lattice_generated_0_0.AFPOINTER = "0b01111111111000" ;
+ defparam fifo_8kb_lattice_generated_0_0.AEPOINTER1 = "0b00000000010000" ;
+ defparam fifo_8kb_lattice_generated_0_0.AEPOINTER = "0b00000000001000" ;
+ defparam fifo_8kb_lattice_generated_0_0.ASYNC_RESET_RELEASE = "SYNC" ;
+ defparam fifo_8kb_lattice_generated_0_0.GSR = "DISABLED" ;
+ defparam fifo_8kb_lattice_generated_0_0.RESETMODE = "ASYNC" ;
+ defparam fifo_8kb_lattice_generated_0_0.REGMODE = "NOREG" ;
+ defparam fifo_8kb_lattice_generated_0_0.CSDECODE_R = "0b11" ;
+ defparam fifo_8kb_lattice_generated_0_0.CSDECODE_W = "0b11" ;
+ defparam fifo_8kb_lattice_generated_0_0.DATA_WIDTH_R = 9 ;
+ defparam fifo_8kb_lattice_generated_0_0.DATA_WIDTH_W = 9 ;
+ FIFO8KB fifo_8kb_lattice_generated_0_0 (.DI0(Data[0]), .DI1(Data[1]),
+ .DI2(Data[2]), .DI3(Data[3]), .DI4(Data[4]), .DI5(Data[5]), .DI6(Data[6]),
+ .DI7(Data[7]), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo),
+ .DI11(scuba_vlo), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo),
+ .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi),
+ .CSW1(scuba_vhi), .CSR0(scuba_vhi), .CSR1(scuba_vhi), .FULLI(Full_int),
+ .EMPTYI(Empty_int), .WE(WrEn), .RE(RdEn), .ORE(RdEn), .CLKW(WrClock),
+ .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[0]), .DO1(Q[1]),
+ .DO2(Q[2]), .DO3(Q[3]), .DO4(Q[4]), .DO5(Q[5]), .DO6(Q[6]), .DO7(Q[7]),
+ .DO8(), .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(),
+ .DO16(), .DO17(), .EF(Empty_int), .AEF(AlmostEmpty), .AFF(AlmostFull),
+ .FF(Full_int));
+
+ assign Empty = Empty_int;
+ assign Full = Full_int;
+
+
+ // exemplar begin
+ // exemplar end
+
+endmodule
diff --git a/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v b/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v
new file mode 100644
index 0000000..5f3ad98
--- /dev/null
+++ b/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v
@@ -0,0 +1,98 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
+/* Module Version: 5.7 */
+/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll_lattice_generated -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 100 -fclkop_tol 0.0 -fclkos 100 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 90 -trims_r -phase_cntl STATIC -fb_mode 1 -lock */
+/* Sat Mar 19 17:10:12 2022 */
+
+
+`timescale 1 ns / 1 ps
+module pll_lattice_generated (CLKI, CLKOP, CLKOS, LOCK)/* synthesis NGD_DRC_MASK=1 */;
+ input wire CLKI;
+ output wire CLKOP;
+ output wire CLKOS;
+ output wire LOCK;
+
+ wire CLKOS_t;
+ wire CLKOP_t;
+ wire scuba_vlo;
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
+ defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
+ defparam PLLInst_0.MRST_ENA = "DISABLED" ;
+ defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
+ defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
+ defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
+ defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
+ defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
+ defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
+ defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
+ defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
+ defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
+ defparam PLLInst_0.CLKOS_FPHASE = 2 ;
+ defparam PLLInst_0.CLKOS_CPHASE = 5 ;
+ defparam PLLInst_0.CLKOP_FPHASE = 0 ;
+ defparam PLLInst_0.CLKOP_CPHASE = 4 ;
+ defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
+ defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
+ defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ;
+ defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
+ defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
+ defparam PLLInst_0.FRACN_DIV = 0 ;
+ defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
+ defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
+ defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
+ defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
+ defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
+ defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
+ defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
+ defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
+ defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
+ defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
+ defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
+ defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
+ defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
+ defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
+ defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
+ defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
+ defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
+ defparam PLLInst_0.CLKOS3_DIV = 1 ;
+ defparam PLLInst_0.CLKOS2_DIV = 1 ;
+ defparam PLLInst_0.CLKOS_DIV = 5 ;
+ defparam PLLInst_0.CLKOP_DIV = 5 ;
+ defparam PLLInst_0.CLKFB_DIV = 2 ;
+ defparam PLLInst_0.CLKI_DIV = 1 ;
+ defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
+ EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
+ .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
+ .LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
+ .RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
+ .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo),
+ .ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo),
+ .PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
+ .PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
+ .PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
+ .PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
+ .PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(),
+ .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(),
+ .PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
+ .PLLDATO2(), .PLLDATO1(), .PLLDATO0())
+ /* synthesis FREQUENCY_PIN_CLKOS="100.000000" */
+ /* synthesis FREQUENCY_PIN_CLKOP="100.000000" */
+ /* synthesis FREQUENCY_PIN_CLKI="50.000000" */
+ /* synthesis ICP_CURRENT="9" */
+ /* synthesis LPF_RESISTOR="72" */;
+
+ assign CLKOS = CLKOS_t;
+ assign CLKOP = CLKOP_t;
+
+
+ // exemplar begin
+ // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 100.000000
+ // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 100.000000
+ // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 50.000000
+ // exemplar attribute PLLInst_0 ICP_CURRENT 9
+ // exemplar attribute PLLInst_0 LPF_RESISTOR 72
+ // exemplar end
+
+endmodule
diff --git a/fw/rtl/vendor/lcmxo2/pll.sv b/fw/rtl/vendor/lcmxo2/pll.sv
new file mode 100644
index 0000000..30c63d4
--- /dev/null
+++ b/fw/rtl/vendor/lcmxo2/pll.sv
@@ -0,0 +1,36 @@
+module pll (
+ input inclk,
+ output logic reset,
+ output clk,
+ output sdram_clk
+);
+
+ logic pll_sdram_clk;
+ logic buf_sdram_clk;
+ logic pll_lock;
+
+ pll_lattice_generated pll_lattice_generated_inst (
+ .CLKI(inclk),
+ .CLKOP(clk),
+ .CLKOS(pll_sdram_clk),
+ .LOCK(pll_lock)
+ );
+
+ ODDRXE oddrxe_sdram_clk_inst (
+ .D0(1'b0),
+ .D1(1'b1),
+ .SCLK(pll_sdram_clk),
+ .RST(1'b0),
+ .Q(buf_sdram_clk)
+ );
+
+ OB ob_sdram_clk_inst (
+ .I(buf_sdram_clk),
+ .O(sdram_clk)
+ ) /* synthesis IO_TYPE="LVCMOS33" */;
+
+ always_ff @(posedge clk) begin
+ reset <= ~pll_lock;
+ end
+
+endmodule
diff --git a/fw/scripts/post_module.tcl b/fw/scripts/post_module.tcl
deleted file mode 100644
index ed19714..0000000
--- a/fw/scripts/post_module.tcl
+++ /dev/null
@@ -1,6 +0,0 @@
-set flow [lindex $quartus(args) 0]
-
-if [string match "quartus_asm" $flow] {
- post_message "Generating final programming file"
- qexec "quartus_cpf -c SummerCart64.cof"
-}
diff --git a/hw/.gitignore b/hw/.gitignore
deleted file mode 100644
index 110ec6d..0000000
--- a/hw/.gitignore
+++ /dev/null
@@ -1,7 +0,0 @@
-/CAMOutputs
-*.b#*
-*.l#*
-*.s#*
-*.pdf
-*.zip
-eagle.epf
diff --git a/hw/README.md b/hw/README.md
deleted file mode 100644
index 4960309..0000000
--- a/hw/README.md
+++ /dev/null
@@ -1,7 +0,0 @@
-# SummerCart64 Hardware
-
-Schematics and PCB design for SummerCart64 done in Autodesk Eagle software.
-
-## TODO
-
-- Expand documentation
diff --git a/hw/SummerCart64.brd b/hw/SummerCart64.brd
deleted file mode 100644
index 9366456..0000000
--- a/hw/SummerCart64.brd
+++ /dev/null
@@ -1,5643 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-SummerCart64
-N64 FlashCart/DevKit
-SummerCart64
-N64 FlashCart/DevKit
-HW version: 1.0a
-Designed by Polprzewodnikowy
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->NAME
->VALUE
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-Footprint for Nintendo 64 cartridge edge connector.
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-26
-30
-35
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-45
-50
-1
-5
-10
-15
-20
-25
-BACK
-FRONT
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->NAME
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->NAME
->VALUE
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->NAME
->VALUE
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->NAME
->VALUE
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-
-<b>MICRON Flash Memory</b><p>
-www.micron.com<br>
-<author>Created by librarian@cadsoft.de</author><p>
-
-
-<b>54-Pin Plastic TSOP</b> (400 mil)<p>
-Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf
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-54-Pin Plastic TSOP (400 mil)
-Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf
-
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-
-
-<b>Resistors in DIL Packages</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>BOURNS</b> Chip Resistor Array<p>
-Source: RS Component / BUORNS
-
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->NAME
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-
-BOURNS Chip Resistor Array
-Source: RS Component / BUORNS
-
-
-
-
-
-
-
-<b>Resistors, Capacitors, Inductors</b><p>
-Based on the previous libraries:
-<ul>
-<li>r.lbr
-<li>cap.lbr
-<li>cap-fe.lbr
-<li>captant.lbr
-<li>polcap.lbr
-<li>ipc-smd.lbr
-</ul>
-All SMD packages are defined according to the IPC specifications and CECC<p>
-<author>Created by librarian@cadsoft.de</author><p>
-<p>
-for Electrolyt Capacitors see also :<p>
-www.bccomponents.com <p>
-www.panasonic.com<p>
-www.kemet.com<p>
-http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
-<p>
-for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
-
-<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
-<tr valign="top">
-
-<! <td width="10"> </td>
-<td width="90%">
-
-<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
-<P>
-<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
- </B>
- </TD><TD> </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
- 3005P<BR>
- 3006P<BR>
- 3006W<BR>
- 3006Y<BR>
- 3009P<BR>
- 3009W<BR>
- 3009Y<BR>
- 3057J<BR>
- 3057L<BR>
- 3057P<BR>
- 3057Y<BR>
- 3059J<BR>
- 3059L<BR>
- 3059P<BR>
- 3059Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 89P<BR>
- 89W<BR>
- 89X<BR>
- 89PH<BR>
- 76P<BR>
- 89XH<BR>
- 78SLT<BR>
- 78L ALT<BR>
- 56P ALT<BR>
- 78P ALT<BR>
- T8S<BR>
- 78L<BR>
- 56P<BR>
- 78P<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- T18/784<BR>
- 783<BR>
- 781<BR>
- -<BR>
- -<BR>
- -<BR>
- 2199<BR>
- 1697/1897<BR>
- 1680/1880<BR>
- 2187<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 8035EKP/CT20/RJ-20P<BR>
- -<BR>
- RJ-20X<BR>
- -<BR>
- -<BR>
- -<BR>
- 1211L<BR>
- 8012EKQ ALT<BR>
- 8012EKR ALT<BR>
- 1211P<BR>
- 8012EKJ<BR>
- 8012EKL<BR>
- 8012EKQ<BR>
- 8012EKR<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 2101P<BR>
- 2101W<BR>
- 2101Y<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 2102L<BR>
- 2102S<BR>
- 2102Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- EVMCOG<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 43P<BR>
- 43W<BR>
- 43Y<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 40L<BR>
- 40P<BR>
- 40Y<BR>
- 70Y-T602<BR>
- 70L<BR>
- 70P<BR>
- 70Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- RT/RTR12<BR>
- RT/RTR12<BR>
- RT/RTR12<BR>
- -<BR>
- RJ/RJR12<BR>
- RJ/RJR12<BR>
- RJ/RJR12<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3250L<BR>
- 3250P<BR>
- 3250W<BR>
- 3250X<BR>
- 3252P<BR>
- 3252W<BR>
- 3252X<BR>
- 3260P<BR>
- 3260W<BR>
- 3260X<BR>
- 3262P<BR>
- 3262W<BR>
- 3262X<BR>
- 3266P<BR>
- 3266W<BR>
- 3266X<BR>
- 3290H<BR>
- 3290P<BR>
- 3290W<BR>
- 3292P<BR>
- 3292W<BR>
- 3292X<BR>
- 3296P<BR>
- 3296W<BR>
- 3296X<BR>
- 3296Y<BR>
- 3296Z<BR>
- 3299P<BR>
- 3299W<BR>
- 3299X<BR>
- 3299Y<BR>
- 3299Z<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66X ALT<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66X ALT<BR>
- -<BR>
- 64W ALT<BR>
- -<BR>
- 64P ALT<BR>
- 64W ALT<BR>
- 64X ALT<BR>
- 64P<BR>
- 64W<BR>
- 64X<BR>
- 66X ALT<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66P<BR>
- 66W<BR>
- 66X<BR>
- 67P<BR>
- 67W<BR>
- 67X<BR>
- 67Y<BR>
- 67Z<BR>
- 68P<BR>
- 68W<BR>
- 68X<BR>
- 67Y ALT<BR>
- 67Z ALT<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 5050<BR>
- 5091<BR>
- 5080<BR>
- 5087<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- T63YB<BR>
- T63XB<BR>
- -<BR>
- -<BR>
- -<BR>
- 5887<BR>
- 5891<BR>
- 5880<BR>
- -<BR>
- -<BR>
- -<BR>
- T93Z<BR>
- T93YA<BR>
- T93XA<BR>
- T93YB<BR>
- T93XB<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 8026EKP<BR>
- 8026EKW<BR>
- 8026EKM<BR>
- 8026EKP<BR>
- 8026EKB<BR>
- 8026EKM<BR>
- 1309X<BR>
- 1309P<BR>
- 1309W<BR>
- 8024EKP<BR>
- 8024EKW<BR>
- 8024EKN<BR>
- RJ-9P/CT9P<BR>
- RJ-9W<BR>
- RJ-9X<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3103P<BR>
- 3103Y<BR>
- 3103Z<BR>
- 3103P<BR>
- 3103Y<BR>
- 3103Z<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3105P/3106P<BR>
- 3105W/3106W<BR>
- 3105X/3106X<BR>
- 3105Y/3106Y<BR>
- 3105Z/3105Z<BR>
- 3102P<BR>
- 3102W<BR>
- 3102X<BR>
- 3102Y<BR>
- 3102Z<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMCBG<BR>
- EVMCCG<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 55-1-X<BR>
- 55-4-X<BR>
- 55-3-X<BR>
- 55-2-X<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 50-2-X<BR>
- 50-4-X<BR>
- 50-3-X<BR>
- -<BR>
- -<BR>
- -<BR>
- 64P<BR>
- 64W<BR>
- 64X<BR>
- 64Y<BR>
- 64Z<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RJ/RJR22<BR>
- RJ/RJR22<BR>
- RJ/RJR22<BR>
- RT/RTR26<BR>
- RT/RTR26<BR>
- RT/RTR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RT/RTR24<BR>
- RT/RTR24<BR>
- RT/RTR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3323P<BR>
- 3323S<BR>
- 3323W<BR>
- 3329H<BR>
- 3329P<BR>
- 3329W<BR>
- 3339H<BR>
- 3339P<BR>
- 3339W<BR>
- 3352E<BR>
- 3352H<BR>
- 3352K<BR>
- 3352P<BR>
- 3352T<BR>
- 3352V<BR>
- 3352W<BR>
- 3362H<BR>
- 3362M<BR>
- 3362P<BR>
- 3362R<BR>
- 3362S<BR>
- 3362U<BR>
- 3362W<BR>
- 3362X<BR>
- 3386B<BR>
- 3386C<BR>
- 3386F<BR>
- 3386H<BR>
- 3386K<BR>
- 3386M<BR>
- 3386P<BR>
- 3386S<BR>
- 3386W<BR>
- 3386X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 25P<BR>
- 25S<BR>
- 25RX<BR>
- 82P<BR>
- 82M<BR>
- 82PA<BR>
- -<BR>
- -<BR>
- -<BR>
- 91E<BR>
- 91X<BR>
- 91T<BR>
- 91B<BR>
- 91A<BR>
- 91V<BR>
- 91W<BR>
- 25W<BR>
- 25V<BR>
- 25P<BR>
- -<BR>
- 25S<BR>
- 25U<BR>
- 25RX<BR>
- 25X<BR>
- 72XW<BR>
- 72XL<BR>
- 72PM<BR>
- 72RX<BR>
- -<BR>
- 72PX<BR>
- 72P<BR>
- 72RXW<BR>
- 72RXL<BR>
- 72X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- T7YB<BR>
- T7YA<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- TXD<BR>
- TYA<BR>
- TYP<BR>
- -<BR>
- TYD<BR>
- TX<BR>
- -<BR>
- 150SX<BR>
- 100SX<BR>
- 102T<BR>
- 101S<BR>
- 190T<BR>
- 150TX<BR>
- 101<BR>
- -<BR>
- -<BR>
- 101SX<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ET6P<BR>
- ET6S<BR>
- ET6X<BR>
- RJ-6W/8014EMW<BR>
- RJ-6P/8014EMP<BR>
- RJ-6X/8014EMX<BR>
- TM7W<BR>
- TM7P<BR>
- TM7X<BR>
- -<BR>
- 8017SMS<BR>
- -<BR>
- 8017SMB<BR>
- 8017SMA<BR>
- -<BR>
- -<BR>
- CT-6W<BR>
- CT-6H<BR>
- CT-6P<BR>
- CT-6R<BR>
- -<BR>
- CT-6V<BR>
- CT-6X<BR>
- -<BR>
- -<BR>
- 8038EKV<BR>
- -<BR>
- 8038EKX<BR>
- -<BR>
- -<BR>
- 8038EKP<BR>
- 8038EKZ<BR>
- 8038EKW<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- 3321H<BR>
- 3321P<BR>
- 3321N<BR>
- 1102H<BR>
- 1102P<BR>
- 1102T<BR>
- RVA0911V304A<BR>
- -<BR>
- RVA0911H413A<BR>
- RVG0707V100A<BR>
- RVA0607V(H)306A<BR>
- RVA1214H213A<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3104B<BR>
- 3104C<BR>
- 3104F<BR>
- 3104H<BR>
- -<BR>
- 3104M<BR>
- 3104P<BR>
- 3104S<BR>
- 3104W<BR>
- 3104X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- EVMQ0G<BR>
- EVMQIG<BR>
- EVMQ3G<BR>
- EVMS0G<BR>
- EVMQ0G<BR>
- EVMG0G<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMK4GA00B<BR>
- EVM30GA00B<BR>
- EVMK0GA00B<BR>
- EVM38GA00B<BR>
- EVMB6<BR>
- EVLQ0<BR>
- -<BR>
- EVMMSG<BR>
- EVMMBG<BR>
- EVMMAG<BR>
- -<BR>
- -<BR>
- EVMMCS<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMM1<BR>
- -<BR>
- -<BR>
- EVMM0<BR>
- -<BR>
- -<BR>
- EVMM3<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- 62-3-1<BR>
- 62-1-2<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 67R<BR>
- -<BR>
- 67P<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 67X<BR>
- 63V<BR>
- 63S<BR>
- 63M<BR>
- -<BR>
- -<BR>
- 63H<BR>
- 63P<BR>
- -<BR>
- -<BR>
- 63X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- RJ/RJR50<BR>
- RJ/RJR50<BR>
- RJ/RJR50<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
-</TABLE>
-<P> <P>
-<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
- <TR>
- <TD COLSPAN=7>
- <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
- <P>
- <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3224G<BR>
- 3224J<BR>
- 3224W<BR>
- 3269P<BR>
- 3269W<BR>
- 3269X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 44G<BR>
- 44J<BR>
- 44W<BR>
- 84P<BR>
- 84W<BR>
- 84X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- ST63Z<BR>
- ST63Y<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- ST5P<BR>
- ST5W<BR>
- ST5X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=7>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=7>
- <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3314G<BR>
- 3314J<BR>
- 3364A/B<BR>
- 3364C/D<BR>
- 3364W/X<BR>
- 3313G<BR>
- 3313J<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 23B<BR>
- 23A<BR>
- 21X<BR>
- 21W<BR>
- -<BR>
- 22B<BR>
- 22A<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ST5YL/ST53YL<BR>
- ST5YJ/5T53YJ<BR>
- ST-23A<BR>
- ST-22B<BR>
- ST-22<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ST-4B<BR>
- ST-4A<BR>
- -<BR>
- -<BR>
- -<BR>
- ST-3B<BR>
- ST-3A<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- EVM-6YS<BR>
- EVM-1E<BR>
- EVM-1G<BR>
- EVM-1D<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- G4B<BR>
- G4A<BR>
- TR04-3S1<BR>
- TRG04-2S1<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- DVR-43A<BR>
- CVR-42C<BR>
- CVR-42A/C<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
-</TABLE>
-<P>
-<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
-<P>
-
-
-<P>
-</td>
-</tr>
-</table>
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b><p>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-
-
-<b>TTL Devices, 74xx Series with European Symbols</b><p>
-Based on the following sources:
-<ul>
-<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
-<li>TTL Data Book, Volume 2 , 1993
-<li>National Seminconductor Databook 1990, ALS/LS Logic
-<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
-<li>http://icmaster.com/ViewCompare.asp
-</ul>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>plastic thin shrink small outline package; 14 leads; body width 4.4 mm</b><p>
-SOT402-1<br>
-Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
->NAME
->VALUE
-
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-
-
-
-
-
-
-
-
-plastic thin shrink small outline package; 14 leads; body width 4.4 mm
-SOT402-1
-Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf
-
-
-
-
-
-
-
-<b>Crystals and Crystal Resonators</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>kHz RANGE CRYSTAL UNIT</b><p>
-LOW PROFILE SMD<b>
-Source: Epson Toyocom FC-12M.pdf
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-kHz RANGE CRYSTAL UNIT
-LOW PROFILE SMD
-Source: Epson Toyocom FC-12M.pdf
-
-
-
-
-
-
-
-<b>Lithium Batteries and NC Accus</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>Battery Holder, SMT, 12mm</b><p>
-multicomp PART NO. CH291-1220LF<br>
-Source: <a href="http://www.farnell.com/datasheets/1505860.pdf"> Data sheet </a>
-
-
-
-
-
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-
->NAME
->VALUE
-
-
-
-
-
-
-Battery Holder, SMT, 12mm
-multicomp PART NO. CH291-1220LF
-Source: Data sheet
-
-
-
-
-
-
-
-<b>Diodes</b><p>
-Based on the following sources:
-<ul>
-<li>Motorola : www.onsemi.com
-<li>Fairchild : www.fairchildsemi.com
-<li>Philips : www.semiconductors.com
-<li>Vishay : www.vishay.de
-</ul>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>SOD-323</b><p>
-Source: www.st.com, BAT60J.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-SOD-323
-Source: www.st.com, BAT60J.pdf
-
-
-
-
-
-
-
-<b>Samtec Connectors</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p>
-Source: Samtec SSW.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
-
-
-
-
-1
-2
->NAME
->VALUE
-
-
-
-
-<b>LEDs</b><p>
-<author>Created by librarian@cadsoft.de</author><br>
-Extended by Federico Battaglin <author><federico.rd@fdpinternational.com></author> with DUOLED
-
-
-<b>SML0603-XXX (HIGH INTENSITY) LED</b><p>
-<table>
-<tr><td>AG3K</td><td>AQUA GREEN</td></tr>
-<tr><td>B1K</td><td>SUPER BLUE</td></tr>
-<tr><td>R1K</td><td>SUPER RED</td></tr>
-<tr><td>R3K</td><td>ULTRA RED</td></tr>
-<tr><td>O3K</td><td>SUPER ORANGE</td></tr>
-<tr><td>O3KH</td><td>SOFT ORANGE</td></tr>
-<tr><td>Y3KH</td><td>SUPER YELLOW</td></tr>
-<tr><td>Y3K</td><td>SUPER YELLOW</td></tr>
-<tr><td>2CW</td><td>WHITE</td></tr>
-</table>
-Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-SML0603-XXX (HIGH INTENSITY) LED
-
-AG3KAQUA GREEN
-B1KSUPER BLUE
-R1KSUPER RED
-R3KULTRA RED
-O3KSUPER ORANGE
-O3KHSOFT ORANGE
-Y3KHSUPER YELLOW
-Y3KSUPER YELLOW
-2CWWHITE
-
-Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf
-
-
-
-
-
-
-
-<b>Voltage Regulators</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>Small Outline Transistor 223</b><p>
-PLASTIC PACKAGE CASE 318E-04<br>
-Source: http://www.onsemi.co.jp .. LM137M-D.PDF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-direction of pcb
-transportation for
-wavesoldering
-
-
-
-
-
-
-
-
-
-
-
-
-Small Outline Transistor 223
-PLASTIC PACKAGE CASE 318E-04
-Source: http://www.onsemi.co.jp .. LM137M-D.PDF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>EAGLE Design Rules</b>
-<p>
-Die Standard-Design-Rules sind so gewählt, dass sie für
-die meisten Anwendungen passen. Sollte ihre Platine
-besondere Anforderungen haben, treffen Sie die erforderlichen
-Einstellungen hier und speichern die Design Rules unter
-einem neuen Namen ab.
-<b>EAGLE Design Rules</b>
-<p>
-The default Design Rules have been set to cover
-a wide range of applications. Your particular design
-may have different requirements, so please make the
-necessary adjustments and save your customized
-design rules under a new name.
-
-
-
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-
-
-
-Since Version 6.2.2 text objects can contain more than one line,
-which will not be processed correctly with this version.
-
-
-Since Version 8.2, EAGLE supports online libraries. The ids
-of those online libraries will not be understood (or retained)
-with this version.
-
-
-Since Version 8.3, EAGLE supports URNs for individual library
-assets (packages, symbols, and devices). The URNs of those assets
-will not be understood (or retained) with this version.
-
-
-Since Version 8.3, EAGLE supports the association of 3D packages
-with devices in libraries, schematics, and board files. Those 3D
-packages will not be understood (or retained) with this version.
-
-
-
diff --git a/hw/SummerCart64.cam b/hw/SummerCart64.cam
deleted file mode 100644
index 3c5f3aa..0000000
--- a/hw/SummerCart64.cam
+++ /dev/null
@@ -1,276 +0,0 @@
-{
- "author": {
- "email": "sc@mateuszfaderewski.pl",
- "name": "Polprzewodnikowy"
- },
- "description": {
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- },
- "output_type": "zip",
- "outputs": [
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- "name": "Soldermask Bottom",
- "polarity": "positive",
- "type": "gerber_layer"
- },
- {
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- "rotate": false,
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- ],
- "milling": false,
- "name": "Silkscreen Bottom",
- "polarity": "positive",
- "type": "gerber_layer"
- }
- ],
- "version": "RS274X"
- },
- {
- "filename_prefix": "CAMOutputs/DrillFiles",
- "format_specifier": {
- "decimal": 3,
- "integer": 3
- },
- "output_type": "drill",
- "outputs": [
- {
- "advanced_options": {
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- "offset_y": 0,
- "rotate": false,
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- },
- "filename_format": "%DRILLPREFIX/drill_%FROM_%TO.xln",
- "name": "Auto Drill",
- "type": "autodrills"
- }
- ]
- },
- {
- "filename_prefix": "CAMOutputs/Assembly",
- "output_type": "assembly",
- "outputs": [
- {
- "filename_format": "%ASSEMBLYPREFIX/%N",
- "list_attribute": true,
- "list_type": "values",
- "name": "Bill of Material",
- "output_format": "txt",
- "type": "bom"
- }
- ]
- },
- {
- "filename_prefix": "CAMOutputs/DrawingFiles",
- "output_type": "drawing",
- "outputs": [
- ]
- }
- ],
- "timestamp": "2020-10-25T01:41:35",
- "type": "EAGLE CAM job",
- "units": "metric",
- "version": "9.2.0"
-}
diff --git a/hw/SummerCart64.lbr b/hw/SummerCart64.lbr
deleted file mode 100644
index f2284ad..0000000
--- a/hw/SummerCart64.lbr
+++ /dev/null
@@ -1,1532 +0,0 @@
-
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-Collection of parts used in SummerCart64 design
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->NAME
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-Footprint for Nintendo 64 cartridge edge connector.
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-26
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-Nintendo 64 cartridge edge connector.
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diff --git a/hw/SummerCart64.sch b/hw/SummerCart64.sch
deleted file mode 100644
index ccde1f7..0000000
--- a/hw/SummerCart64.sch
+++ /dev/null
@@ -1,17889 +0,0 @@
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->NAME
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-Footprint for Nintendo 64 cartridge edge connector.
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-26
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-BACK
-FRONT
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-Symbol for Nintendo 64 cartridge edge connector.
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-Nintendo 64 cartridge edge connector.
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-
-<b>Supply Symbols</b><p>
- GND, VCC, 0V, +5V, -5V, etc.<p>
- Please keep in mind, that these devices are necessary for the
- automatic wiring of the supply signals.<p>
- The pin name defined in the symbol is identical to the net which is to be wired automatically.<p>
- In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p>
- <author>Created by librarian@cadsoft.de</author>
-
-
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->VALUE
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-<b>SUPPLY SYMBOL</b>
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-<b>SUPPLY SYMBOL</b>
-
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-
-
-<b>MICRON Flash Memory</b><p>
-www.micron.com<br>
-<author>Created by librarian@cadsoft.de</author><p>
-
-
-<b>54-Pin Plastic TSOP</b> (400 mil)<p>
-Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf
-
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-
-54-Pin Plastic TSOP (400 mil)
-Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf
-
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-
-<b>256Mb: x16 SDRAM</b> MT48LC16M16A2 - 4 Meg x 16 x 4 banks<p>
-Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf
-
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-
-
-<b>Resistors in DIL Packages</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>Chip Resistor Array</b> size 4 × 0603<p>
-concave termination - Phycomp Components<br>
-Source: RS Components
-
-
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->NAME
->VALUE
-
-
-<b>Chip Resistor Array</b> size 4 × 0603<p>
-convex termination - Phycomp Components<br>
-Source: RS Components
-
-
-
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-
-<b>BOURNS</b> Chip Resistor Array<p>
-Source: RS Component / BUORNS
-
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-
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-<b>BOURNS</b> Chip Resistor Array<p>
-Source: RS Component / BUORNS
-
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->NAME
->VALUE
-
-
-<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p>
-Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
-
-
-
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->NAME
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-
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-
-
-<b>Array chip resistor</b> size 4 × 0402<p>
-Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
-
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->VALUE
-
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-
-
-<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p>
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
-
-
-
-
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->NAME
->VALUE
-
-
-<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
-Source: PANASONIC .. aoc0000ce1.pdf
-
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->NAME
->VALUE
-
-
-<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p>
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
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->NAME
->VALUE
-
-
-<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
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->NAME
->VALUE
-
-
-<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p>
-Source: PANASONIC .. aoc0000ce1.pdf
-
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->NAME
->VALUE
-
-
-<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
-
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->NAME
->VALUE
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-Chip Resistor Array size 4 × 0603
-concave termination - Phycomp Components
-Source: RS Components
-
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-
-
-Chip Resistor Array size 4 × 0603
-convex termination - Phycomp Components
-Source: RS Components
-
-
-
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-
-BOURNS Chip Resistor Array
-Source: RS Component / BUORNS
-
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-BOURNS Chip Resistor Array
-Source: RS Component / BUORNS
-
-
-
-
-
-ARRAY CHIP RESISTOR Size 4 x 0402
-Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
-
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-
-
-Array chip resistor size 4 × 0402
-Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
-
-
-
-
-
-Chip Resistor Array 0201x4 4 resistors in 1.4 mm x 0.6 mm size
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
-
-
-
-Chip Resistor Array 0402x4 4 resistors in 2.0 mm x 1.0 mm size
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
-
-
-
-Chip Resistor Array 0603x4 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
-
-
-
-Chip Resistor Array 0402x4 4 resistors in 2.0 mm x 1.0 mm size
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
-
-
-
-Chip Resistor Array 0805x4 4 resistors in 5.08 mm x 2.20 mm size
-Source: PANASONIC .. aoc0000ce1.pdf
-
-
-
-
-
-Chip Resistor Array 0603x4 4 resistors in 3.20 mm x 1.60 mm size
-Source: PANASONIC .. aoc0000ce1.pdf
-
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->VALUE
->NAME
-
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-
-<b>Array Chip Resistor</b><p>
-Source: RS Component / Phycomp
-
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-
-
-<b>Resistors, Capacitors, Inductors</b><p>
-Based on the previous libraries:
-<ul>
-<li>r.lbr
-<li>cap.lbr
-<li>cap-fe.lbr
-<li>captant.lbr
-<li>polcap.lbr
-<li>ipc-smd.lbr
-</ul>
-All SMD packages are defined according to the IPC specifications and CECC<p>
-<author>Created by librarian@cadsoft.de</author><p>
-<p>
-for Electrolyt Capacitors see also :<p>
-www.bccomponents.com <p>
-www.panasonic.com<p>
-www.kemet.com<p>
-http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
-<p>
-for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
-
-<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
-<tr valign="top">
-
-<! <td width="10"> </td>
-<td width="90%">
-
-<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
-<P>
-<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
- </B>
- </TD><TD> </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
- 3005P<BR>
- 3006P<BR>
- 3006W<BR>
- 3006Y<BR>
- 3009P<BR>
- 3009W<BR>
- 3009Y<BR>
- 3057J<BR>
- 3057L<BR>
- 3057P<BR>
- 3057Y<BR>
- 3059J<BR>
- 3059L<BR>
- 3059P<BR>
- 3059Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 89P<BR>
- 89W<BR>
- 89X<BR>
- 89PH<BR>
- 76P<BR>
- 89XH<BR>
- 78SLT<BR>
- 78L ALT<BR>
- 56P ALT<BR>
- 78P ALT<BR>
- T8S<BR>
- 78L<BR>
- 56P<BR>
- 78P<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- T18/784<BR>
- 783<BR>
- 781<BR>
- -<BR>
- -<BR>
- -<BR>
- 2199<BR>
- 1697/1897<BR>
- 1680/1880<BR>
- 2187<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 8035EKP/CT20/RJ-20P<BR>
- -<BR>
- RJ-20X<BR>
- -<BR>
- -<BR>
- -<BR>
- 1211L<BR>
- 8012EKQ ALT<BR>
- 8012EKR ALT<BR>
- 1211P<BR>
- 8012EKJ<BR>
- 8012EKL<BR>
- 8012EKQ<BR>
- 8012EKR<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 2101P<BR>
- 2101W<BR>
- 2101Y<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 2102L<BR>
- 2102S<BR>
- 2102Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- EVMCOG<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 43P<BR>
- 43W<BR>
- 43Y<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 40L<BR>
- 40P<BR>
- 40Y<BR>
- 70Y-T602<BR>
- 70L<BR>
- 70P<BR>
- 70Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- RT/RTR12<BR>
- RT/RTR12<BR>
- RT/RTR12<BR>
- -<BR>
- RJ/RJR12<BR>
- RJ/RJR12<BR>
- RJ/RJR12<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3250L<BR>
- 3250P<BR>
- 3250W<BR>
- 3250X<BR>
- 3252P<BR>
- 3252W<BR>
- 3252X<BR>
- 3260P<BR>
- 3260W<BR>
- 3260X<BR>
- 3262P<BR>
- 3262W<BR>
- 3262X<BR>
- 3266P<BR>
- 3266W<BR>
- 3266X<BR>
- 3290H<BR>
- 3290P<BR>
- 3290W<BR>
- 3292P<BR>
- 3292W<BR>
- 3292X<BR>
- 3296P<BR>
- 3296W<BR>
- 3296X<BR>
- 3296Y<BR>
- 3296Z<BR>
- 3299P<BR>
- 3299W<BR>
- 3299X<BR>
- 3299Y<BR>
- 3299Z<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66X ALT<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66X ALT<BR>
- -<BR>
- 64W ALT<BR>
- -<BR>
- 64P ALT<BR>
- 64W ALT<BR>
- 64X ALT<BR>
- 64P<BR>
- 64W<BR>
- 64X<BR>
- 66X ALT<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66P<BR>
- 66W<BR>
- 66X<BR>
- 67P<BR>
- 67W<BR>
- 67X<BR>
- 67Y<BR>
- 67Z<BR>
- 68P<BR>
- 68W<BR>
- 68X<BR>
- 67Y ALT<BR>
- 67Z ALT<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 5050<BR>
- 5091<BR>
- 5080<BR>
- 5087<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- T63YB<BR>
- T63XB<BR>
- -<BR>
- -<BR>
- -<BR>
- 5887<BR>
- 5891<BR>
- 5880<BR>
- -<BR>
- -<BR>
- -<BR>
- T93Z<BR>
- T93YA<BR>
- T93XA<BR>
- T93YB<BR>
- T93XB<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 8026EKP<BR>
- 8026EKW<BR>
- 8026EKM<BR>
- 8026EKP<BR>
- 8026EKB<BR>
- 8026EKM<BR>
- 1309X<BR>
- 1309P<BR>
- 1309W<BR>
- 8024EKP<BR>
- 8024EKW<BR>
- 8024EKN<BR>
- RJ-9P/CT9P<BR>
- RJ-9W<BR>
- RJ-9X<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3103P<BR>
- 3103Y<BR>
- 3103Z<BR>
- 3103P<BR>
- 3103Y<BR>
- 3103Z<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3105P/3106P<BR>
- 3105W/3106W<BR>
- 3105X/3106X<BR>
- 3105Y/3106Y<BR>
- 3105Z/3105Z<BR>
- 3102P<BR>
- 3102W<BR>
- 3102X<BR>
- 3102Y<BR>
- 3102Z<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMCBG<BR>
- EVMCCG<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 55-1-X<BR>
- 55-4-X<BR>
- 55-3-X<BR>
- 55-2-X<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 50-2-X<BR>
- 50-4-X<BR>
- 50-3-X<BR>
- -<BR>
- -<BR>
- -<BR>
- 64P<BR>
- 64W<BR>
- 64X<BR>
- 64Y<BR>
- 64Z<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RJ/RJR22<BR>
- RJ/RJR22<BR>
- RJ/RJR22<BR>
- RT/RTR26<BR>
- RT/RTR26<BR>
- RT/RTR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RT/RTR24<BR>
- RT/RTR24<BR>
- RT/RTR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3323P<BR>
- 3323S<BR>
- 3323W<BR>
- 3329H<BR>
- 3329P<BR>
- 3329W<BR>
- 3339H<BR>
- 3339P<BR>
- 3339W<BR>
- 3352E<BR>
- 3352H<BR>
- 3352K<BR>
- 3352P<BR>
- 3352T<BR>
- 3352V<BR>
- 3352W<BR>
- 3362H<BR>
- 3362M<BR>
- 3362P<BR>
- 3362R<BR>
- 3362S<BR>
- 3362U<BR>
- 3362W<BR>
- 3362X<BR>
- 3386B<BR>
- 3386C<BR>
- 3386F<BR>
- 3386H<BR>
- 3386K<BR>
- 3386M<BR>
- 3386P<BR>
- 3386S<BR>
- 3386W<BR>
- 3386X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 25P<BR>
- 25S<BR>
- 25RX<BR>
- 82P<BR>
- 82M<BR>
- 82PA<BR>
- -<BR>
- -<BR>
- -<BR>
- 91E<BR>
- 91X<BR>
- 91T<BR>
- 91B<BR>
- 91A<BR>
- 91V<BR>
- 91W<BR>
- 25W<BR>
- 25V<BR>
- 25P<BR>
- -<BR>
- 25S<BR>
- 25U<BR>
- 25RX<BR>
- 25X<BR>
- 72XW<BR>
- 72XL<BR>
- 72PM<BR>
- 72RX<BR>
- -<BR>
- 72PX<BR>
- 72P<BR>
- 72RXW<BR>
- 72RXL<BR>
- 72X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- T7YB<BR>
- T7YA<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- TXD<BR>
- TYA<BR>
- TYP<BR>
- -<BR>
- TYD<BR>
- TX<BR>
- -<BR>
- 150SX<BR>
- 100SX<BR>
- 102T<BR>
- 101S<BR>
- 190T<BR>
- 150TX<BR>
- 101<BR>
- -<BR>
- -<BR>
- 101SX<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ET6P<BR>
- ET6S<BR>
- ET6X<BR>
- RJ-6W/8014EMW<BR>
- RJ-6P/8014EMP<BR>
- RJ-6X/8014EMX<BR>
- TM7W<BR>
- TM7P<BR>
- TM7X<BR>
- -<BR>
- 8017SMS<BR>
- -<BR>
- 8017SMB<BR>
- 8017SMA<BR>
- -<BR>
- -<BR>
- CT-6W<BR>
- CT-6H<BR>
- CT-6P<BR>
- CT-6R<BR>
- -<BR>
- CT-6V<BR>
- CT-6X<BR>
- -<BR>
- -<BR>
- 8038EKV<BR>
- -<BR>
- 8038EKX<BR>
- -<BR>
- -<BR>
- 8038EKP<BR>
- 8038EKZ<BR>
- 8038EKW<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- 3321H<BR>
- 3321P<BR>
- 3321N<BR>
- 1102H<BR>
- 1102P<BR>
- 1102T<BR>
- RVA0911V304A<BR>
- -<BR>
- RVA0911H413A<BR>
- RVG0707V100A<BR>
- RVA0607V(H)306A<BR>
- RVA1214H213A<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3104B<BR>
- 3104C<BR>
- 3104F<BR>
- 3104H<BR>
- -<BR>
- 3104M<BR>
- 3104P<BR>
- 3104S<BR>
- 3104W<BR>
- 3104X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- EVMQ0G<BR>
- EVMQIG<BR>
- EVMQ3G<BR>
- EVMS0G<BR>
- EVMQ0G<BR>
- EVMG0G<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMK4GA00B<BR>
- EVM30GA00B<BR>
- EVMK0GA00B<BR>
- EVM38GA00B<BR>
- EVMB6<BR>
- EVLQ0<BR>
- -<BR>
- EVMMSG<BR>
- EVMMBG<BR>
- EVMMAG<BR>
- -<BR>
- -<BR>
- EVMMCS<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMM1<BR>
- -<BR>
- -<BR>
- EVMM0<BR>
- -<BR>
- -<BR>
- EVMM3<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- 62-3-1<BR>
- 62-1-2<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 67R<BR>
- -<BR>
- 67P<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 67X<BR>
- 63V<BR>
- 63S<BR>
- 63M<BR>
- -<BR>
- -<BR>
- 63H<BR>
- 63P<BR>
- -<BR>
- -<BR>
- 63X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- RJ/RJR50<BR>
- RJ/RJR50<BR>
- RJ/RJR50<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
-</TABLE>
-<P> <P>
-<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
- <TR>
- <TD COLSPAN=7>
- <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
- <P>
- <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3224G<BR>
- 3224J<BR>
- 3224W<BR>
- 3269P<BR>
- 3269W<BR>
- 3269X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 44G<BR>
- 44J<BR>
- 44W<BR>
- 84P<BR>
- 84W<BR>
- 84X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- ST63Z<BR>
- ST63Y<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- ST5P<BR>
- ST5W<BR>
- ST5X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=7>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=7>
- <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3314G<BR>
- 3314J<BR>
- 3364A/B<BR>
- 3364C/D<BR>
- 3364W/X<BR>
- 3313G<BR>
- 3313J<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 23B<BR>
- 23A<BR>
- 21X<BR>
- 21W<BR>
- -<BR>
- 22B<BR>
- 22A<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ST5YL/ST53YL<BR>
- ST5YJ/5T53YJ<BR>
- ST-23A<BR>
- ST-22B<BR>
- ST-22<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ST-4B<BR>
- ST-4A<BR>
- -<BR>
- -<BR>
- -<BR>
- ST-3B<BR>
- ST-3A<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- EVM-6YS<BR>
- EVM-1E<BR>
- EVM-1G<BR>
- EVM-1D<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- G4B<BR>
- G4A<BR>
- TR04-3S1<BR>
- TRG04-2S1<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- DVR-43A<BR>
- CVR-42C<BR>
- CVR-42A/C<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
-</TABLE>
-<P>
-<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
-<P>
-
-
-<P>
-</td>
-</tr>
-</table>
-
-
-<b>Chip RESISTOR 0402 EIA (1005 Metric)</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b> wave soldering<p>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b> wave soldering<p>
-Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.10 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.25 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.12 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.10 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.25 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.25 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.12 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.25 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0204, grid 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0204, grid 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0204, grid 2.5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 10 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 12 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 15mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 2.5 mm
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 5 mm
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0309, grid 10mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0309, grid 12.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0309, grid 2.5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0411, grid 12.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0411, grid 15 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0411, grid 3.81 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b><p>
-type 0414, grid 15 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0414, grid 5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b><p>
-type 0617, grid 17.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0617, grid 22.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0617, grid 5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b><p>
-type 0922, grid 22.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0613, grid 5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b><p>
-type 0613, grid 15 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0817, grid 22.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-0817
-
-
-
-
-<b>RESISTOR</b><p>
-type 0817, grid 6.35 mm
-
-
-
-
-
-
->NAME
->VALUE
-0817
-
-
-
-<b>RESISTOR</b><p>
-type V234, grid 12.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type V235, grid 17.78 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type V526-0, grid 2.5 mm
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC2211</b> Reflow Soldering<p>
-source Beyschlag
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC2211</b> Wave Soldering<p>
-source Beyschlag
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC3715</b> Reflow Soldering<p>
-source Beyschlag
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC3715</b> Wave Soldering<p>
-source Beyschlag
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC6123</b> Reflow Soldering<p>
-source Beyschlag
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC6123</b> Wave Soldering<p>
-source Beyschlag
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>RESISTOR</b><p>
-type 0922, grid 7.5 mm
-
-
-
-
-
-
->NAME
->VALUE
-0922
-
-
-
-<b>RESISTOR</b><p>
-type RDH, grid 15 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-RDH
-
-
-
-
-<b>Mini MELF 0102 Axial</b>
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b> chip<p>
-Source: http://www.vishay.com/docs/20008/dcrcw.pdf
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR52<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR53<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR54<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR55<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR56<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RNC55<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RNC60<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Package 4527</b><p>
-Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
-Source: http://www.vishay.com .. dcrcw.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
-Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>PRL1632 are realized as 1W for 3.2 × 1.6mm(1206)</b><p>
-Source: http://www.mouser.com/ds/2/392/products_18-2245.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b><p>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 2.4 x 4.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 2.5 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 3 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 4 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 5 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 6 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 2.4 x 4.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 2.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 4.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 3 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 5.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 7.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>CAPACITOR</b><p>
-grid 7.5 mm, outline 3.2 x 10.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 7.5 mm, outline 4.2 x 10.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 7.5 mm, outline 5.2 x 10.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 10.2 mm, outline 4.3 x 13.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 10.2 mm, outline 5.4 x 13.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 10.2 mm, outline 6.4 x 13.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 5.4 x 18.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 6.4 x 18.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 7.2 x 18.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 8.4 x 18.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 9.1 x 18.2 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 6.2 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 7.4 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 8.7 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 10.8 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 11.3 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 9.3 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 11.3 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 13.4 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 20.5 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 32.5 mm, outline 13.7 x 37.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 32.5 mm, outline 16.2 x 37.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 32.5 mm, outline 18.2 x 37.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 37.5 mm, outline 19.2 x 41.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 37.5 mm, outline 20.3 x 41.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 3.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 37.5 mm, outline 15.5 x 41.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 7.5 mm, outline 6.3 x 10.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 15.4 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 17.3 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
-Metric Code Size 1005
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
-Metric Code Size 1608
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
-Metric Code Size 2012
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
-Metric Code Size 3216
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
-Metric Code Size 3225
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
-Metric Code Size 4532
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
-Metric Code Size 4564
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b> </b><p>
-Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
-
-
->NAME
->VALUE
-
-
-
-Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>CAPACITOR</b><p>
-Source: AVX .. aphvc.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>CAPACITOR</b><p>
-Source: AVX .. aphvc.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-Chip RESISTOR 0402 EIA (1005 Metric)
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR wave soldering
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-wave soldering
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-wave soldering
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-wave soldering
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-wave soldering
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-wave soldering
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-wave soldering
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-wave soldering
-
-
-
-
-
-RESISTOR
-
-
-
-
-
-RESISTOR
-wave soldering
-
-
-
-
-
-RESISTOR
-Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
-
-
-
-
-
-RESISTOR wave soldering
-Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
-
-
-
-
-
-RESISTOR
-MELF 0.10 W
-
-
-
-
-
-RESISTOR
-MELF 0.25 W
-
-
-
-
-
-RESISTOR
-MELF 0.12 W
-
-
-
-
-
-RESISTOR
-MELF 0.10 W
-
-
-
-
-
-RESISTOR
-MELF 0.25 W
-
-
-
-
-
-RESISTOR
-MELF 0.25 W
-
-
-
-
-
-RESISTOR
-MELF 0.12 W
-
-
-
-
-
-RESISTOR
-MELF 0.25 W
-
-
-
-
-
-RESISTOR
-type 0204, grid 5 mm
-
-
-
-
-
-RESISTOR
-type 0204, grid 7.5 mm
-
-
-
-
-
-RESISTOR
-type 0204, grid 2.5 mm
-
-
-
-
-
-RESISTOR
-type 0207, grid 10 mm
-
-
-
-
-
-RESISTOR
-type 0207, grid 12 mm
-
-
-
-
-
-RESISTOR
-type 0207, grid 15mm
-
-
-
-
-
-RESISTOR
-type 0207, grid 2.5 mm
-
-
-
-
-
-RESISTOR
-type 0207, grid 5 mm
-
-
-
-
-
-RESISTOR
-type 0207, grid 7.5 mm
-
-
-
-
-
-RESISTOR
-type 0309, grid 10mm
-
-
-
-
-
-RESISTOR
-type 0309, grid 12.5 mm
-
-
-
-
-
-RESISTOR
-type 0309, grid 2.5 mm
-
-
-
-
-
-RESISTOR
-type 0411, grid 12.5 mm
-
-
-
-
-
-RESISTOR
-type 0411, grid 15 mm
-
-
-
-
-
-RESISTOR
-type 0411, grid 3.81 mm
-
-
-
-
-
-RESISTOR
-type 0414, grid 15 mm
-
-
-
-
-
-RESISTOR
-type 0414, grid 5 mm
-
-
-
-
-
-RESISTOR
-type 0617, grid 17.5 mm
-
-
-
-
-
-RESISTOR
-type 0617, grid 22.5 mm
-
-
-
-
-
-RESISTOR
-type 0617, grid 5 mm
-
-
-
-
-
-RESISTOR
-type 0922, grid 22.5 mm
-
-
-
-
-
-RESISTOR
-type 0613, grid 5 mm
-
-
-
-
-
-RESISTOR
-type 0613, grid 15 mm
-
-
-
-
-
-RESISTOR
-type 0817, grid 22.5 mm
-
-
-
-
-
-RESISTOR
-type 0817, grid 6.35 mm
-
-
-
-
-
-RESISTOR
-type V234, grid 12.5 mm
-
-
-
-
-
-RESISTOR
-type V235, grid 17.78 mm
-
-
-
-
-
-RESISTOR
-type V526-0, grid 2.5 mm
-
-
-
-
-
-CECC Size RC2211 Reflow Soldering
-source Beyschlag
-
-
-
-
-
-CECC Size RC2211 Wave Soldering
-source Beyschlag
-
-
-
-
-
-CECC Size RC3715 Reflow Soldering
-source Beyschlag
-
-
-
-
-
-CECC Size RC3715 Wave Soldering
-source Beyschlag
-
-
-
-
-
-CECC Size RC6123 Reflow Soldering
-source Beyschlag
-
-
-
-
-
-CECC Size RC6123 Wave Soldering
-source Beyschlag
-
-
-
-
-
-RESISTOR
-type 0922, grid 7.5 mm
-
-
-
-
-
-RESISTOR
-type RDH, grid 15 mm
-
-
-
-
-
-Mini MELF 0102 Axial
-
-
-
-
-
-RESISTOR chip
-Source: http://www.vishay.com/docs/20008/dcrcw.pdf
-
-
-
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR52
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR53
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR54
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR55
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR56
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RNC55
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RNC60
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-Package 4527
-Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
-
-
-
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-CRCW1218 Thick Film, Rectangular Chip Resistors
-Source: http://www.vishay.com .. dcrcw.pdf
-
-
-
-
-
-Chip Monolithic Ceramic Capacitors Medium Voltage High Capacitance for General Use
-Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
-
-
-
-
-
-PRL1632 are realized as 1W for 3.2 × 1.6mm(1206)
-Source: http://www.mouser.com/ds/2/392/products_18-2245.pdf
-
-
-
-
-
-Chip, 0.40 X 0.20 X 0.16 mm body
-<p>Chip package with body size 0.40 X 0.20 X 0.16 mm</p>
-
-
-
-
-
-Chip, 1.00 X 0.50 X 0.60 mm body
-<p>Chip package with body size 1.00 X 0.50 X 0.60 mm</p>
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-CAPACITOR
-grid 2.5 mm, outline 2.4 x 4.4 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 mm, outline 2.5 x 5 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 mm, outline 3 x 5 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 mm, outline 4 x 5 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 mm, outline 5 x 5 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 mm, outline 6 x 5 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 5 mm, outline 2.4 x 4.4 mm
-
-
-
-
-
-CAPACITOR
-grid 5 mm, outline 2.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 5 mm, outline 4.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 5 mm, outline 3 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 5 mm, outline 5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 5 mm, outline 5.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 5 mm, outline 7.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 7.5 mm, outline 3.2 x 10.3 mm
-
-
-
-
-
-CAPACITOR
-grid 7.5 mm, outline 4.2 x 10.3 mm
-
-
-
-
-
-CAPACITOR
-grid 7.5 mm, outline 5.2 x 10.6 mm
-
-
-
-
-
-CAPACITOR
-grid 10.2 mm, outline 4.3 x 13.3 mm
-
-
-
-
-
-CAPACITOR
-grid 10.2 mm, outline 5.4 x 13.3 mm
-
-
-
-
-
-CAPACITOR
-grid 10.2 mm, outline 6.4 x 13.3 mm
-
-
-
-
-
-CAPACITOR
-grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
-
-
-
-
-
-CAPACITOR
-grid 15 mm, outline 5.4 x 18.3 mm
-
-
-
-
-
-CAPACITOR
-grid 15 mm, outline 6.4 x 18.3 mm
-
-
-
-
-
-CAPACITOR
-grid 15 mm, outline 7.2 x 18.3 mm
-
-
-
-
-
-CAPACITOR
-grid 15 mm, outline 8.4 x 18.3 mm
-
-
-
-
-
-CAPACITOR
-grid 15 mm, outline 9.1 x 18.2 mm
-
-
-
-
-
-CAPACITOR
-grid 22.5 mm, outline 6.2 x 26.8 mm
-
-
-
-
-
-CAPACITOR
-grid 22.5 mm, outline 7.4 x 26.8 mm
-
-
-
-
-
-CAPACITOR
-grid 22.5 mm, outline 8.7 x 26.8 mm
-
-
-
-
-
-CAPACITOR
-grid 22.5 mm, outline 10.8 x 26.8 mm
-
-
-
-
-
-CAPACITOR
-grid 22.5 mm, outline 11.3 x 26.8 mm
-
-
-
-
-
-CAPACITOR
-grid 27.5 mm, outline 9.3 x 31.6 mm
-
-
-
-
-
-CAPACITOR
-grid 27.5 mm, outline 11.3 x 31.6 mm
-
-
-
-
-
-CAPACITOR
-grid 27.5 mm, outline 13.4 x 31.6 mm
-
-
-
-
-
-CAPACITOR
-grid 27.5 mm, outline 20.5 x 31.6 mm
-
-
-
-
-
-CAPACITOR
-grid 32.5 mm, outline 13.7 x 37.4 mm
-
-
-
-
-
-CAPACITOR
-grid 32.5 mm, outline 16.2 x 37.4 mm
-
-
-
-
-
-CAPACITOR
-grid 32.5 mm, outline 18.2 x 37.4 mm
-
-
-
-
-
-CAPACITOR
-grid 37.5 mm, outline 19.2 x 41.8 mm
-
-
-
-
-
-CAPACITOR
-grid 37.5 mm, outline 20.3 x 41.8 mm
-
-
-
-
-
-CAPACITOR
-grid 5 mm, outline 3.5 x 7.5 mm
-
-
-
-
-
-CAPACITOR
-grid 37.5 mm, outline 15.5 x 41.8 mm
-
-
-
-
-
-CAPACITOR
-grid 7.5 mm, outline 6.3 x 10.6 mm
-
-
-
-
-
-CAPACITOR
-grid 27.5 mm, outline 15.4 x 31.6 mm
-
-
-
-
-
-CAPACITOR
-grid 27.5 mm, outline 17.3 x 31.6 mm
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 0204 reflow solder
-Metric Code Size 1005
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 0603 reflow solder
-Metric Code Size 1608
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 0805 reflow solder
-Metric Code Size 2012
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 1206 reflow solder
-Metric Code Size 3216
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 1210 reflow solder
-Metric Code Size 3225
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 1812 reflow solder
-Metric Code Size 4532
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 1825 reflow solder
-Metric Code Size 4564
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 2220 reflow solderMetric Code Size 5650
-
-
-
-
-
-Ceramic Chip Capacitor KEMET 2225 reflow solderMetric Code Size 5664
-
-
-
-
-
-
-Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
-
-
-
-
-
-Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
-
-
-
-
-
-CAPACITOR
-Source: AVX .. aphvc.pdf
-
-
-
-
-
-CAPACITOR
-Source: AVX .. aphvc.pdf
-
-
-
-
-
-CAPACITOR
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-<B>RESISTOR</B>, European symbol
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
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-<b>TTL Devices, 74xx Series with European Symbols</b><p>
-Based on the following sources:
-<ul>
-<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
-<li>TTL Data Book, Volume 2 , 1993
-<li>National Seminconductor Databook 1990, ALS/LS Logic
-<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
-<li>http://icmaster.com/ViewCompare.asp
-</ul>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>Dual In Line Package</b>
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->NAME
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-<b>Small Outline package</b> 150 mil
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-<b>plastic shrink small outline package; 14 leads; body width 5.3 mm</b><p>
-SOT337-1<br>
-Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf
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-<b>plastic thin shrink small outline package; 14 leads; body width 4.4 mm</b><p>
-SOT402-1<br>
-Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf
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-<b>plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm</b><p>
-Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf
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->NAME
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-Dual In Line Package
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-Small Outline package 150 mil
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-plastic shrink small outline package; 14 leads; body width 5.3 mm
-SOT337-1
-Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf
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-plastic thin shrink small outline package; 14 leads; body width 4.4 mm
-SOT402-1
-Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf
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-plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm
-Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf
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-
-
-<b>Crystals and Crystal Resonators</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>kHz RANGE CRYSTAL UNIT</b><p>
-LOW PROFILE SMD<b>
-Source: Epson Toyocom FC-12M.pdf
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-kHz RANGE CRYSTAL UNIT
-LOW PROFILE SMD
-Source: Epson Toyocom FC-12M.pdf
-
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->NAME
->VALUE
-1
-2
-
-
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-
-
-<b>kHz RANGE CRYSTAL UNIT</b><p>
-LOW PROFILE SMD<b>
-Source: Epson Toyocom FC-12M.pdf
-
-
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-<b>Lithium Batteries and NC Accus</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>Battery Holder, SMT, 12mm</b><p>
-multicomp PART NO. CH291-1220LF<br>
-Source: <a href="http://www.farnell.com/datasheets/1505860.pdf"> Data sheet </a>
-
-
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->NAME
->VALUE
-
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-
-
-Battery Holder, SMT, 12mm
-multicomp PART NO. CH291-1220LF
-Source: Data sheet
-
-
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->NAME
->VALUE
-
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-
-
-<b>Battery Holder, SMT, 12mm</b><p>
-multicomp PART NO. CH291-1220LF<br>
-Source: <a href="http://www.farnell.com/datasheets/1505860.pdf"> Data sheet </a>
-
-
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-
-<b>Diodes</b><p>
-Based on the following sources:
-<ul>
-<li>Motorola : www.onsemi.com
-<li>Fairchild : www.fairchildsemi.com
-<li>Philips : www.semiconductors.com
-<li>Vishay : www.vishay.de
-</ul>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>SOD-323</b><p>
-Source: www.st.com, BAT60J.pdf
-
-
-
-
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-
->NAME
->VALUE
-
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-
-SOD-323
-Source: www.st.com, BAT60J.pdf
-
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->NAME
->VALUE
-
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-
-
-<b>Schottky barrier diode</b><p>
-Source: www.st.com, BAT60J.pdf
-
-
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-<b>Samtec Connectors</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p>
-Source: Samtec SSW.pdf
-
-
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-1
-2
->NAME
->VALUE
-
-
-<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p>
-Source: Samtec SSW.pdf
-
-
-
-
-
-
-
-
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-
-
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-
-1
-2
->NAME
->VALUE
-
-
-
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-
-
-
-
-<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p>
-Source: Samtec SSW.pdf
-
-
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-1
-2
->NAME
->VALUE
-
-
-<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p>
-Source: Samtec SSW.pdf
-
-
-
-
-
-
-
-
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-
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-1
-2
->NAME
->VALUE
-
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->VALUE
->NAME
-
-
-
-
-
-
->NAME
-
-
-
-
-
-<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p>
-Source: Samtec SSW.pdf
-
-
-
-
-
-
-
-
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-
-
-<b>LEDs</b><p>
-<author>Created by librarian@cadsoft.de</author><br>
-Extended by Federico Battaglin <author><federico.rd@fdpinternational.com></author> with DUOLED
-
-
-<b>CHICAGO MINIATURE LAMP, INC.</b><p>
-7022X Series SMT LEDs 1206 Package Size
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-<B>LED</B><p>
-5 mm, square, Siemens
-
-
-
-
-
-
-
-
-
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-
-
-
-
-
-
-
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-
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->NAME
->VALUE
-
-
-
-
-<B>LED</B><p>
-2 x 5 mm, rectangle
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
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->NAME
->VALUE
-
-
-
-<B>LED</B><p>
-3 mm, round
-
-
-
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-
-
-
-
-
-
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-
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->NAME
->VALUE
-
-
-<B>LED</B><p>
-5 mm, round
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<B>LED</B><p>
-1 mm, round, Siemens
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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->NAME
->VALUE
-
-
-
-
-<B>LED BLOCK</B><p>
-1 LED, Siemens
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>LED HOLDER</b><p>
-Siemens
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
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-
-
->NAME
->VALUE
-
-
-<b>LED HOLDER</b><p>
-Siemens
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>LED HOLDER</b><p>
-Siemens
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-A+
-K-
->NAME
->VALUE
-
-
-
-
-
-<b>LED HOLDER</b><p>
-Siemens
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-+
--
-
-
-<B>IR LED</B><p>
-infrared emitting diode, Infineon
-TO-18, lead spacing 2.54 mm, cathode marking<p>
-Inifineon
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<B>IR LED</B><p>
-infrared emitting diode, Infineon
-TO-18, lead spacing 2.54 mm, cathode marking<p>
-Inifineon
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<B>LED</B><p>
-rectangle, 5.7 x 3.2 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<B>IR LED</B><p>
-IR transmitter Siemens
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>TOPLED® High-optical Power LED (HOP)</b><p>
-Source: http://www.osram.convergy.de/ ... ls_t675.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-A
-C
-
-
-
-
-
-
-
-<b>BLUE LINETM Hyper Mini TOPLED® Hyper-Bright LED</b><p>
-Source: http://www.osram.convergy.de/ ... LB M676.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-A
-C
->NAME
->VALUE
-
-
-
-
-
-
-
-<b>Super SIDELED® High-Current LED</b><p>
-LG A672, LP A672 <br>
-Source: http://www.osram.convergy.de/ ... LG_LP_A672.pdf (2004.05.13)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-C
-A
->NAME
->VALUE
-
-
-
-
-
-
-
-<b>SmartLEDTM Hyper-Bright LED</b><p>
-Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY L896.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>Hyper TOPLED® RG Hyper-Bright LED</b><p>
-Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY T776.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-A
-C
-
-
-
-
-
-
-
-
-
-
-<b>Hyper Micro SIDELED®</b><p>
-Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY Y876.pdf
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-<b>Power TOPLED®</b><p>
-Source: http://www.osram.convergy.de/ ... LA_LO_LA_LY E67B.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-C
-A
-C
-C
-
-
-
-
-
-
-
-
-
-
-
-<b>Hyper CHIPLED Hyper-Bright LED</b><p>
-LB Q993<br>
-Source: http://www.osram.convergy.de/ ... Lb_q993.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-<b>Hyper CHIPLED Hyper-Bright LED</b><p>
-LB R99A<br>
-Source: http://www.osram.convergy.de/ ... lb_r99a.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-<b>Mini TOPLED Santana®</b><p>
-Source: http://www.osram.convergy.de/ ... LG M470.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-<b>CHIPLED</b><p>
-Source: http://www.osram.convergy.de/ ... LG_R971.pdf
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>CHIPLED</b><p>
-Source: http://www.osram.convergy.de/ ... LG_LY N971.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>CHIPLED</b><p>
-Source: http://www.osram.convergy.de/ ... LG_LY Q971.pdf
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>CHIPLED-0603</b><p>
-Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603<br>
-Package able to withstand TTW-soldering heat<br>
-Package suitable for TTW-soldering<br>
-Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>SmartLED TTW</b><p>
-Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603<br>
-Package able to withstand TTW-soldering heat<br>
-Package suitable for TTW-soldering<br>
-Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-<b>Lumileds Lighting. LUXEON®</b> with cool pad<p>
-Source: K2.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>Lumileds Lighting. LUXEON®</b> without cool pad<p>
-Source: K2.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<B>LED</B><p>
-10 mm, round
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>SURFACE MOUNT LED LAMP</b> 3.5x2.8mm<p>
-Source: http://www.kingbright.com/manager/upload/pdf/KA-3528ASYC(Ver1189474662.1)
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>SML0805-2CW-TR (0805 PROFILE)</b> COOL WHITE<p>
-Source: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>SML10XXKH-TR (HIGH INTENSITY) LED</b><p>
-<table>
-<tr><td>SML10R3KH-TR</td><td>ULTRA RED</td></tr>
-<tr><td>SML10E3KH-TR</td><td>SUPER REDSUPER BLUE</td></tr>
-<tr><td>SML10O3KH-TR</td><td>SUPER ORANGE</td></tr>
-<tr><td>SML10PY3KH-TR</td><td>PURE YELLOW</td></tr>
-<tr><td>SML10OY3KH-TR</td><td>ULTRA YELLOW</td></tr>
-<tr><td>SML10AG3KH-TR</td><td>AQUA GREEN</td></tr>
-<tr><td>SML10BG3KH-TR</td><td>BLUE GREEN</td></tr>
-<tr><td>SML10PB1KH-TR</td><td>SUPER BLUE</td></tr>
-<tr><td>SML10CW1KH-TR</td><td>WHITE</td></tr>
-</table>
-
-Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-<b>SML0603-XXX (HIGH INTENSITY) LED</b><p>
-<table>
-<tr><td>AG3K</td><td>AQUA GREEN</td></tr>
-<tr><td>B1K</td><td>SUPER BLUE</td></tr>
-<tr><td>R1K</td><td>SUPER RED</td></tr>
-<tr><td>R3K</td><td>ULTRA RED</td></tr>
-<tr><td>O3K</td><td>SUPER ORANGE</td></tr>
-<tr><td>O3KH</td><td>SOFT ORANGE</td></tr>
-<tr><td>Y3KH</td><td>SUPER YELLOW</td></tr>
-<tr><td>Y3K</td><td>SUPER YELLOW</td></tr>
-<tr><td>2CW</td><td>WHITE</td></tr>
-</table>
-Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-CHICAGO MINIATURE LAMP, INC.
-7022X Series SMT LEDs 1206 Package Size
-
-
-
-
-
-LED
-5 mm, square, Siemens
-
-
-
-
-
-LED
-2 x 5 mm, rectangle
-
-
-
-
-
-LED
-3 mm, round
-
-
-
-
-
-LED
-5 mm, round
-
-
-
-
-
-LED
-1 mm, round, Siemens
-
-
-
-
-
-LED BLOCK
-1 LED, Siemens
-
-
-
-
-
-LED HOLDER
-Siemens
-
-
-
-
-
-LED HOLDER
-Siemens
-
-
-
-
-
-LED HOLDER
-Siemens
-
-
-
-
-
-LED HOLDER
-Siemens
-
-
-
-
-
-IR LED
-infrared emitting diode, Infineon
-TO-18, lead spacing 2.54 mm, cathode marking
-Inifineon
-
-
-
-
-
-IR LED
-infrared emitting diode, Infineon
-TO-18, lead spacing 2.54 mm, cathode marking
-Inifineon
-
-
-
-
-
-LED
-rectangle, 5.7 x 3.2 mm
-
-
-
-
-
-IR LED
-IR transmitter Siemens
-
-
-
-
-
-TOPLED® High-optical Power LED (HOP)
-Source: http://www.osram.convergy.de/ ... ls_t675.pdf
-
-
-
-
-
-BLUE LINETM Hyper Mini TOPLED® Hyper-Bright LED
-Source: http://www.osram.convergy.de/ ... LB M676.pdf
-
-
-
-
-
-Super SIDELED® High-Current LED
-LG A672, LP A672
-Source: http://www.osram.convergy.de/ ... LG_LP_A672.pdf (2004.05.13)
-
-
-
-
-
-SmartLEDTM Hyper-Bright LED
-Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY L896.pdf
-
-
-
-
-
-Hyper TOPLED® RG Hyper-Bright LED
-Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY T776.pdf
-
-
-
-
-
-Hyper Micro SIDELED®
-Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY Y876.pdf
-
-
-
-
-
-Power TOPLED®
-Source: http://www.osram.convergy.de/ ... LA_LO_LA_LY E67B.pdf
-
-
-
-
-
-Hyper CHIPLED Hyper-Bright LED
-LB Q993
-Source: http://www.osram.convergy.de/ ... Lb_q993.pdf
-
-
-
-
-
-Hyper CHIPLED Hyper-Bright LED
-LB R99A
-Source: http://www.osram.convergy.de/ ... lb_r99a.pdf
-
-
-
-
-
-Mini TOPLED Santana®
-Source: http://www.osram.convergy.de/ ... LG M470.pdf
-
-
-
-
-
-CHIPLED
-Source: http://www.osram.convergy.de/ ... LG_R971.pdf
-
-
-
-
-
-CHIPLED
-Source: http://www.osram.convergy.de/ ... LG_LY N971.pdf
-
-
-
-
-
-CHIPLED
-Source: http://www.osram.convergy.de/ ... LG_LY Q971.pdf
-
-
-
-
-
-CHIPLED-0603
-Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603
-Package able to withstand TTW-soldering heat
-Package suitable for TTW-soldering
-Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf
-
-
-
-
-
-SmartLED TTW
-Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603
-Package able to withstand TTW-soldering heat
-Package suitable for TTW-soldering
-Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf
-
-
-
-
-
-Lumileds Lighting. LUXEON® with cool pad
-Source: K2.pdf
-
-
-
-
-
-Lumileds Lighting. LUXEON® without cool pad
-Source: K2.pdf
-
-
-
-
-
-LED
-10 mm, round
-
-
-
-
-
-SURFACE MOUNT LED LAMP 3.5x2.8mm
-Source: http://www.kingbright.com/manager/upload/pdf/KA-3528ASYC(Ver1189474662.1)
-
-
-
-
-
-SML0805-2CW-TR (0805 PROFILE) COOL WHITE
-Source: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf
-
-
-
-
-
-SML10XXKH-TR (HIGH INTENSITY) LED
-
-SML10R3KH-TRULTRA RED
-SML10E3KH-TRSUPER REDSUPER BLUE
-SML10O3KH-TRSUPER ORANGE
-SML10PY3KH-TRPURE YELLOW
-SML10OY3KH-TRULTRA YELLOW
-SML10AG3KH-TRAQUA GREEN
-SML10BG3KH-TRBLUE GREEN
-SML10PB1KH-TRSUPER BLUE
-SML10CW1KH-TRWHITE
-
-
-Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF
-
-
-
-
-
-SML0603-XXX (HIGH INTENSITY) LED
-
-AG3KAQUA GREEN
-B1KSUPER BLUE
-R1KSUPER RED
-R3KULTRA RED
-O3KSUPER ORANGE
-O3KHSOFT ORANGE
-Y3KHSUPER YELLOW
-Y3KSUPER YELLOW
-2CWWHITE
-
-Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>LED</b><p>
-<u>OSRAM</u>:<br>
-
-- <u>CHIPLED</u><br>
-LG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971
-LH N974, LH R974<br>
-LS Q976, LO Q976, LY Q976<br>
-LO Q996<br>
-
-- <u>Hyper CHIPLED</u><br>
-LW Q18S<br>
-LB Q993, LB Q99A, LB R99A<br>
-
-- <u>SideLED</u><br>
-LS A670, LO A670, LY A670, LG A670, LP A670<br>
-LB A673, LV A673, LT A673, LW A673<br>
-LH A674<br>
-LY A675<br>
-LS A676, LA A676, LO A676, LY A676, LW A676<br>
-LS A679, LY A679, LG A679<br>
-
-- <u>Hyper Micro SIDELED®</u><br>
-LS Y876, LA Y876, LO Y876, LY Y876<br>
-LT Y87S<br>
-
-- <u>SmartLED</u><br>
-LW L88C, LW L88S<br>
-LB L89C, LB L89S, LG L890<br>
-LS L89K, LO L89K, LY L89K<br>
-LS L896, LA L896, LO L896, LY L896<br>
-
-- <u>TOPLED</u><br>
-LS T670, LO T670, LY T670, LG T670, LP T670<br>
-LSG T670, LSP T670, LSY T670, LOP T670, LYG T670<br>
-LG T671, LOG T671, LSG T671<br>
-LB T673, LV T673, LT T673, LW T673<br>
-LH T674<br>
-LS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676<br>
-LB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C<br>
-LS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C<br>
-LW T67C<br>
-LS T679, LY T679, LG T679<br>
-LS T770, LO T770, LY T770, LG T770, LP T770<br>
-LB T773, LV T773, LT T773, LW T773<br>
-LH T774<br>
-LS E675, LA E675, LY E675, LS T675<br>
-LS T776, LA T776, LO T776, LY T776, LB T776<br>
-LHGB T686<br>
-LT T68C, LB T68C<br>
-
-- <u>Hyper Mini TOPLED®</u><br>
-LB M676<br>
-
-- <u>Mini TOPLED Santana®</u><br>
-LG M470<br>
-LS M47K, LO M47K, LY M47K
-<p>
-Source: http://www.osram.convergy.de<p>
-
-<u>LUXEON:</u><br>
-- <u>LUMILED®</u><br>
-LXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00<br>
-LXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00<br>
-LXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00<br>
-LXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00<br>
-LXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00<br>
-LXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00<br>
-LXK2-PH12-R00, LXK2-PH12-S00<br>
-LXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00
-<p>
-Source: www.luxeon.com<p>
-
-<u>KINGBRIGHT:</U><p>
-KA-3528ASYC<br>
-Source: www.kingbright.com
-
-
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-
-
-<b>Voltage Regulators</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-<b>DPAK</b><p>
-PLASTIC PACKAGE CASE 369C-01<br>
-Source: http://www.onsemi.co.jp .. LM317M-D.PDF
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
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-
-
-
-
-<b>VOLTAGE REGULATOR</b>
-
-
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-
->NAME
->VALUE
-A15,2mm
-1
-2
-3
-
-
-
-
-
-
-
-
-
-<b>Small Outline Transistor 223</b><p>
-PLASTIC PACKAGE CASE 318E-04<br>
-Source: http://www.onsemi.co.jp .. LM137M-D.PDF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-direction of pcb
-transportation for
-wavesoldering
-
-
-
-
-
-
-
-
-
-
-<b>D2PACK</b><p>
-INTERNATIONAL RECTIFIER, irg4bc15ud-s.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-
-
-
-DPAK
-PLASTIC PACKAGE CASE 369C-01
-Source: http://www.onsemi.co.jp .. LM317M-D.PDF
-
-
-
-
-
-VOLTAGE REGULATOR
-
-
-
-
-
-Small Outline Transistor 223
-PLASTIC PACKAGE CASE 318E-04
-Source: http://www.onsemi.co.jp .. LM137M-D.PDF
-
-
-
-
-
-D2PACK
-INTERNATIONAL RECTIFIER, irg4bc15ud-s.pdf
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-ADJ
-IN
-OUT
-
-
-
-
-
-
-
-<b>Low drop fixed and adjustable positive voltage regulators</b> 1 A<p>
-Source: http://www.st.com/stonline/products/literature/ds/7194/ld1117axx.pdf
-
-
-
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-RTC
-LED
-CIC
-
-
-
-
-PMOD
-
-
-
-
-
-
-
-
-FLASH
-SRAM
-
-
-
-
-FTDI EEPROM
-
-
-
-
-N64 <-> FPGA Resistors
-
-
-
-
-N64 Edge Connector
-
-
-
-
-Crystal Oscillators
-
-
-
-
-SDRAM
-
-
-
-
-FTDI <-> CIC Buffer
-
-
-
-
-FPGA
-
-
-
-
-Pull-up Resistors
-
-
-
-
-SD Card
-
-
-
-
-FTDI
-
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-
-Since Version 8.2, EAGLE supports online libraries. The ids
-of those online libraries will not be understood (or retained)
-with this version.
-
-
-Since Version 8.3, EAGLE supports URNs for individual library
-assets (packages, symbols, and devices). The URNs of those assets
-will not be understood (or retained) with this version.
-
-
-Since Version 8.3, EAGLE supports the association of 3D packages
-with devices in libraries, schematics, and board files. Those 3D
-packages will not be understood (or retained) with this version.
-
-
-Since Version 8.4, EAGLE supports properties for SPICE simulation.
-Probes in schematics and SPICE mapping objects found in parts and library devices
-will not be understood with this version. Update EAGLE to the latest version
-for full support of SPICE simulation.
-
-
-
diff --git a/hw/pcb/.gitignore b/hw/pcb/.gitignore
new file mode 100644
index 0000000..b24f878
--- /dev/null
+++ b/hw/pcb/.gitignore
@@ -0,0 +1,6 @@
+**/*-backups
+**/*-bak
+**/*.gerbers
+**/*.kicad_prl
+**/*.zip
+**/fp-info-cache
diff --git a/hw/pcb/sc64v2.kicad_pcb b/hw/pcb/sc64v2.kicad_pcb
new file mode 100644
index 0000000..5a97cae
--- /dev/null
+++ b/hw/pcb/sc64v2.kicad_pcb
@@ -0,0 +1,62349 @@
+(kicad_pcb (version 20211014) (generator pcbnew)
+
+ (general
+ (thickness 1.2)
+ )
+
+ (paper "A4")
+ (title_block
+ (title "SummerCart64")
+ (date "2022-05-15")
+ (rev "2.0")
+ (company "Polprzewodnikowy")
+ )
+
+ (layers
+ (0 "F.Cu" signal)
+ (31 "B.Cu" signal)
+ (32 "B.Adhes" user "B.Adhesive")
+ (33 "F.Adhes" user "F.Adhesive")
+ (34 "B.Paste" user)
+ (35 "F.Paste" user)
+ (36 "B.SilkS" user "B.Silkscreen")
+ (37 "F.SilkS" user "F.Silkscreen")
+ (38 "B.Mask" user)
+ (39 "F.Mask" user)
+ (40 "Dwgs.User" user "User.Drawings")
+ (41 "Cmts.User" user "User.Comments")
+ (42 "Eco1.User" user "User.Eco1")
+ (43 "Eco2.User" user "User.Eco2")
+ (44 "Edge.Cuts" user)
+ (45 "Margin" user)
+ (46 "B.CrtYd" user "B.Courtyard")
+ (47 "F.CrtYd" user "F.Courtyard")
+ (48 "B.Fab" user)
+ (49 "F.Fab" user)
+ (50 "User.1" user)
+ (51 "User.2" user)
+ (52 "User.3" user)
+ (53 "User.4" user)
+ (54 "User.5" user)
+ (55 "User.6" user)
+ (56 "User.7" user)
+ (57 "User.8" user)
+ (58 "User.9" user)
+ )
+
+ (setup
+ (stackup
+ (layer "F.SilkS" (type "Top Silk Screen") (color "White"))
+ (layer "F.Paste" (type "Top Solder Paste"))
+ (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
+ (layer "F.Cu" (type "copper") (thickness 0.035))
+ (layer "dielectric 1" (type "core") (thickness 1.11) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+ (layer "B.Cu" (type "copper") (thickness 0.035))
+ (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
+ (layer "B.Paste" (type "Bottom Solder Paste"))
+ (layer "B.SilkS" (type "Bottom Silk Screen") (color "White"))
+ (copper_finish "ENIG")
+ (dielectric_constraints no)
+ (edge_connector bevelled)
+ )
+ (pad_to_mask_clearance 0)
+ (pcbplotparams
+ (layerselection 0x00010fc_ffffffff)
+ (disableapertmacros false)
+ (usegerberextensions true)
+ (usegerberattributes false)
+ (usegerberadvancedattributes false)
+ (creategerberjobfile false)
+ (svguseinch false)
+ (svgprecision 6)
+ (excludeedgelayer true)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15.000000)
+ (dxfpolygonmode true)
+ (dxfimperialunits true)
+ (dxfusepcbnewfont true)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue false)
+ (plotinvisibletext false)
+ (sketchpadsonfab false)
+ (subtractmaskfromsilk true)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 0)
+ (scaleselection 1)
+ (outputdirectory "sc64v2.gerbers/")
+ )
+ )
+
+ (net 0 "")
+ (net 1 "unconnected-(X1-Pad1)")
+ (net 2 "unconnected-(X2-Pad1)")
+ (net 3 "unconnected-(J_N1-Pad39)")
+ (net 4 "unconnected-(J_N1-Pad38)")
+ (net 5 "unconnected-(J_N1-Pad14)")
+ (net 6 "unconnected-(J_N1-Pad13)")
+ (net 7 "N64_AD15")
+ (net 8 "N64_AD14")
+ (net 9 "N64_AD13")
+ (net 10 "N64_AD12")
+ (net 11 "N64_AD11")
+ (net 12 "N64_AD10")
+ (net 13 "N64_AD9")
+ (net 14 "N64_AD8")
+ (net 15 "N64_CIC_DATA")
+ (net 16 "N64_PIF_CLK")
+ (net 17 "N64_JOYBUS")
+ (net 18 "N64_AD0")
+ (net 19 "N64_AD1")
+ (net 20 "N64_AD2")
+ (net 21 "N64_AD3")
+ (net 22 "N64_ALEL")
+ (net 23 "N64_ALEH")
+ (net 24 "N64_AD4")
+ (net 25 "N64_AD5")
+ (net 26 "N64_AD6")
+ (net 27 "N64_AD7")
+ (net 28 "N64_CIC_CLK")
+ (net 29 "N64_VIDEO_SYNC")
+ (net 30 "SD_DAT2")
+ (net 31 "SD_DAT3")
+ (net 32 "SD_CMD")
+ (net 33 "SD_CLK")
+ (net 34 "SD_DAT0")
+ (net 35 "SD_DAT1")
+ (net 36 "SD_DET")
+ (net 37 "SWDIO")
+ (net 38 "SWCLK")
+ (net 39 "UART_TX")
+ (net 40 "UART_RX")
+ (net 41 "JTAG_TDO")
+ (net 42 "JTAG_TDI")
+ (net 43 "JTAG_TCK")
+ (net 44 "JTAG_TMS")
+ (net 45 "Net-(BT1-Pad1)")
+ (net 46 "GND")
+ (net 47 "I2C_SDA")
+ (net 48 "I2C_SCL")
+ (net 49 "RTC_MFP")
+ (net 50 "+3V3")
+ (net 51 "N64_3V3")
+ (net 52 "+5V")
+ (net 53 "FLASH_CS")
+ (net 54 "FLASH_IO1")
+ (net 55 "FLASH_IO2")
+ (net 56 "FLASH_IO0")
+ (net 57 "FLASH_CLK")
+ (net 58 "FLASH_IO3")
+ (net 59 "FTDI_D0")
+ (net 60 "FTDI_D1")
+ (net 61 "FTDI_D2")
+ (net 62 "FTDI_D3")
+ (net 63 "FTDI_D4")
+ (net 64 "FTDI_D5")
+ (net 65 "FTDI_D6")
+ (net 66 "FTDI_D7")
+ (net 67 "FTDI_C0")
+ (net 68 "FTDI_C1")
+ (net 69 "FTDI_C2")
+ (net 70 "~{N64_WRITE}")
+ (net 71 "~{N64_READ}")
+ (net 72 "~{N64_RESET}")
+ (net 73 "~{N64_INT}")
+ (net 74 "~{N64_NMI}")
+ (net 75 "SDRAM_DQ0")
+ (net 76 "SDRAM_DQ1")
+ (net 77 "SDRAM_DQ2")
+ (net 78 "SDRAM_DQ3")
+ (net 79 "SDRAM_DQ4")
+ (net 80 "SDRAM_DQ5")
+ (net 81 "SDRAM_DQ6")
+ (net 82 "SDRAM_DQ7")
+ (net 83 "SDRAM_DQ8")
+ (net 84 "SDRAM_DQ9")
+ (net 85 "SDRAM_DQ10")
+ (net 86 "SDRAM_DQ11")
+ (net 87 "SDRAM_DQ12")
+ (net 88 "SDRAM_DQ13")
+ (net 89 "SDRAM_DQ14")
+ (net 90 "SDRAM_DQ15")
+ (net 91 "FPGA_CLK")
+ (net 92 "MCU_CS")
+ (net 93 "MCU_MOSI")
+ (net 94 "MCU_MISO")
+ (net 95 "MCU_INT")
+ (net 96 "SDRAM_DQML")
+ (net 97 "~{SDRAM_WE}")
+ (net 98 "~{SDRAM_CAS}")
+ (net 99 "~{SDRAM_RAS}")
+ (net 100 "~{SDRAM_CS}")
+ (net 101 "SDRAM_BA0")
+ (net 102 "SDRAM_BA1")
+ (net 103 "SDRAM_A10")
+ (net 104 "SDRAM_A0")
+ (net 105 "SDRAM_A1")
+ (net 106 "SDRAM_A2")
+ (net 107 "SDRAM_A3")
+ (net 108 "SDRAM_A4")
+ (net 109 "SDRAM_A5")
+ (net 110 "SDRAM_A6")
+ (net 111 "SDRAM_A7")
+ (net 112 "SDRAM_A8")
+ (net 113 "SDRAM_A9")
+ (net 114 "SDRAM_A11")
+ (net 115 "SDRAM_A12")
+ (net 116 "SDRAM_CLK")
+ (net 117 "SDRAM_DQMH")
+ (net 118 "FTDI_C3")
+ (net 119 "FTDI_C4")
+ (net 120 "FTDI_C5")
+ (net 121 "FTDI_C6")
+ (net 122 "LED")
+ (net 123 "TEST1")
+ (net 124 "TEST2")
+ (net 125 "FTDI_C7")
+ (net 126 "USB_D+")
+ (net 127 "USB_D-")
+ (net 128 "Net-(D1-Pad2)")
+ (net 129 "BUTTON")
+ (net 130 "unconnected-(SW1-Pad4)")
+ (net 131 "unconnected-(J_N1-Pad24)")
+ (net 132 "unconnected-(J_N1-Pad49)")
+ (net 133 "TEST3")
+ (net 134 "MCU_SCLK")
+ (net 135 "unconnected-(U2-Pad1)")
+ (net 136 "Net-(C3-Pad1)")
+ (net 137 "Net-(J1-PadA5)")
+ (net 138 "unconnected-(J1-PadA8)")
+ (net 139 "Net-(J1-PadB5)")
+ (net 140 "unconnected-(J1-PadB8)")
+ (net 141 "Net-(R1-Pad2)")
+ (net 142 "Net-(R3-Pad1)")
+ (net 143 "Net-(R10-Pad1)")
+ (net 144 "USB_EEDATA")
+ (net 145 "USB_CLK")
+ (net 146 "unconnected-(U3-Pad2)")
+ (net 147 "unconnected-(U3-Pad32)")
+ (net 148 "unconnected-(U3-Pad33)")
+ (net 149 "USB_EECLK")
+ (net 150 "USB_EECS")
+ (net 151 "unconnected-(U6-Pad3)")
+ (net 152 "unconnected-(U8-Pad129)")
+ (net 153 "unconnected-(U9-Pad40)")
+ (net 154 "Net-(C7-Pad2)")
+ (net 155 "Net-(C8-Pad1)")
+ (net 156 "Net-(C14-Pad2)")
+ (net 157 "Net-(R13-Pad1)")
+ (net 158 "Net-(C21-Pad1)")
+ (net 159 "Net-(C22-Pad2)")
+ (net 160 "Net-(C13-Pad2)")
+ (net 161 "Net-(R6-Pad2)")
+ (net 162 "Net-(R7-Pad2)")
+
+ (footprint "Resistor_SMD:R_0603_1608Metric" (layer "F.Cu")
+ (tedit 5F68FEEE) (tstamp 0f7c3f4f-27a9-4c81-8f37-7dcf0241c04c)
+ (at 107.825 117 180)
+ (descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+ (tags "resistor")
+ (property "Sheetfile" "sc64v2.kicad_sch")
+ (property "Sheetname" "")
+ (path "/8225742a-f816-4b22-8618-1e188dae72ec")
+ (attr smd)
+ (fp_text reference "R1" (at -2.675 0) (layer "F.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp b0554a85-99be-4a6f-880d-e1cbcf17beaf)
+ )
+ (fp_text value "10k" (at 0 1.43) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp 7661c2cb-ebab-477a-b6fc-c68a9c995993)
+ )
+ (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
+ (effects (font (size 0.4 0.4) (thickness 0.06)))
+ (tstamp f033f08e-a070-43dd-87f5-d75ca8d58c43)
+ )
+ (fp_line (start -0.237258 -0.5225) (end 0.237258 -0.5225) (layer "F.SilkS") (width 0.12) (tstamp 20821350-bc01-4b93-9f5c-f4d7bb2d30c9))
+ (fp_line (start -0.237258 0.5225) (end 0.237258 0.5225) (layer "F.SilkS") (width 0.12) (tstamp a9d7ac0f-81f3-4d62-bc76-a149dfe15225))
+ (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer "F.CrtYd") (width 0.05) (tstamp 1613c98a-3b2a-437d-b44a-5e83c6399e33))
+ (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer "F.CrtYd") (width 0.05) (tstamp 38ac0e9f-7a85-494f-a54f-13564a0dc2be))
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+ (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer "F.CrtYd") (width 0.05) (tstamp a0ff102f-fd96-4765-8058-29ab2bd67cb1))
+ (fp_line (start 0.8 -0.4125) (end 0.8 0.4125) (layer "F.Fab") (width 0.1) (tstamp 0cad109b-7dc4-4996-9c5d-ca91e965de32))
+ (fp_line (start -0.8 -0.4125) (end 0.8 -0.4125) (layer "F.Fab") (width 0.1) (tstamp 2732e926-f7c3-48de-8851-17a1d24ff6fd))
+ (fp_line (start -0.8 0.4125) (end -0.8 -0.4125) (layer "F.Fab") (width 0.1) (tstamp 2efafc52-b5dc-4117-9d45-058209700122))
+ (fp_line (start 0.8 0.4125) (end -0.8 0.4125) (layer "F.Fab") (width 0.1) (tstamp 5cab3ca7-2559-436c-97c7-0899b7018f86))
+ (pad "1" smd roundrect (at -0.825 0 180) (size 0.8 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 136 "Net-(C3-Pad1)") (pintype "passive") (tstamp b259ee29-ba29-4f09-99c5-82c9cbe3ee80))
+ (pad "2" smd roundrect (at 0.825 0 180) (size 0.8 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 141 "Net-(R1-Pad2)") (pintype "passive") (tstamp 07485bf4-b6a8-4498-b0e2-a778cfab7c94))
+ (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
+ (offset (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (footprint "Package_QFP:LQFP-48_7x7mm_P0.5mm" (layer "F.Cu")
+ (tedit 5D9F72AF) (tstamp 1865821f-f182-4fc3-a9b1-276cdef4665c)
+ (at 132.5 104 90)
+ (descr "LQFP, 48 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2358-16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+ (tags "LQFP QFP")
+ (property "Sheetfile" "sc64v2.kicad_sch")
+ (property "Sheetname" "")
+ (path "/6e901f8d-de31-4712-9607-3a9979e49550")
+ (attr smd)
+ (fp_text reference "U3" (at 0 -6.5 180) (layer "F.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp 7f9c41b1-49a3-4434-be3f-42221a164867)
+ )
+ (fp_text value "FT232HL" (at 0 1 90) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp 84684dd0-00ad-472d-a60f-437f4b81abb9)
+ )
+ (fp_text user "${REFERENCE}" (at 0 -6 90) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp f885d360-6fd5-427f-a6f6-393304067f88)
+ )
+ (fp_line (start 3.61 3.61) (end 3.61 3.16) (layer "F.SilkS") (width 0.12) (tstamp 2215fcc9-7ccb-46f1-8531-62382023d38d))
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+ (model "${KICAD6_3DMODEL_DIR}/Package_QFP.3dshapes/LQFP-48_7x7mm_P0.5mm.wrl"
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+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (footprint "Capacitor_SMD:C_0603_1608Metric" (layer "F.Cu")
+ (tedit 5F68FEEE) (tstamp 18db2538-d0d9-4bf6-93fb-a94a46eeab69)
+ (at 118.75 110.75 90)
+ (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+ (tags "capacitor")
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+ (pad "29" smd roundrect (at -10.6625 5.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 46 "GND") (pinfunction "GND") (pintype "power_in") (tstamp d2d8b90f-1cc3-46b8-ae12-2efddeab106a))
+ (pad "30" smd roundrect (at -10.6625 5.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 50 "+3V3") (pinfunction "VCCIO3") (pintype "power_in") (tstamp 4fd71c9f-fda7-44dc-a730-71f9a293687a))
+ (pad "31" smd roundrect (at -10.6625 6.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 72 "~{N64_RESET}") (pinfunction "PL23D") (pintype "bidirectional") (tstamp f049ccda-80da-4a79-bdbd-120ab1cbdd64))
+ (pad "32" smd roundrect (at -10.6625 6.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 73 "~{N64_INT}") (pinfunction "PL24A") (pintype "bidirectional") (tstamp 85b30a72-2286-4f4b-9644-be52d496f960))
+ (pad "33" smd roundrect (at -10.6625 7.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 16 "N64_PIF_CLK") (pinfunction "PL24B") (pintype "bidirectional") (tstamp ce6fab27-0c0a-45c5-b304-bedf2a2363ca))
+ (pad "34" smd roundrect (at -10.6625 7.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 28 "N64_CIC_CLK") (pinfunction "PL25A") (pintype "bidirectional") (tstamp 7491255a-1f2f-444b-a433-59664b45004d))
+ (pad "35" smd roundrect (at -10.6625 8.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 15 "N64_CIC_DATA") (pinfunction "PL25B") (pintype "bidirectional") (tstamp dd833fe9-3e27-4443-b300-ef655e704311))
+ (pad "36" smd roundrect (at -10.6625 8.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 50 "+3V3") (pinfunction "VCC") (pintype "power_in") (tstamp 8f379579-e294-46e7-ab1c-e5e4b2ef7d0c))
+ (pad "37" smd roundrect (at -8.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 50 "+3V3") (pinfunction "VCCIO2") (pintype "power_in") (tstamp f7af00b0-76c3-459f-8c46-f5a83dd3bee8))
+ (pad "38" smd roundrect (at -8.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 27 "N64_AD7") (pinfunction "PB4A") (pintype "bidirectional") (tstamp da8c55c6-63df-473c-9e1e-fdce7c38b264))
+ (pad "39" smd roundrect (at -7.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 14 "N64_AD8") (pinfunction "PB4B") (pintype "bidirectional") (tstamp 7d646651-5aef-453f-ad93-710225b27da3))
+ (pad "40" smd roundrect (at -7.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 26 "N64_AD6") (pinfunction "PB6A/CSSPIN") (pintype "bidirectional") (tstamp cada0bea-1c13-43de-8c76-f71887adf217))
+ (pad "41" smd roundrect (at -6.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 13 "N64_AD9") (pinfunction "PB6B") (pintype "bidirectional") (tstamp 08f043dd-bcf7-4acd-8635-32f5deb1da95))
+ (pad "42" smd roundrect (at -6.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 12 "N64_AD10") (pinfunction "PB9A") (pintype "bidirectional") (tstamp a98f71dd-c354-4853-808a-84ac5a6fd5b8))
+ (pad "43" smd roundrect (at -5.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 25 "N64_AD5") (pinfunction "PB9B") (pintype "bidirectional") (tstamp 77c3608e-7555-4ea2-9cf6-8b737d2fa1ab))
+ (pad "44" smd roundrect (at -5.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 11 "N64_AD11") (pinfunction "PB12A/MCLK/CCLK") (pintype "bidirectional") (tstamp 24217754-65f8-4058-9ca8-8216e58d0e1a))
+ (pad "45" smd roundrect (at -4.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 24 "N64_AD4") (pinfunction "PB12B/SO/SPISO") (pintype "bidirectional") (tstamp 8a32e254-34b1-4b9c-b7a4-13d903135be2))
+ (pad "46" smd roundrect (at -4.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 46 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 1c29e414-397e-4fe3-9282-d1236b08d101))
+ (pad "47" smd roundrect (at -3.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 71 "~{N64_READ}") (pinfunction "PB13A") (pintype "bidirectional") (tstamp 27208b49-19e9-4d2b-ae5f-f9d3f61dd96a))
+ (pad "48" smd roundrect (at -3.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 23 "N64_ALEH") (pinfunction "PB13B") (pintype "bidirectional") (tstamp e1db068e-8ed8-4edf-a7f4-035239f5ddee))
+ (pad "49" smd roundrect (at -2.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 70 "~{N64_WRITE}") (pinfunction "PB16A/PCLKT2_0") (pintype "bidirectional") (tstamp 80e098c7-ff0f-40d9-839f-9ee0ada137c7))
+ (pad "50" smd roundrect (at -2.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 22 "N64_ALEL") (pinfunction "PB16B/PCLKC2_0") (pintype "bidirectional") (tstamp 931b2192-b16b-4ebe-b929-3a8ff8451b32))
+ (pad "51" smd roundrect (at -1.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 50 "+3V3") (pinfunction "VCCIO2") (pintype "power_in") (tstamp 52a0f0b5-ecc7-4927-b13c-0655c9a7b663))
+ (pad "52" smd roundrect (at -1.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 10 "N64_AD12") (pinfunction "PB18A") (pintype "bidirectional") (tstamp 6c900bf0-cac7-4987-a689-121ebc5161e1))
+ (pad "53" smd roundrect (at -0.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 46 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 5de151cb-70ef-4de6-8791-7554d8803ed7))
+ (pad "54" smd roundrect (at -0.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 21 "N64_AD3") (pinfunction "PB18B") (pintype "bidirectional") (tstamp adeb541d-0e55-423b-b1a5-ac8cec777f8d))
+ (pad "55" smd roundrect (at 0.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 9 "N64_AD13") (pinfunction "PB23A/PCLKT2_1") (pintype "bidirectional") (tstamp ae2697a6-5b6c-4144-a80c-f59c20cf01e1))
+ (pad "56" smd roundrect (at 0.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 20 "N64_AD2") (pinfunction "PB23B/PCLKC2_1") (pintype "bidirectional") (tstamp 7c047bc0-9e6e-464e-8bc2-a129de6017bb))
+ (pad "57" smd roundrect (at 1.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 8 "N64_AD14") (pinfunction "PB26A") (pintype "bidirectional") (tstamp e417e4c5-b508-4e5a-afd1-7dc505f57056))
+ (pad "58" smd roundrect (at 1.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 19 "N64_AD1") (pinfunction "PB26B") (pintype "bidirectional") (tstamp f535cada-7757-4632-8f16-ee8a06da7cc6))
+ (pad "59" smd roundrect (at 2.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 7 "N64_AD15") (pinfunction "PB29A") (pintype "bidirectional") (tstamp 67522698-b563-4886-bdbf-5c433326fba2))
+ (pad "60" smd roundrect (at 2.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 18 "N64_AD0") (pinfunction "PB29B") (pintype "bidirectional") (tstamp 9f3fe97e-1e9e-485d-9bc4-cdfd2b3b791e))
+ (pad "61" smd roundrect (at 3.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 116 "SDRAM_CLK") (pinfunction "PB31A") (pintype "bidirectional") (tstamp 94e07222-a37e-40c1-9001-a754ffe8b148))
+ (pad "62" smd roundrect (at 3.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 115 "SDRAM_A12") (pinfunction "PB31B") (pintype "bidirectional") (tstamp 6ab0df03-3bba-4c66-ae19-73cf336e8ecc))
+ (pad "63" smd roundrect (at 4.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 114 "SDRAM_A11") (pinfunction "PB31D") (pintype "bidirectional") (tstamp 511544ba-bbf8-4f33-a977-0fcd63e86ccc))
+ (pad "64" smd roundrect (at 4.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 46 "GND") (pinfunction "GND") (pintype "power_in") (tstamp dbac7066-2fdd-4dac-b00e-c1d1e9a2ff24))
+ (pad "65" smd roundrect (at 5.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 113 "SDRAM_A9") (pinfunction "PB35A") (pintype "bidirectional") (tstamp 896232b1-e057-4484-b9cd-53ea18de7753))
+ (pad "66" smd roundrect (at 5.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 50 "+3V3") (pinfunction "VCCIO2") (pintype "power_in") (tstamp 1fa53ba4-9572-4824-9c7a-49a94b999a8e))
+ (pad "67" smd roundrect (at 6.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 112 "SDRAM_A8") (pinfunction "PB35B") (pintype "bidirectional") (tstamp 8e1c7203-9931-4994-8c3c-15dd9e303d95))
+ (pad "68" smd roundrect (at 6.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 111 "SDRAM_A7") (pinfunction "PB37A") (pintype "bidirectional") (tstamp 08732a30-5b7f-491c-9f7e-c143a39ece72))
+ (pad "69" smd roundrect (at 7.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 110 "SDRAM_A6") (pinfunction "PB37B") (pintype "bidirectional") (tstamp 8797612e-14ed-44eb-a090-2a8aad427753))
+ (pad "70" smd roundrect (at 7.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 109 "SDRAM_A5") (pinfunction "PB38A/SN") (pintype "bidirectional") (tstamp a63bc584-eeb6-40c6-8804-6cb35a542b24))
+ (pad "71" smd roundrect (at 8.25 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 108 "SDRAM_A4") (pinfunction "PB38B/SI/SISPI") (pintype "bidirectional") (tstamp 89e5d9c8-0bb3-4443-b8fd-6941fecb950e))
+ (pad "72" smd roundrect (at 8.75 10.6625) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 50 "+3V3") (pinfunction "VCC") (pintype "power_in") (tstamp 0b7445ea-e103-4e5b-9a00-dd53e991655e))
+ (pad "73" smd roundrect (at 10.6625 8.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 117 "SDRAM_DQMH") (pinfunction "PR24B") (pintype "bidirectional") (tstamp 0f5e332d-aeaa-4ead-958c-993a39728c19))
+ (pad "74" smd roundrect (at 10.6625 8.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 83 "SDRAM_DQ8") (pinfunction "PR24A") (pintype "bidirectional") (tstamp e9ceb823-c334-4f2e-8d99-229361de873b))
+ (pad "75" smd roundrect (at 10.6625 7.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 84 "SDRAM_DQ9") (pinfunction "PR23B") (pintype "bidirectional") (tstamp 323166a4-910a-417b-8c7d-c03feb7ffad4))
+ (pad "76" smd roundrect (at 10.6625 7.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 85 "SDRAM_DQ10") (pinfunction "PR23A") (pintype "bidirectional") (tstamp eaa51897-930a-4f8d-a8ef-555c39f2a2a9))
+ (pad "77" smd roundrect (at 10.6625 6.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 86 "SDRAM_DQ11") (pinfunction "PR21B") (pintype "bidirectional") (tstamp c98d36b8-9034-4cc3-842e-e855c4c8d2d2))
+ (pad "78" smd roundrect (at 10.6625 6.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 87 "SDRAM_DQ12") (pinfunction "PR21A") (pintype "bidirectional") (tstamp 906b5f7a-936d-45b9-9540-4d3934a93429))
+ (pad "79" smd roundrect (at 10.6625 5.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 50 "+3V3") (pinfunction "VCCIO1") (pintype "power_in") (tstamp c6e0a66c-1a0d-4a98-bcfd-2d9fcc773fcc))
+ (pad "80" smd roundrect (at 10.6625 5.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 46 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 5b945d17-5db9-4f27-954f-2f26254feeb9))
+ (pad "81" smd roundrect (at 10.6625 4.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 88 "SDRAM_DQ13") (pinfunction "PR18B") (pintype "bidirectional") (tstamp b59c4726-b377-4e6b-88de-b9168b63598e))
+ (pad "82" smd roundrect (at 10.6625 4.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 89 "SDRAM_DQ14") (pinfunction "PR18A") (pintype "bidirectional") (tstamp 9b5d8fad-a9d5-4261-94ae-888d349a7fb4))
+ (pad "83" smd roundrect (at 10.6625 3.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 90 "SDRAM_DQ15") (pinfunction "PR17B") (pintype "bidirectional") (tstamp a2634fce-63a7-464e-949e-676604bb3aff))
+ (pad "84" smd roundrect (at 10.6625 3.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 103 "SDRAM_A10") (pinfunction "PR17A") (pintype "bidirectional") (tstamp 251dee92-c362-41db-a1bd-8b45e6177357))
+ (pad "85" smd roundrect (at 10.6625 2.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 104 "SDRAM_A0") (pinfunction "PR16B") (pintype "bidirectional") (tstamp f5a2439b-06cb-41f4-a35c-c0e90d1afb13))
+ (pad "86" smd roundrect (at 10.6625 2.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 105 "SDRAM_A1") (pinfunction "PR16A") (pintype "bidirectional") (tstamp 076e6292-e03c-4264-8e1a-38fc388ff7ba))
+ (pad "87" smd roundrect (at 10.6625 1.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 106 "SDRAM_A2") (pinfunction "PR15B") (pintype "bidirectional") (tstamp 0ccea004-159c-4140-b5bd-f9753bf6d9f0))
+ (pad "88" smd roundrect (at 10.6625 1.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 50 "+3V3") (pinfunction "VCCIO1") (pintype "power_in") (tstamp 3e23ff80-976e-481f-b649-d3b6afc29a05))
+ (pad "89" smd roundrect (at 10.6625 0.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 107 "SDRAM_A3") (pinfunction "PR15A") (pintype "bidirectional") (tstamp 4afbcab0-8772-4bb7-8c18-21fe06bf2973))
+ (pad "90" smd roundrect (at 10.6625 0.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 46 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 1f52d044-35a1-4971-a033-158db0c09f89))
+ (pad "91" smd roundrect (at 10.6625 -0.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 102 "SDRAM_BA1") (pinfunction "PR12B/PCLKC1_0") (pintype "bidirectional") (tstamp 2cd4200f-d3e2-47d7-9e04-6340e4870ffc))
+ (pad "92" smd roundrect (at 10.6625 -0.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 101 "SDRAM_BA0") (pinfunction "PR12A/PCLKT1_0") (pintype "bidirectional") (tstamp 696fc689-c13d-4a9e-abe6-d97c1df0b026))
+ (pad "93" smd roundrect (at 10.6625 -1.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 100 "~{SDRAM_CS}") (pinfunction "PR11B") (pintype "bidirectional") (tstamp 44ceed4d-02f1-4589-87bb-12242eec59cf))
+ (pad "94" smd roundrect (at 10.6625 -1.75) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 99 "~{SDRAM_RAS}") (pinfunction "PR11A") (pintype "bidirectional") (tstamp fd359357-19b0-4f4e-8f3e-cbd63c2c758b))
+ (pad "95" smd roundrect (at 10.6625 -2.25) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 98 "~{SDRAM_CAS}") (pinfunction "PR9B") (pintype "bidirectional") (tstamp 058f45a1-dd8e-4168-b397-fb3e1bc2348f))
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diff --git a/hw/pcb/sc64v2.kicad_pro b/hw/pcb/sc64v2.kicad_pro
new file mode 100644
index 0000000..4969e6a
--- /dev/null
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@@ -0,0 +1,435 @@
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diff --git a/hw/pcb/sc64v2.kicad_sch b/hw/pcb/sc64v2.kicad_sch
new file mode 100644
index 0000000..07d1a3b
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+ (reference "C4") (unit 1) (value "47uF") (footprint "Capacitor_SMD:C_0805_2012Metric")
+ )
+ (path "/13d2b351-5091-4e28-9a5e-2a00667fbc07"
+ (reference "C5") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/8875e69d-d89e-41ba-bde2-45767e9df445"
+ (reference "C6") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/5eb8655d-026d-48b3-9313-87b558b7f693"
+ (reference "C7") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/03085d81-2734-4969-bd47-0eafbab0f38e"
+ (reference "C8") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/2fe178e5-f305-4d73-9f34-5dc926fbad07"
+ (reference "C9") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/b1eae589-88fc-49de-92a5-165aa1590642"
+ (reference "C10") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/81faf8c0-1827-4289-ab03-9e47b8583766"
+ (reference "C11") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/5f5a5875-6a56-4582-a73d-ebf515c445e5"
+ (reference "C12") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/0f368328-b928-4c36-bde8-df1e5494dab0"
+ (reference "C13") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/fe7d11ce-921f-4c35-a390-452b3002c6eb"
+ (reference "C14") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/04819b2b-cb43-4cae-baac-01caae26be72"
+ (reference "C15") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/9b5d4a16-c0ac-4bd5-96ac-9f9edadfcd60"
+ (reference "C16") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/0a51cd04-5336-4bfb-ac7b-21533c8d00bb"
+ (reference "C17") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/614914c2-3abd-4f26-90db-4b83af4389e9"
+ (reference "C18") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/9a8905a3-5ca0-46a1-bee9-ca122e954a22"
+ (reference "C19") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/d21e5415-679a-40f4-b9d3-0f558c2e3abf"
+ (reference "C20") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/994dc62b-2a7b-4bff-8f5a-68d36773f4c8"
+ (reference "C21") (unit 1) (value "12pF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/13265650-3af2-4401-adaf-15efd42a756b"
+ (reference "C22") (unit 1) (value "12pF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/49f3385c-4a1a-4ed1-a308-2c37f51240ba"
+ (reference "C23") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/fd1e1286-95a1-43a4-bd11-65aa433249c2"
+ (reference "C24") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/e1f00983-a235-4d69-9d9e-906d079c4b90"
+ (reference "C25") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/acd48532-9df4-4213-8073-4ea5ab05ba2a"
+ (reference "C26") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/c3135751-427f-42d2-9a94-3179d7de2153"
+ (reference "C27") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/4f8814bc-1ddc-4d9d-8341-e717fa829f27"
+ (reference "C28") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/2bbbf7e2-fec0-4e0e-af5e-d1d876305dd1"
+ (reference "C29") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/5641d56b-9829-49e8-b5b5-4c281f49578e"
+ (reference "C30") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/e1080d6b-d7da-48f7-b6bc-20790315d00d"
+ (reference "C31") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/e505a7b3-3ba0-4037-b4e7-40457055df66"
+ (reference "C32") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/6f6c2377-8039-497e-9b10-e130c951f0c3"
+ (reference "C33") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/79c68ec7-484d-45d8-b8ea-7b0a7306e7c6"
+ (reference "C34") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/5a894943-2e60-4640-96a2-a55eb4cfef14"
+ (reference "C35") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/8b893dd0-e97f-4683-8d2e-b0e1c10c6051"
+ (reference "C36") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/368cbd0e-6260-44d9-af09-bc08be9667bd"
+ (reference "C37") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/84b8b021-1eac-40ec-9d18-9bb490fec58a"
+ (reference "C38") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/109c53cf-c8a3-456a-9546-7c3328fa259a"
+ (reference "C39") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/bc7d6f8c-6dfc-49b5-ab62-ccadd92d55cc"
+ (reference "C40") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/a61e6e2e-0cef-4616-939d-fadea790ce4f"
+ (reference "C41") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/807f06fd-69e9-4462-bc69-40d576fe8720"
+ (reference "C42") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/4a8503ee-5770-4f04-9dfc-cfd261659fa9"
+ (reference "C43") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/1df87e80-2d07-4a8a-bb5b-e5faf9d9c905"
+ (reference "C44") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/65dd3f32-98df-4103-ac72-9d5146d33dfe"
+ (reference "C45") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/aeb0d0cf-6d04-4e89-836d-342f2e598d6b"
+ (reference "C46") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/25b1fb90-87c1-483e-8933-09b55f4fd3ab"
+ (reference "C47") (unit 1) (value "100nF") (footprint "Capacitor_SMD:C_0603_1608Metric")
+ )
+ (path "/94dcb139-2876-4a88-9afc-5a91f644dff1"
+ (reference "C48") (unit 1) (value "47uF") (footprint "Capacitor_SMD:C_0805_2012Metric")
+ )
+ (path "/45c5d7eb-fb02-4045-bae4-ce53aa49b4f2"
+ (reference "D1") (unit 1) (value "150060RS75000") (footprint "LED_SMD:LED_0603_1608Metric")
+ )
+ (path "/e5375fae-8d12-42aa-b7f4-67a68780c27e"
+ (reference "GND1") (unit 1) (value "TestPoint") (footprint "TestPoint:TestPoint_Pad_D1.5mm")
+ )
+ (path "/defdcc3f-5dd1-462d-9a3c-629711ed4f38"
+ (reference "J1") (unit 1) (value "DX07S016JA3R1500") (footprint "Connector_USB:USB_C_Receptacle_JAE_DX07S016JA1R1500")
+ )
+ (path "/18505a27-e048-4c99-939f-13bbdf43eb7b"
+ (reference "J2") (unit 1) (value "Conn_01x03_Male") (footprint "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical")
+ )
+ (path "/51744168-bfea-4a8e-8692-c99342c4a1b3"
+ (reference "J3") (unit 1) (value "TC2050-FP") (footprint "sc64v2:TC2050-FP")
+ )
+ (path "/09e47e41-fce2-4be6-a894-63ccba0f1215"
+ (reference "J4") (unit 1) (value "104031-0811") (footprint "Connector_Card:microSD_HC_Molex_104031-0811")
+ )
+ (path "/0ccace5b-45a7-46eb-82b5-c5e6d2488545"
+ (reference "J_N1") (unit 1) (value "N64_Cartridge") (footprint "sc64v2:N64_Edge")
+ )
+ (path "/6a7f3f5f-7361-4bc7-aab9-0a665363dea2"
+ (reference "L1") (unit 1) (value "470R") (footprint "Inductor_SMD:L_0603_1608Metric")
+ )
+ (path "/45ec13fe-5f93-4814-b0a9-2ef724502115"
+ (reference "L2") (unit 1) (value "470R") (footprint "Inductor_SMD:L_0603_1608Metric")
+ )
+ (path "/8225742a-f816-4b22-8618-1e188dae72ec"
+ (reference "R1") (unit 1) (value "10k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/38d3e0bc-e7f3-4fcf-b28b-1dd2ebbed152"
+ (reference "R2") (unit 1) (value "3.3k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/f29baa2d-b8f7-45f8-96ad-5b304188d80b"
+ (reference "R3") (unit 1) (value "470R") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/9676acb4-ecdb-4bb9-8697-bbf28b479ff0"
+ (reference "R4") (unit 1) (value "5.1k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/7ed06213-5fec-4fc2-a07b-97a7e844b4e4"
+ (reference "R5") (unit 1) (value "5.1k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/0c635b0d-75d2-43fe-aa37-07274a83e016"
+ (reference "R6") (unit 1) (value "12k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/53a3914e-49ab-47c6-9e8c-471b61f99f60"
+ (reference "R7") (unit 1) (value "12k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/d1984805-4314-4f1c-9ab1-479802945b94"
+ (reference "R8") (unit 1) (value "12k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/38f041d3-336d-4c45-9e25-efeece1e2340"
+ (reference "R9") (unit 1) (value "5.1k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/f47d1b56-1473-4960-b027-88c1d1af2f5a"
+ (reference "R10") (unit 1) (value "2.2k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/9f9dfac6-0c0d-4ee0-924b-e95250d2b98f"
+ (reference "R11") (unit 1) (value "10k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/f9c93d04-ae88-4458-aada-7c0f1c1f482b"
+ (reference "R12") (unit 1) (value "3.3k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/218503c2-8dbd-4619-ac7b-4c01fe0226fe"
+ (reference "R13") (unit 1) (value "10k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/303e7d15-a601-4397-8721-b9f3cf051807"
+ (reference "R14") (unit 1) (value "2.2k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/aab80820-43a0-4879-aa62-70e3b13add9d"
+ (reference "R15") (unit 1) (value "2.2k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/7295e019-ebb9-424a-ad6e-06fdc7f816d8"
+ (reference "R16") (unit 1) (value "10k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/83ac819d-dfbc-422a-a76f-f95cac775ba2"
+ (reference "R17") (unit 1) (value "10k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/351bd7d9-24e6-4a96-9b71-d9b4f5d9bd9a"
+ (reference "R18") (unit 1) (value "470R") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/57757361-0691-4a91-bc3d-0dc7562fcbe2"
+ (reference "R19") (unit 1) (value "10k") (footprint "Resistor_SMD:R_0603_1608Metric")
+ )
+ (path "/95782e76-cb4b-4009-9945-08a041720df8"
+ (reference "SW1") (unit 1) (value "TS07-667-37-BK-160-SMT") (footprint "Button_Switch_SMD:SW_SPST_Omron_B3FS-101xP")
+ )
+ (path "/fd9f5719-35a0-432f-9a74-8007f2818ce9"
+ (reference "TP1") (unit 1) (value "TestPoint") (footprint "TestPoint:TestPoint_Pad_D1.5mm")
+ )
+ (path "/dc408f8d-04af-4d73-a1d2-90b29f263566"
+ (reference "TP2") (unit 1) (value "TestPoint") (footprint "TestPoint:TestPoint_Pad_D1.5mm")
+ )
+ (path "/e3a53687-1d2c-4f55-a6dc-3cb068c0e853"
+ (reference "TP3") (unit 1) (value "TestPoint") (footprint "TestPoint:TestPoint_Pad_D1.5mm")
+ )
+ (path "/2d0fed17-815d-432f-a7eb-ae8520ef2c33"
+ (reference "U1") (unit 1) (value "TC1264-3.3VDB") (footprint "Package_TO_SOT_SMD:SOT-223-3_TabPin2")
+ )
+ (path "/11199015-56cf-4f32-a080-c15518c28d0f"
+ (reference "U2") (unit 1) (value "TPS2111A") (footprint "Package_SO:TSSOP-8_4.4x3mm_P0.65mm")
+ )
+ (path "/6e901f8d-de31-4712-9607-3a9979e49550"
+ (reference "U3") (unit 1) (value "FT232HL") (footprint "Package_QFP:LQFP-48_7x7mm_P0.5mm")
+ )
+ (path "/a669f65a-ba28-488f-8876-920a059fc027"
+ (reference "U4") (unit 1) (value "93AA56Bx-x/OT") (footprint "Package_TO_SOT_SMD:SOT-23-6")
+ )
+ (path "/0fc6d60f-b51b-46bd-9f02-cc292d56b643"
+ (reference "U5") (unit 1) (value "W25Q128JVSIQ") (footprint "Package_SO:SOIC-8_5.23x5.23mm_P1.27mm")
+ )
+ (path "/8a46818f-80b6-48c6-9d8f-04eb3e3ccdb1"
+ (reference "U6") (unit 1) (value "STM32G030F6P6") (footprint "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm")
+ )
+ (path "/766e0844-4cc7-4fee-800a-7bdf93675837"
+ (reference "U7") (unit 1) (value "MCP7940N-x/ST") (footprint "Package_SO:TSSOP-8_4.4x3mm_P0.65mm")
+ )
+ (path "/577a15d5-96bb-4ab6-91f7-9846e15282cb"
+ (reference "U8") (unit 1) (value "LCMXO2-7000Hx-xTG144x") (footprint "Package_QFP:TQFP-144_20x20mm_P0.5mm")
+ )
+ (path "/93ddce85-c1a8-42b3-a16c-75b607cf3749"
+ (reference "U8") (unit 2) (value "LCMXO2-7000Hx-xTG144x") (footprint "Package_QFP:TQFP-144_20x20mm_P0.5mm")
+ )
+ (path "/749a3945-389b-4081-ad7d-147241e86892"
+ (reference "U8") (unit 3) (value "LCMXO2-7000Hx-xTG144x") (footprint "Package_QFP:TQFP-144_20x20mm_P0.5mm")
+ )
+ (path "/d36b5d51-b628-4248-a4a1-d225a2713196"
+ (reference "U8") (unit 4) (value "LCMXO2-7000Hx-xTG144x") (footprint "Package_QFP:TQFP-144_20x20mm_P0.5mm")
+ )
+ (path "/f5284160-b8bd-4591-b634-bcdefecda6c2"
+ (reference "U8") (unit 5) (value "LCMXO2-7000Hx-xTG144x") (footprint "Package_QFP:TQFP-144_20x20mm_P0.5mm")
+ )
+ (path "/7b73b1ca-70af-4411-a26c-1686ab71a5d7"
+ (reference "U8") (unit 6) (value "LCMXO2-7000Hx-xTG144x") (footprint "Package_QFP:TQFP-144_20x20mm_P0.5mm")
+ )
+ (path "/7adce0b2-9540-4d77-8cf1-4df964c29563"
+ (reference "U8") (unit 7) (value "LCMXO2-7000Hx-xTG144x") (footprint "Package_QFP:TQFP-144_20x20mm_P0.5mm")
+ )
+ (path "/1dbbd042-b212-4933-895e-d1a10aa96c60"
+ (reference "U9") (unit 1) (value "IS42S16320F-7TL") (footprint "Package_SO:TSOP-II-54_22.2x10.16mm_P0.8mm")
+ )
+ (path "/a73f4f5a-6e4d-472e-9b51-954e3d116bd7"
+ (reference "X1") (unit 1) (value "ECS-3225MV-120-CN") (footprint "Oscillator:Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm")
+ )
+ (path "/fd95e6e1-2b37-4604-8f85-981efac5e15c"
+ (reference "X2") (unit 1) (value "ECS-3225MV-500-BN") (footprint "Oscillator:Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm")
+ )
+ (path "/c229caf9-bd8e-4df4-8266-2d39e81a3f5d"
+ (reference "Y1") (unit 1) (value "FC-135") (footprint "Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm")
+ )
+ )
+)
diff --git a/hw/shell/sc64_shell.f3d b/hw/shell/sc64_shell.f3d
new file mode 100644
index 0000000..b328450
Binary files /dev/null and b/hw/shell/sc64_shell.f3d differ
diff --git a/hw/shell/sc64_shell_back.stl b/hw/shell/sc64_shell_back.stl
new file mode 100644
index 0000000..a5299a9
Binary files /dev/null and b/hw/shell/sc64_shell_back.stl differ
diff --git a/hw/shell/sc64_shell_front.stl b/hw/shell/sc64_shell_front.stl
new file mode 100644
index 0000000..16e3450
Binary files /dev/null and b/hw/shell/sc64_shell_front.stl differ
diff --git a/sw/n64/.gitignore b/sw/bootloader/.gitignore
similarity index 100%
rename from sw/n64/.gitignore
rename to sw/bootloader/.gitignore
diff --git a/sw/n64/Makefile b/sw/bootloader/Makefile
similarity index 63%
rename from sw/n64/Makefile
rename to sw/bootloader/Makefile
index c54519a..6813317 100644
--- a/sw/n64/Makefile
+++ b/sw/bootloader/Makefile
@@ -4,13 +4,15 @@ CXX = $(TOOLCHAIN)g++
OBJCOPY = $(TOOLCHAIN)objcopy
OBJDUMP = $(TOOLCHAIN)objdump
SIZE = $(TOOLCHAIN)size
+PYTHON = python3
FLAGS = -march=vr4300 -mtune=vr4300 $(USER_FLAGS)
-CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP
+CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -G 0 -MMD -MP
ASFLAGS = -Wa,-I$(N64_INST)/mips64-elf/lib
LDFLAGS = -lc -nostartfiles -Wl,--gc-sections
SRC_DIR = src
+ASSET_DIR = assets
BUILD_DIR = build
SRC_FILES = \
@@ -35,11 +37,15 @@ SRC_FILES = \
fatfs/ffsystem.c \
fatfs/ffunicode.c
-SRCS = $(addprefix $(SRC_DIR)/, $(SRC_FILES))
+ASSET_FILES = \
+ background.png
+
+SRCS = $(SRC_FILES) $(ASSET_FILES)
OBJS = $(addprefix $(BUILD_DIR)/, $(notdir $(patsubst %,%.o,$(SRCS))))
DEPS = $(OBJS:.o=.d)
-
-VPATH = $(SRC_DIR) $(SRC_DIR)/fatfs
+$(info $(SRCS))
+$(info $(OBJS))
+VPATH = $(SRC_DIR) $(SRC_DIR)/fatfs $(ASSET_DIR)
$(@info $(shell mkdir -p ./$(BUILD_DIR) &> /dev/null))
@@ -49,25 +55,29 @@ $(BUILD_DIR)/%.S.o: %.S
$(BUILD_DIR)/%.c.o: %.c
$(CC) $(FLAGS) $(CFLAGS) -c $< -o $@
-$(BUILD_DIR)/n64boot.elf: $(OBJS) N64.ld
- $(CXX) $(FLAGS) $(LDFLAGS) -TN64.ld $(OBJS) -o $@
- @$(OBJDUMP) -S $@ > $(BUILD_DIR)/n64boot.lst
+$(BUILD_DIR)/%.png.o: %.png
+ $(PYTHON) tools/asset_converter.py $< $@
+ $(OBJCOPY) -I binary -O elf32-bigmips -B mips:4000 $@ $@
-$(BUILD_DIR)/n64boot.bin: $(BUILD_DIR)/n64boot.elf
+$(BUILD_DIR)/bootloader.elf: $(OBJS) N64.ld
+ $(CXX) $(FLAGS) $(LDFLAGS) -TN64.ld $(OBJS) -o $@
+ @$(OBJDUMP) -S $@ > $(BUILD_DIR)/bootloader.lst
+
+$(BUILD_DIR)/bootloader.bin: $(BUILD_DIR)/bootloader.elf
@$(OBJCOPY) -O binary $< $@
@chksum64 $@ > /dev/null
- @truncate --size=64k $@
+ @truncate --size=1028k $@
-$(BUILD_DIR)/n64boot.hex: $(BUILD_DIR)/n64boot.bin
+$(BUILD_DIR)/bootloader.hex: $(BUILD_DIR)/bootloader.bin
@$(OBJCOPY) -I binary -O ihex $< $@
-print_size: $(BUILD_DIR)/n64boot.elf
+print_size: $(BUILD_DIR)/bootloader.elf
@echo 'Size of modules:'
@$(SIZE) -B -d -t --common $(OBJS)
- @echo 'Size of n64boot:'
+ @echo 'Size of bootloader:'
@$(SIZE) -B -d $<
-all: $(BUILD_DIR)/n64boot.hex print_size
+all: $(BUILD_DIR)/bootloader.hex print_size
clean:
@rm -rf ./$(BUILD_DIR)/*
diff --git a/sw/n64/N64.ld b/sw/bootloader/N64.ld
similarity index 81%
rename from sw/n64/N64.ld
rename to sw/bootloader/N64.ld
index b4d0349..ecf6f26 100644
--- a/sw/n64/N64.ld
+++ b/sw/bootloader/N64.ld
@@ -1,6 +1,6 @@
MEMORY {
- rdram (rwx) : org = 0x803E0000, len = 128k
- flash (r) : org = 0xB0000000, len = 64k
+ rdram (rwx) : org = 0x80300000, len = 1M
+ flash (r) : org = 0xB0000000, len = 1028k
}
ENTRY(entry_handler)
@@ -14,7 +14,7 @@ SECTIONS {
KEEP(*(.text.ipl3));
} > flash
- .text : {
+ .text : SUBALIGN(4) {
*(.text.entry_handler)
*(.text .text.* .gnu.linkonce.t.*)
*(.rodata .rodata.* .gnu.linkonce.r.*)
@@ -26,11 +26,13 @@ SECTIONS {
} > rdram AT > flash
.bss : {
+ _sbss = .;
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon .scommon.*)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
+ _ebss = .;
} > rdram
_sheap = .;
diff --git a/sw/bootloader/assets/background.png b/sw/bootloader/assets/background.png
new file mode 100644
index 0000000..5d72cf9
Binary files /dev/null and b/sw/bootloader/assets/background.png differ
diff --git a/sw/n64/src/boot.c b/sw/bootloader/src/boot.c
similarity index 95%
rename from sw/n64/src/boot.c
rename to sw/bootloader/src/boot.c
index ed4f61c..30d33b2 100644
--- a/sw/n64/src/boot.c
+++ b/sw/bootloader/src/boot.c
@@ -3,7 +3,7 @@
#include "io.h"
-extern uint32_t ipl2 __attribute__((section(".data")));
+extern uint32_t ipl2;
typedef struct {
diff --git a/sw/n64/src/boot.h b/sw/bootloader/src/boot.h
similarity index 100%
rename from sw/n64/src/boot.h
rename to sw/bootloader/src/boot.h
diff --git a/sw/n64/src/crc32.c b/sw/bootloader/src/crc32.c
similarity index 100%
rename from sw/n64/src/crc32.c
rename to sw/bootloader/src/crc32.c
diff --git a/sw/n64/src/crc32.h b/sw/bootloader/src/crc32.h
similarity index 100%
rename from sw/n64/src/crc32.h
rename to sw/bootloader/src/crc32.h
diff --git a/sw/n64/src/error.c b/sw/bootloader/src/error.c
similarity index 87%
rename from sw/n64/src/error.c
rename to sw/bootloader/src/error.c
index 027bfe9..c76c080 100644
--- a/sw/n64/src/error.c
+++ b/sw/bootloader/src/error.c
@@ -8,4 +8,6 @@ void error_display (const char *fmt, ...) {
va_start(args, fmt);
EXCEPTION_TRIGGER(TRIGGER_CODE_ERROR);
va_end(args);
+
+ while (1);
}
diff --git a/sw/n64/src/error.h b/sw/bootloader/src/error.h
similarity index 100%
rename from sw/n64/src/error.h
rename to sw/bootloader/src/error.h
diff --git a/sw/n64/src/exception.S b/sw/bootloader/src/exception.S
similarity index 100%
rename from sw/n64/src/exception.S
rename to sw/bootloader/src/exception.S
diff --git a/sw/n64/src/exception.c b/sw/bootloader/src/exception.c
similarity index 75%
rename from sw/n64/src/exception.c
rename to sw/bootloader/src/exception.c
index 7a97283..bd706a0 100644
--- a/sw/n64/src/exception.c
+++ b/sw/bootloader/src/exception.c
@@ -1,7 +1,7 @@
#include
#include
-#include "exception.h"
#include "exception_regs.h"
+#include "exception.h"
#include "font.h"
#include "io.h"
#include "sc64.h"
@@ -18,21 +18,16 @@
#define SYSCALL_CODE_BIT (6)
#define SCREEN_WIDTH (640)
-#define SCREEN_HEIGHT_NTSC (240)
-#define SCREEN_HEIGHT_PAL (288)
+#define SCREEN_HEIGHT (240)
#define BORDER_WIDTH (32)
#define BORDER_HEIGHT (16)
-#define BACKGROUND_COLOR (0xFFFFFFFFUL)
-#define FOREGROUND_COLOR (0x000000FFUL)
-#define BORDER_COLOR (0x080808FFUL)
-
+#define TEXT_COLOR (0xFFFFFFFFUL)
#define LINE_HEIGHT (10)
-#define START_X_OFFSET (19)
-extern const io32_t entry_handler __attribute__((section(".data")));
-
+extern const uint32_t _binary_build_background_png_o_start;
+static io32_t exception_framebuffer[SCREEN_WIDTH * SCREEN_HEIGHT] __attribute__((aligned(64)));
static const vi_regs_t vi_config[] = {{
.CR = (
VI_CR_PIXEL_ADVANCE_1 |
@@ -50,7 +45,7 @@ static const vi_regs_t vi_config[] = {{
.H_SYNC = 0x00150C69,
.H_SYNC_LEAP = 0x0C6F0C6E,
.H_LIMITS = 0x00800300,
- .V_LIMITS = 0x002D026D,
+ .V_LIMITS = 0x005D023D,
.COLOR_BURST = 0x00090268,
.H_SCALE = 0x00000400,
.V_SCALE = 0x00000400,
@@ -67,7 +62,7 @@ static const vi_regs_t vi_config[] = {{
.V_INTR = 0x000003FF,
.CURR_LINE = 0x00000000,
.TIMING = 0x03E52239,
- .V_SYNC = 0x0000020C,
+ .V_SYNC = 0x0000020D,
.H_SYNC = 0x00000C15,
.H_SYNC_LEAP = 0x0C150C15,
.H_LIMITS = 0x006C02EC,
@@ -77,35 +72,15 @@ static const vi_regs_t vi_config[] = {{
.V_SCALE = 0x00000400,
}};
-static const int screen_heights[] = {
- SCREEN_HEIGHT_PAL,
- SCREEN_HEIGHT_NTSC,
-};
-
-static int screen_heigth;
-static io32_t *exception_framebuffer;
-
static void exception_init_screen (void) {
const vi_regs_t *cfg = &vi_config[OS_INFO->tv_type];
- screen_heigth = screen_heights[OS_INFO->tv_type];
- exception_framebuffer = (io32_t *) (((io32_t) (&entry_handler)) - (SCREEN_WIDTH * screen_heigth * sizeof(io32_t)));
+ uint32_t *background_data = (uint32_t *) (&_binary_build_background_png_o_start);
- for (int y = 0; y < screen_heigth; y++) {
- for (int x = 0; x < SCREEN_WIDTH; x++) {
- uint32_t color;
- if (
- (x < (BORDER_WIDTH - FONT_WIDTH)) ||
- (x > (SCREEN_WIDTH - (BORDER_WIDTH - FONT_WIDTH))) ||
- (y < (BORDER_HEIGHT - FONT_HEIGHT)) ||
- (y > (screen_heigth - (BORDER_HEIGHT - FONT_HEIGHT)))
- ) {
- color = BORDER_COLOR;
- } else {
- color = BACKGROUND_COLOR;
- }
- io_write(&exception_framebuffer[x + (y * SCREEN_WIDTH)], color);
- }
+ for (int i = 0; i < (SCREEN_WIDTH * SCREEN_HEIGHT); i += 2) {
+ io_write(&exception_framebuffer[i], *background_data);
+ io_write(&exception_framebuffer[i + 1], *background_data);
+ background_data++;
}
io_write(&VI->MADDR, (uint32_t) (exception_framebuffer));
@@ -125,7 +100,7 @@ static void exception_init_screen (void) {
}
static void exception_draw_character (char c) {
- static int x = BORDER_WIDTH + (START_X_OFFSET * FONT_WIDTH);
+ static int x = BORDER_WIDTH;
static int y = BORDER_HEIGHT;
if (c == '\n') {
@@ -147,13 +122,13 @@ static void exception_draw_character (char c) {
int c_x = x + (i % FONT_WIDTH);
int c_y = y + (i / FONT_WIDTH);
- if ((c_x >= (SCREEN_WIDTH - BORDER_WIDTH)) || (c_y >= (screen_heigth - BORDER_HEIGHT))) {
+ if ((c_x >= (SCREEN_WIDTH - BORDER_WIDTH)) || (c_y >= (SCREEN_HEIGHT - BORDER_HEIGHT))) {
break;
}
if (font_data[c - ' '][i / 8] & (1 << (i % 8))) {
int screen_offset = c_x + (c_y * SCREEN_WIDTH);
- io_write(&exception_framebuffer[screen_offset], FOREGROUND_COLOR);
+ io_write(&exception_framebuffer[screen_offset], TEXT_COLOR);
}
}
@@ -212,12 +187,11 @@ void exception_fatal_handler (uint32_t exception_code, uint32_t interrupt_mask,
exception_init_screen();
- exception_print("----- n64boot SummerCart64 -----\n");
exception_print("branch: %s\n", version->git_branch);
exception_print("tag: %s\n", version->git_tag);
exception_print("sha: %s\n\n", version->git_sha);
- exception_print("%s at pc: 0x%08lX\n", exception_get_description(exception_code), e->epc.u32);
- exception_print("sr: 0x%08lX cr: 0x%08lX hw: 0x%08lX [%4s]\n", e->sr, e->cr, sc64_version, (char *) (&sc64_version));
+ exception_print("%s\n\n", exception_get_description(exception_code));
+ exception_print("pc: 0x%08lX sr: 0x%08lX cr: 0x%08lX hw: 0x%08lX [%.4s]\n", e->epc.u32, e->sr, e->cr, sc64_version, (char *) (&sc64_version));
exception_print("zr: 0x%08lX at: 0x%08lX v0: 0x%08lX v1: 0x%08lX\n", e->zr.u32, e->at.u32, e->v0.u32, e->v1.u32);
exception_print("a0: 0x%08lX a1: 0x%08lX a2: 0x%08lX a3: 0x%08lX\n", e->a0.u32, e->a1.u32, e->a2.u32, e->a3.u32);
exception_print("t0: 0x%08lX t1: 0x%08lX t2: 0x%08lX t3: 0x%08lX\n", e->t0.u32, e->t1.u32, e->t2.u32, e->t3.u32);
diff --git a/sw/n64/src/exception.h b/sw/bootloader/src/exception.h
similarity index 100%
rename from sw/n64/src/exception.h
rename to sw/bootloader/src/exception.h
diff --git a/sw/n64/src/exception_regs.h b/sw/bootloader/src/exception_regs.h
similarity index 100%
rename from sw/n64/src/exception_regs.h
rename to sw/bootloader/src/exception_regs.h
diff --git a/sw/n64/src/fatfs/00history.txt b/sw/bootloader/src/fatfs/00history.txt
similarity index 100%
rename from sw/n64/src/fatfs/00history.txt
rename to sw/bootloader/src/fatfs/00history.txt
diff --git a/sw/n64/src/fatfs/00readme.txt b/sw/bootloader/src/fatfs/00readme.txt
similarity index 100%
rename from sw/n64/src/fatfs/00readme.txt
rename to sw/bootloader/src/fatfs/00readme.txt
diff --git a/sw/n64/src/fatfs/diskio.c b/sw/bootloader/src/fatfs/diskio.c
similarity index 100%
rename from sw/n64/src/fatfs/diskio.c
rename to sw/bootloader/src/fatfs/diskio.c
diff --git a/sw/n64/src/fatfs/diskio.h b/sw/bootloader/src/fatfs/diskio.h
similarity index 100%
rename from sw/n64/src/fatfs/diskio.h
rename to sw/bootloader/src/fatfs/diskio.h
diff --git a/sw/n64/src/fatfs/ff.c b/sw/bootloader/src/fatfs/ff.c
similarity index 100%
rename from sw/n64/src/fatfs/ff.c
rename to sw/bootloader/src/fatfs/ff.c
diff --git a/sw/n64/src/fatfs/ff.h b/sw/bootloader/src/fatfs/ff.h
similarity index 100%
rename from sw/n64/src/fatfs/ff.h
rename to sw/bootloader/src/fatfs/ff.h
diff --git a/sw/n64/src/fatfs/ffconf.h b/sw/bootloader/src/fatfs/ffconf.h
similarity index 96%
rename from sw/n64/src/fatfs/ffconf.h
rename to sw/bootloader/src/fatfs/ffconf.h
index 33c16b4..0e48a24 100644
--- a/sw/n64/src/fatfs/ffconf.h
+++ b/sw/bootloader/src/fatfs/ffconf.h
@@ -15,7 +15,7 @@
/ and optional writing functions as well. */
-#define FF_FS_MINIMIZE 1
+#define FF_FS_MINIMIZE 0
/* This option defines minimization level to remove some basic API functions.
/
/ 0: Basic functions are fully enabled.
@@ -25,7 +25,7 @@
/ 3: f_lseek() function is removed in addition to 2. */
-#define FF_USE_FIND 0
+#define FF_USE_FIND 1
/* This option switches filtered directory read functions, f_findfirst() and
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
@@ -52,7 +52,7 @@
/ (0:Disable or 1:Enable) */
-#define FF_USE_FORWARD 0
+#define FF_USE_FORWARD 1
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
diff --git a/sw/n64/src/fatfs/ffsystem.c b/sw/bootloader/src/fatfs/ffsystem.c
similarity index 100%
rename from sw/n64/src/fatfs/ffsystem.c
rename to sw/bootloader/src/fatfs/ffsystem.c
diff --git a/sw/n64/src/fatfs/ffunicode.c b/sw/bootloader/src/fatfs/ffunicode.c
similarity index 100%
rename from sw/n64/src/fatfs/ffunicode.c
rename to sw/bootloader/src/fatfs/ffunicode.c
diff --git a/sw/n64/src/font.c b/sw/bootloader/src/font.c
similarity index 100%
rename from sw/n64/src/font.c
rename to sw/bootloader/src/font.c
diff --git a/sw/n64/src/font.h b/sw/bootloader/src/font.h
similarity index 100%
rename from sw/n64/src/font.h
rename to sw/bootloader/src/font.h
diff --git a/sw/n64/src/init.c b/sw/bootloader/src/init.c
similarity index 100%
rename from sw/n64/src/init.c
rename to sw/bootloader/src/init.c
diff --git a/sw/n64/src/init.h b/sw/bootloader/src/init.h
similarity index 100%
rename from sw/n64/src/init.h
rename to sw/bootloader/src/init.h
diff --git a/sw/n64/src/interrupt.c b/sw/bootloader/src/interrupt.c
similarity index 100%
rename from sw/n64/src/interrupt.c
rename to sw/bootloader/src/interrupt.c
diff --git a/sw/n64/src/io.c b/sw/bootloader/src/io.c
similarity index 100%
rename from sw/n64/src/io.c
rename to sw/bootloader/src/io.c
diff --git a/sw/n64/src/io.h b/sw/bootloader/src/io.h
similarity index 94%
rename from sw/n64/src/io.h
rename to sw/bootloader/src/io.h
index 94d7818..1f08762 100644
--- a/sw/n64/src/io.h
+++ b/sw/bootloader/src/io.h
@@ -234,9 +234,8 @@ typedef struct {
#define SC64_BASE (0x1FFF0000UL)
#define SC64 ((sc64_regs_t *) SC64_BASE)
-#define SC64_SR_CMD_ERROR (1 << 28)
-#define SC64_SR_CPU_BUSY (1 << 30)
-#define SC64_SR_CPU_READY (1 << 31)
+#define SC64_SR_CMD_ERROR (1 << 30)
+#define SC64_SR_CPU_BUSY (1 << 31)
typedef struct {
diff --git a/sw/n64/src/ipl2.S b/sw/bootloader/src/ipl2.S
similarity index 100%
rename from sw/n64/src/ipl2.S
rename to sw/bootloader/src/ipl2.S
diff --git a/sw/n64/src/main.c b/sw/bootloader/src/main.c
similarity index 100%
rename from sw/n64/src/main.c
rename to sw/bootloader/src/main.c
diff --git a/sw/n64/src/sc64.c b/sw/bootloader/src/sc64.c
similarity index 92%
rename from sw/n64/src/sc64.c
rename to sw/bootloader/src/sc64.c
index 6194561..12044a2 100644
--- a/sw/n64/src/sc64.c
+++ b/sw/bootloader/src/sc64.c
@@ -9,13 +9,6 @@ bool sc64_check_presence (void) {
return (version == SC64_VERSION_2);
}
-static void sc64_wait_cpu_ready (void) {
- uint32_t sr;
- do {
- sr = pi_io_read(&SC64->SR_CMD);
- } while (!(sr & SC64_SR_CPU_READY));
-}
-
static bool sc64_wait_cpu_busy (void) {
uint32_t sr;
do {
@@ -58,8 +51,7 @@ void sc64_get_info (sc64_info_t *info) {
void sc64_init (void) {
while (!sc64_check_presence());
- sc64_wait_cpu_ready();
- sc64_change_config(CFG_ID_SDRAM_SWITCH, true);
+ sc64_change_config(CFG_ID_BOOTLOADER_SWITCH, false);
}
void sc64_get_time (rtc_time_t *t) {
diff --git a/sw/n64/src/sc64.h b/sw/bootloader/src/sc64.h
similarity index 75%
rename from sw/n64/src/sc64.h
rename to sw/bootloader/src/sc64.h
index 8a56cb5..3f73405 100644
--- a/sw/n64/src/sc64.h
+++ b/sw/bootloader/src/sc64.h
@@ -7,40 +7,32 @@
#include "io.h"
-#define SC64_CMD_QUERY ('Q')
+#define SC64_CMD_QUERY ('c')
#define SC64_CMD_CONFIG ('C')
-#define SC64_CMD_GET_TIME (0xEE)
-#define SC64_CMD_SET_TIME (0xEF)
+#define SC64_CMD_GET_TIME ('t')
+#define SC64_CMD_SET_TIME ('T')
#define SC64_CMD_DRIVE_INIT (0xF0)
#define SC64_CMD_DRIVE_BUSY (0xF1)
#define SC64_CMD_DRIVE_READ (0xF2)
#define SC64_CMD_DRIVE_WRITE (0xF3)
#define SC64_CMD_DRIVE_LOAD (0xF4)
#define SC64_CMD_DRIVE_STORE (0xF5)
-#define SC64_CMD_UART_PUT (0xFF)
+#define SC64_CMD_UART_PUT ('U')
#define SC64_VERSION_2 (0x53437632)
typedef enum {
- CFG_ID_SCR,
- CFG_ID_SDRAM_SWITCH,
- CFG_ID_SDRAM_WRITABLE,
+ CFG_ID_BOOTLOADER_SWITCH,
+ CFG_ID_ROM_WRITE_ENABLE,
+ CFG_ID_ROM_SHADOW_ENABLE,
CFG_ID_DD_ENABLE,
+ CFG_ID_ISV_ENABLE,
+ CFG_ID_BOOT_MODE,
CFG_ID_SAVE_TYPE,
CFG_ID_CIC_SEED,
CFG_ID_TV_TYPE,
- CFG_ID_SAVE_OFFEST,
- CFG_ID_DDIPL_OFFEST,
- CFG_ID_BOOT_MODE,
- CFG_ID_FLASH_SIZE,
- CFG_ID_FLASH_READ,
- CFG_ID_FLASH_PROGRAM,
- CFG_ID_RECONFIGURE,
- CFG_ID_DD_DRIVE_ID,
- CFG_ID_DD_DISK_STATE,
- CFG_ID_DD_THB_TABLE_OFFSET,
- CFG_ID_IS_VIEWER_ENABLE,
+ CFG_ID_FLASH_ERASE_BLOCK,
} cfg_id_t;
typedef enum {
diff --git a/sw/n64/src/startup.S b/sw/bootloader/src/startup.S
similarity index 72%
rename from sw/n64/src/startup.S
rename to sw/bootloader/src/startup.S
index 2e2b41d..73f1e78 100644
--- a/sw/n64/src/startup.S
+++ b/sw/bootloader/src/startup.S
@@ -1,3 +1,6 @@
+#include "vr4300.h"
+
+
.section .text.rom_header
header_pi_config:
.word 0x80371240
@@ -32,6 +35,15 @@ entry_handler:
la $gp, _gp
la $sp, _sp
+bss_init:
+ la $a0, _sbss
+ la $a1, _ebss
+1:
+ sd $zero, 0($a0)
+ cache HIT_WRITE_BACK_D, 0($a0)
+ addiu $a0, 8
+ bltu $a0, $a1, 1b
+
la $t0, init
jalr $t0
diff --git a/sw/n64/src/storage.c b/sw/bootloader/src/storage.c
similarity index 100%
rename from sw/n64/src/storage.c
rename to sw/bootloader/src/storage.c
diff --git a/sw/n64/src/storage.h b/sw/bootloader/src/storage.h
similarity index 100%
rename from sw/n64/src/storage.h
rename to sw/bootloader/src/storage.h
diff --git a/sw/n64/src/syscalls.c b/sw/bootloader/src/syscalls.c
similarity index 73%
rename from sw/n64/src/syscalls.c
rename to sw/bootloader/src/syscalls.c
index 70c1327..10c5b3b 100644
--- a/sw/n64/src/syscalls.c
+++ b/sw/bootloader/src/syscalls.c
@@ -2,8 +2,8 @@
#include
-extern char _sheap __attribute__((section(".data")));
-extern char _eheap __attribute__((section(".data")));
+extern char _sheap;
+extern char _eheap;
caddr_t _sbrk_r (struct _reent *prt, ptrdiff_t incr) {
diff --git a/sw/n64/src/version.c b/sw/bootloader/src/version.c
similarity index 100%
rename from sw/n64/src/version.c
rename to sw/bootloader/src/version.c
diff --git a/sw/n64/src/version.h b/sw/bootloader/src/version.h
similarity index 100%
rename from sw/n64/src/version.h
rename to sw/bootloader/src/version.h
diff --git a/sw/n64/src/vr4300.h b/sw/bootloader/src/vr4300.h
similarity index 95%
rename from sw/n64/src/vr4300.h
rename to sw/bootloader/src/vr4300.h
index 93e1890..a9222d6 100644
--- a/sw/n64/src/vr4300.h
+++ b/sw/bootloader/src/vr4300.h
@@ -3,6 +3,7 @@
#define HIT_INVALIDATE_I ((4 << 2) | 0)
+#define HIT_WRITE_BACK_D ((6 << 2) | 1)
#define C0_COUNT $9
diff --git a/sw/bootloader/tools/asset_converter.py b/sw/bootloader/tools/asset_converter.py
new file mode 100644
index 0000000..67c1893
--- /dev/null
+++ b/sw/bootloader/tools/asset_converter.py
@@ -0,0 +1,31 @@
+#!/usr/bin/env python3
+
+import sys
+from PIL import Image
+
+
+
+if (len(sys.argv) != 3):
+ print(f"Usage: python {sys.argv[0]} input_path output_path")
+ exit(-1)
+
+asset_input = sys.argv[1]
+asset_output = sys.argv[2]
+
+source_asset = None
+final_asset = None
+
+try:
+ source_asset = Image.open(asset_input)
+ converted_asset = source_asset.convert("RGBA")
+ final_asset = open(asset_output, "wb")
+ final_asset.write(converted_asset.tobytes())
+except FileNotFoundError:
+ print(f"Couldn't open file \"{asset_input}\"")
+except Exception as e:
+ print(e)
+finally:
+ if (source_asset):
+ source_asset.close()
+ if (final_asset):
+ final_asset.close()
diff --git a/sw/bootloader/tools/requirements.txt b/sw/bootloader/tools/requirements.txt
new file mode 100644
index 0000000..b530339
--- /dev/null
+++ b/sw/bootloader/tools/requirements.txt
@@ -0,0 +1 @@
+Pillow>=8.4.0
diff --git a/sw/cic b/sw/cic
deleted file mode 160000
index 16fd1ee..0000000
--- a/sw/cic
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 16fd1eecd8528ab2d7fd0490f24fb7738017bd39
diff --git a/sw/controller/.gitignore b/sw/controller/.gitignore
new file mode 100644
index 0000000..5743e15
--- /dev/null
+++ b/sw/controller/.gitignore
@@ -0,0 +1,2 @@
+/build
+*.svd
diff --git a/sw/riscv/Makefile b/sw/controller/Makefile
similarity index 52%
rename from sw/riscv/Makefile
rename to sw/controller/Makefile
index 9f8ff65..2d4ea72 100644
--- a/sw/riscv/Makefile
+++ b/sw/controller/Makefile
@@ -1,12 +1,12 @@
-TOOLCHAIN = riscv32-unknown-elf-
+TOOLCHAIN = arm-none-eabi-
CC = $(TOOLCHAIN)gcc
CXX = $(TOOLCHAIN)g++
OBJCOPY = $(TOOLCHAIN)objcopy
OBJDUMP = $(TOOLCHAIN)objdump
SIZE = $(TOOLCHAIN)size
-FLAGS = -mabi=ilp32 -march=rv32i $(USER_FLAGS)
-CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -fno-delete-null-pointer-checks -MMD -MP
+FLAGS = -mcpu=cortex-m0plus -mthumb -DSTM32G030xx $(USER_FLAGS) -g -ggdb3
+CFLAGS = -Og -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP -I./lib
LDFLAGS = -nostartfiles -Wl,--gc-sections
SRC_DIR = src
@@ -14,17 +14,17 @@ BUILD_DIR = build
SRC_FILES = \
startup.S \
- process.c \
- usb.c \
cfg.c \
- joybus.c \
- rtc.c \
- i2c.c \
- flashram.c \
- uart.c \
+ cic.c \
flash.c \
- dd.c \
- isv.c
+ flashram.c \
+ fpga.c \
+ gvr.c \
+ hw.c \
+ main.c \
+ rtc.c \
+ task.c \
+ usb.c
SRCS = $(addprefix $(SRC_DIR)/, $(SRC_FILES))
OBJS = $(addprefix $(BUILD_DIR)/, $(notdir $(patsubst %,%.o,$(SRCS))))
@@ -40,23 +40,23 @@ $(BUILD_DIR)/%.S.o: %.S
$(BUILD_DIR)/%.c.o: %.c
$(CC) $(FLAGS) $(CFLAGS) -c $< -o $@
-$(BUILD_DIR)/governor.elf: $(OBJS) SC64.ld
- $(CXX) $(FLAGS) $(LDFLAGS) -TSC64.ld $(OBJS) -o $@
- @$(OBJDUMP) -D $@ > $(BUILD_DIR)/governor.lst
+$(BUILD_DIR)/controller.elf: $(OBJS) STM32G030F6Px_FLASH.ld
+ $(CXX) $(FLAGS) $(LDFLAGS) -TSTM32G030F6Px_FLASH.ld $(OBJS) -o $@
+ @$(OBJDUMP) -S -D $@ > $(BUILD_DIR)/controller.lst
-$(BUILD_DIR)/governor.bin: $(BUILD_DIR)/governor.elf
- @$(OBJCOPY) -O binary --gap-fill 0xFF --pad-to 0x00016800 $< $@
+$(BUILD_DIR)/controller.bin: $(BUILD_DIR)/controller.elf
+ @$(OBJCOPY) -O binary $< $@
-$(BUILD_DIR)/governor.hex: $(BUILD_DIR)/governor.bin
+$(BUILD_DIR)/controller.hex: $(BUILD_DIR)/controller.bin
@$(OBJCOPY) -I binary -O ihex $< $@
-print_size: $(BUILD_DIR)/governor.elf
+print_size: $(BUILD_DIR)/controller.elf
@echo 'Size of modules:'
@$(SIZE) -B -d -t --common $(OBJS)
- @echo 'Size of governor:'
+ @echo 'Size of controller:'
@$(SIZE) -B -d $<
-all: $(BUILD_DIR)/governor.hex print_size
+all: $(BUILD_DIR)/controller.hex print_size
clean:
@rm -rf ./$(BUILD_DIR)/*
diff --git a/sw/controller/STM32G030F6Px_FLASH.ld b/sw/controller/STM32G030F6Px_FLASH.ld
new file mode 100644
index 0000000..2a3edca
--- /dev/null
+++ b/sw/controller/STM32G030F6Px_FLASH.ld
@@ -0,0 +1,55 @@
+MEMORY {
+ rom (rx) : org = 0x08000000, len = 32k
+ ram (rwx) : org = 0x20000000, len = 8k
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS {
+ .isr_vector : {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector))
+ . = ALIGN(4);
+ } > rom
+
+ .text : {
+ . = ALIGN(4);
+ *(.text)
+ *(.text*)
+ *(.glue_7)
+ *(.glue_7t)
+ . = ALIGN(4);
+ _etext = .;
+ } > rom
+
+ .rodata : {
+ . = ALIGN(4);
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } > rom
+
+ .data : {
+ _sidata = LOADADDR(.data);
+ . = ALIGN(4);
+ _sdata = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN(4);
+ _edata = .;
+ } > ram AT > rom
+
+ .bss : {
+ . = ALIGN(4);
+ _sbss = .;
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ __bss_end__ = _ebss;
+ } > ram
+
+ _estack = ORIGIN(ram) + LENGTH(ram);
+}
diff --git a/sw/controller/lib/cmsis_compiler.h b/sw/controller/lib/cmsis_compiler.h
new file mode 100644
index 0000000..21a2c71
--- /dev/null
+++ b/sw/controller/lib/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/sw/controller/lib/cmsis_gcc.h b/sw/controller/lib/cmsis_gcc.h
new file mode 100644
index 0000000..1e08e7e
--- /dev/null
+++ b/sw/controller/lib/cmsis_gcc.h
@@ -0,0 +1,2168 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/sw/controller/lib/cmsis_version.h b/sw/controller/lib/cmsis_version.h
new file mode 100644
index 0000000..3174cf6
--- /dev/null
+++ b/sw/controller/lib/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.3
+ * @date 24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/sw/controller/lib/core_cm0plus.h b/sw/controller/lib/core_cm0plus.h
new file mode 100644
index 0000000..fe7b424
--- /dev/null
+++ b/sw/controller/lib/core_cm0plus.h
@@ -0,0 +1,1085 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t vectors = SCB->VTOR;
+#else
+ uint32_t vectors = 0x0U;
+#endif
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t vectors = SCB->VTOR;
+#else
+ uint32_t vectors = 0x0U;
+#endif
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/sw/controller/lib/mpu_armv7.h b/sw/controller/lib/mpu_armv7.h
new file mode 100644
index 0000000..337eb65
--- /dev/null
+++ b/sw/controller/lib/mpu_armv7.h
@@ -0,0 +1,272 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.1.0
+ * @date 08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if shareable) or 010b (if non-shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/sw/controller/lib/stm32g030xx.h b/sw/controller/lib/stm32g030xx.h
new file mode 100644
index 0000000..87131b4
--- /dev/null
+++ b/sw/controller/lib/stm32g030xx.h
@@ -0,0 +1,7335 @@
+/**
+ ******************************************************************************
+ * @file stm32g030xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32g030xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2018-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32g030xx
+ * @{
+ */
+
+#ifndef STM32G030xx_H
+#define STM32G030xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32G0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32g030xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
+/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */
+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
+ RCC_IRQn = 4, /*!< RCC global Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupts */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_stm32g0xx.h"
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
+ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
+ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
+ uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
+ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
+ uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
+ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */
+ uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+
+
+/**
+ * @brief CRC calculation unit
+ */
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED1; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */
+ __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */
+ __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */
+} DBG_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA Multiplexer
+ */
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
+ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
+ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+ * @brief Asynch Interrupt/Event Controller (EXTI)
+ */
+typedef struct
+{
+ __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
+ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
+ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
+ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
+ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
+ uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */
+ uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */
+ uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */
+ __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
+ uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */
+ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
+ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
+ __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
+ __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
+ __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
+ __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
+ uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x24--0x28 */
+ __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */
+ __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */
+ uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x34--0x38 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
+} GPIO_TypeDef;
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
+ __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
+ __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
+ __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
+ __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
+ __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
+ __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
+ __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
+ __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
+ __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
+ __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
+ __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */
+ __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */
+ __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
+ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
+ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
+ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
+ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */
+ __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */
+ __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */
+ __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */
+ __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */
+ __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */
+ __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */
+ __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */
+ __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */
+ __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */
+ __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
+ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
+ __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
+ __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */
+} RTC_TypeDef;
+
+/**
+ * @brief Tamper and backup registers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
+ __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */
+ uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */
+ __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
+ __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
+ __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */
+ __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
+ uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */
+ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
+ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
+ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
+ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
+ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
+} TAMP_TypeDef;
+
+ /**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ uint32_t RESERVED1[25]; /*!< Reserved 0x1C */
+ __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
+ __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */
+ __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */
+ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
+} USART_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
+#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
+
+#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U)
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE (PERIPH_BASE)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+
+/*!< APB peripherals */
+
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL)
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL)
+#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+
+/*!< AHB peripherals */
+#define DMA1_BASE (AHBPERIPH_BASE)
+#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+
+#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)
+#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)
+#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)
+#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)
+
+#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
+#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
+#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
+#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
+
+#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
+#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
+
+/*!< IOPORT */
+#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL)
+#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL)
+
+/*!< Device Electronic Signature */
+#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
+#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+#define ADC (ADC1_COMMON) /* Kept for legacy purpose */
+
+
+
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+
+#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+
+#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+#define DBG ((DBG_TypeDef *) DBG_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_ISR register *******************/
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos (3U)
+#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
+#define ADC_ISR_AWD1_Pos (7U)
+#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos (8U)
+#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos (9U)
+#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */
+#define ADC_ISR_CCRDY_Pos (13U)
+#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */
+#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */
+
+/* Legacy defines */
+#define ADC_ISR_EOSEQ (ADC_ISR_EOS)
+
+/******************** Bit definition for ADC_IER register *******************/
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos (3U)
+#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
+#define ADC_IER_AWD1IE_Pos (7U)
+#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos (8U)
+#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos (9U)
+#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */
+#define ADC_IER_CCRDYIE_Pos (13U)
+#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */
+#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */
+
+/* Legacy defines */
+#define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+
+/******************** Bit definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
+
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
+#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
+
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CFGR1_CHSELRMOD_Pos (21U)
+#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
+#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */
+
+#define ADC_CFGR1_AWD1SGL_Pos (22U)
+#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR1_AWD1EN_Pos (23U)
+#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+#define ADC_CFGR1_AWD1CH_Pos (26U)
+#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
+
+/* Legacy defines */
+#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
+
+/******************** Bit definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
+
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+
+#define ADC_CFGR2_LFTRIG_Pos (29U)
+#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
+#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */
+
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_SMPR register ******************/
+#define ADC_SMPR_SMP1_Pos (0U)
+#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */
+#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR_SMP2_Pos (4U)
+#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */
+#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */
+#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */
+#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */
+#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */
+
+#define ADC_SMPR_SMPSEL_Pos (8U)
+#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */
+#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */
+#define ADC_SMPR_SMPSEL0_Pos (8U)
+#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */
+#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR_SMPSEL1_Pos (9U)
+#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */
+#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR_SMPSEL2_Pos (10U)
+#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */
+#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR_SMPSEL3_Pos (11U)
+#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR_SMPSEL4_Pos (12U)
+#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR_SMPSEL5_Pos (13U)
+#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */
+#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR_SMPSEL6_Pos (14U)
+#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */
+#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR_SMPSEL7_Pos (15U)
+#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */
+#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR_SMPSEL8_Pos (16U)
+#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */
+#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR_SMPSEL9_Pos (17U)
+#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */
+#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR_SMPSEL10_Pos (18U)
+#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */
+#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR_SMPSEL11_Pos (19U)
+#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */
+#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR_SMPSEL12_Pos (20U)
+#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */
+#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR_SMPSEL13_Pos (21U)
+#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */
+#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR_SMPSEL14_Pos (22U)
+#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */
+#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR_SMPSEL15_Pos (23U)
+#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */
+#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR_SMPSEL16_Pos (24U)
+#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */
+#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR_SMPSEL17_Pos (25U)
+#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
+#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR_SMPSEL18_Pos (26U)
+#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
+#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */
+
+/******************** Bit definition for ADC_TR1 register *******************/
+#define ADC_TR1_LT1_Pos (0U)
+#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
+#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
+#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
+#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
+#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
+#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
+#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
+#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
+#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
+#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
+#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
+#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
+#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos (16U)
+#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
+#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
+#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
+#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
+#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
+#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
+#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
+#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
+#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
+#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
+#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
+#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_TR2 register *******************/
+#define ADC_TR2_LT2_Pos (0U)
+#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */
+#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
+#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
+#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
+#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
+#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
+#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
+#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
+#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
+#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */
+#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */
+#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */
+#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */
+
+#define ADC_TR2_HT2_Pos (16U)
+#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
+#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
+#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
+#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
+#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
+#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
+#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
+#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
+#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */
+#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */
+#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */
+#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_CHSELR register ****************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL16_Pos (16U)
+#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
+
+#define ADC_CHSELR_SQ_ALL_Pos (0U)
+#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
+
+#define ADC_CHSELR_SQ8_Pos (28U)
+#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */
+#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */
+#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */
+#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */
+#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */
+
+#define ADC_CHSELR_SQ7_Pos (24U)
+#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */
+#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */
+#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */
+#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */
+#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */
+
+#define ADC_CHSELR_SQ6_Pos (20U)
+#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */
+#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */
+#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */
+#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */
+#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */
+
+#define ADC_CHSELR_SQ5_Pos (16U)
+#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */
+#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */
+
+#define ADC_CHSELR_SQ4_Pos (12U)
+#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */
+#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */
+
+#define ADC_CHSELR_SQ3_Pos (8U)
+#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */
+#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */
+
+#define ADC_CHSELR_SQ2_Pos (4U)
+#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */
+#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */
+
+#define ADC_CHSELR_SQ1_Pos (0U)
+#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */
+#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
+#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
+
+/******************** Bit definition for ADC_TR3 register *******************/
+#define ADC_TR3_LT3_Pos (0U)
+#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */
+#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
+#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
+#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
+#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
+#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
+#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
+#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
+#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
+#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */
+#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */
+#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */
+#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */
+
+#define ADC_TR3_HT3_Pos (16U)
+#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
+#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
+#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
+#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
+#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
+#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
+#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
+#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
+#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */
+#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */
+#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */
+#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */
+#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */
+#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */
+#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */
+#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */
+#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */
+#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */
+#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */
+#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */
+#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */
+#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */
+#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */
+#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */
+#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */
+#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */
+#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_AWD2CR register ****************/
+#define ADC_AWD2CR_AWD2CH_Pos (0U)
+#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_AWD3CR register ****************/
+#define ADC_AWD3CR_AWD3CH_Pos (0U)
+#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_CALFACT register ***************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC_CCR register *******************/
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos (24U)
+#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
+
+/* Legacy */
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
+
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* DMAMUX Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMAMUX_CxCR register **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */
+#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
+#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
+#define DMAMUX_CxCR_SOIE_Pos (8U)
+#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
+#define DMAMUX_CxCR_EGE_Pos (9U)
+#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */
+#define DMAMUX_CxCR_SE_Pos (16U)
+#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
+#define DMAMUX_CxCR_SPOL_Pos (17U)
+#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
+#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
+#define DMAMUX_CxCR_NBREQ_Pos (19U)
+#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */
+#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
+#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */
+#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
+
+/******************* Bits definition for DMAMUX_CSR register **************/
+#define DMAMUX_CSR_SOF0_Pos (0U)
+#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */
+#define DMAMUX_CSR_SOF1_Pos (1U)
+#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */
+#define DMAMUX_CSR_SOF2_Pos (2U)
+#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */
+#define DMAMUX_CSR_SOF3_Pos (3U)
+#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */
+#define DMAMUX_CSR_SOF4_Pos (4U)
+#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */
+#define DMAMUX_CSR_SOF5_Pos (5U)
+#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */
+#define DMAMUX_CSR_SOF6_Pos (6U)
+#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */
+
+/******************** Bits definition for DMAMUX_CFR register **************/
+#define DMAMUX_CFR_CSOF0_Pos (0U)
+#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */
+#define DMAMUX_CFR_CSOF1_Pos (1U)
+#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */
+#define DMAMUX_CFR_CSOF2_Pos (2U)
+#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */
+#define DMAMUX_CFR_CSOF3_Pos (3U)
+#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */
+#define DMAMUX_CFR_CSOF4_Pos (4U)
+#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */
+#define DMAMUX_CFR_CSOF5_Pos (5U)
+#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */
+#define DMAMUX_CFR_CSOF6_Pos (6U)
+#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */
+
+/******************** Bits definition for DMAMUX_RGxCR register ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */
+#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
+#define DMAMUX_RGxCR_OIE_Pos (8U)
+#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */
+#define DMAMUX_RGxCR_GE_Pos (16U)
+#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */
+#define DMAMUX_RGxCR_GPOL_Pos (17U)
+#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */
+#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
+#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */
+#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
+
+/******************** Bits definition for DMAMUX_RGSR register **************/
+#define DMAMUX_RGSR_OF0_Pos (0U)
+#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */
+#define DMAMUX_RGSR_OF1_Pos (1U)
+#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */
+#define DMAMUX_RGSR_OF2_Pos (2U)
+#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */
+#define DMAMUX_RGSR_OF3_Pos (3U)
+#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */
+
+/******************** Bits definition for DMAMUX_RGCFR register **************/
+#define DMAMUX_RGCFR_COF0_Pos (0U)
+#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */
+#define DMAMUX_RGCFR_COF1_Pos (1U)
+#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */
+#define DMAMUX_RGCFR_COF2_Pos (2U)
+#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */
+#define DMAMUX_RGCFR_COF3_Pos (3U)
+#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for EXTI_RTSR1 register ******************/
+#define EXTI_RTSR1_RT0_Pos (0U)
+#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */
+#define EXTI_RTSR1_RT1_Pos (1U)
+#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */
+#define EXTI_RTSR1_RT2_Pos (2U)
+#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */
+#define EXTI_RTSR1_RT3_Pos (3U)
+#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */
+#define EXTI_RTSR1_RT4_Pos (4U)
+#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */
+#define EXTI_RTSR1_RT5_Pos (5U)
+#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */
+#define EXTI_RTSR1_RT6_Pos (6U)
+#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */
+#define EXTI_RTSR1_RT7_Pos (7U)
+#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */
+#define EXTI_RTSR1_RT8_Pos (8U)
+#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */
+#define EXTI_RTSR1_RT9_Pos (9U)
+#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */
+#define EXTI_RTSR1_RT10_Pos (10U)
+#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */
+#define EXTI_RTSR1_RT11_Pos (11U)
+#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */
+#define EXTI_RTSR1_RT12_Pos (12U)
+#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */
+#define EXTI_RTSR1_RT13_Pos (13U)
+#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */
+#define EXTI_RTSR1_RT14_Pos (14U)
+#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */
+#define EXTI_RTSR1_RT15_Pos (15U)
+#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */
+
+/****************** Bit definition for EXTI_FTSR1 register ******************/
+#define EXTI_FTSR1_FT0_Pos (0U)
+#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */
+#define EXTI_FTSR1_FT1_Pos (1U)
+#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */
+#define EXTI_FTSR1_FT2_Pos (2U)
+#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */
+#define EXTI_FTSR1_FT3_Pos (3U)
+#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */
+#define EXTI_FTSR1_FT4_Pos (4U)
+#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */
+#define EXTI_FTSR1_FT5_Pos (5U)
+#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */
+#define EXTI_FTSR1_FT6_Pos (6U)
+#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */
+#define EXTI_FTSR1_FT7_Pos (7U)
+#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */
+#define EXTI_FTSR1_FT8_Pos (8U)
+#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */
+#define EXTI_FTSR1_FT9_Pos (9U)
+#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */
+#define EXTI_FTSR1_FT10_Pos (10U)
+#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */
+#define EXTI_FTSR1_FT11_Pos (11U)
+#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */
+#define EXTI_FTSR1_FT12_Pos (12U)
+#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */
+#define EXTI_FTSR1_FT13_Pos (13U)
+#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */
+#define EXTI_FTSR1_FT14_Pos (14U)
+#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */
+#define EXTI_FTSR1_FT15_Pos (15U)
+#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */
+
+/****************** Bit definition for EXTI_SWIER1 register *****************/
+#define EXTI_SWIER1_SWI0_Pos (0U)
+#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos (1U)
+#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos (2U)
+#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos (3U)
+#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos (4U)
+#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos (5U)
+#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos (6U)
+#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos (7U)
+#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos (8U)
+#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos (9U)
+#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos (10U)
+#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos (11U)
+#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos (12U)
+#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos (13U)
+#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos (14U)
+#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos (15U)
+#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
+
+/******************* Bit definition for EXTI_RPR1 register ******************/
+#define EXTI_RPR1_RPIF0_Pos (0U)
+#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */
+#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
+#define EXTI_RPR1_RPIF1_Pos (1U)
+#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */
+#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
+#define EXTI_RPR1_RPIF2_Pos (2U)
+#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */
+#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
+#define EXTI_RPR1_RPIF3_Pos (3U)
+#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */
+#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
+#define EXTI_RPR1_RPIF4_Pos (4U)
+#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */
+#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */
+#define EXTI_RPR1_RPIF5_Pos (5U)
+#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */
+#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */
+#define EXTI_RPR1_RPIF6_Pos (6U)
+#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */
+#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */
+#define EXTI_RPR1_RPIF7_Pos (7U)
+#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */
+#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */
+#define EXTI_RPR1_RPIF8_Pos (8U)
+#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */
+#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */
+#define EXTI_RPR1_RPIF9_Pos (9U)
+#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */
+#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */
+#define EXTI_RPR1_RPIF10_Pos (10U)
+#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */
+#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */
+#define EXTI_RPR1_RPIF11_Pos (11U)
+#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */
+#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */
+#define EXTI_RPR1_RPIF12_Pos (12U)
+#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */
+#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */
+#define EXTI_RPR1_RPIF13_Pos (13U)
+#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */
+#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */
+#define EXTI_RPR1_RPIF14_Pos (14U)
+#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */
+#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */
+#define EXTI_RPR1_RPIF15_Pos (15U)
+#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
+#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
+
+/******************* Bit definition for EXTI_FPR1 register ******************/
+#define EXTI_FPR1_FPIF0_Pos (0U)
+#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
+#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */
+#define EXTI_FPR1_FPIF1_Pos (1U)
+#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */
+#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */
+#define EXTI_FPR1_FPIF2_Pos (2U)
+#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */
+#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */
+#define EXTI_FPR1_FPIF3_Pos (3U)
+#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */
+#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */
+#define EXTI_FPR1_FPIF4_Pos (4U)
+#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */
+#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */
+#define EXTI_FPR1_FPIF5_Pos (5U)
+#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */
+#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */
+#define EXTI_FPR1_FPIF6_Pos (6U)
+#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */
+#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */
+#define EXTI_FPR1_FPIF7_Pos (7U)
+#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */
+#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */
+#define EXTI_FPR1_FPIF8_Pos (8U)
+#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */
+#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */
+#define EXTI_FPR1_FPIF9_Pos (9U)
+#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */
+#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */
+#define EXTI_FPR1_FPIF10_Pos (10U)
+#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */
+#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */
+#define EXTI_FPR1_FPIF11_Pos (11U)
+#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */
+#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */
+#define EXTI_FPR1_FPIF12_Pos (12U)
+#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */
+#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */
+#define EXTI_FPR1_FPIF13_Pos (13U)
+#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */
+#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */
+#define EXTI_FPR1_FPIF14_Pos (14U)
+#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */
+#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */
+#define EXTI_FPR1_FPIF15_Pos (15U)
+#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */
+#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */
+
+/***************** Bit definition for EXTI_EXTICR1 register **************/
+#define EXTI_EXTICR1_EXTI0_Pos (0U)
+#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
+#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */
+#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */
+#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */
+#define EXTI_EXTICR1_EXTI1_Pos (8U)
+#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */
+#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */
+#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR1_EXTI2_Pos (16U)
+#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */
+#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */
+#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */
+#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */
+#define EXTI_EXTICR1_EXTI3_Pos (24U)
+#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */
+#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */
+#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */
+#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */
+
+/***************** Bit definition for EXTI_EXTICR2 register **************/
+#define EXTI_EXTICR2_EXTI4_Pos (0U)
+#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
+#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */
+#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */
+#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */
+#define EXTI_EXTICR2_EXTI5_Pos (8U)
+#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */
+#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */
+#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR2_EXTI6_Pos (16U)
+#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */
+#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */
+#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */
+#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */
+#define EXTI_EXTICR2_EXTI7_Pos (24U)
+#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */
+#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */
+#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */
+#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */
+
+/***************** Bit definition for EXTI_EXTICR3 register **************/
+#define EXTI_EXTICR3_EXTI8_Pos (0U)
+#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
+#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */
+#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */
+#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */
+#define EXTI_EXTICR3_EXTI9_Pos (8U)
+#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */
+#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */
+#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR3_EXTI10_Pos (16U)
+#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */
+#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */
+#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */
+#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */
+#define EXTI_EXTICR3_EXTI11_Pos (24U)
+#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */
+#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */
+#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */
+#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */
+
+/***************** Bit definition for EXTI_EXTICR4 register **************/
+#define EXTI_EXTICR4_EXTI12_Pos (0U)
+#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
+#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */
+#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */
+#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */
+#define EXTI_EXTICR4_EXTI13_Pos (8U)
+#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */
+#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
+#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR4_EXTI14_Pos (16U)
+#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */
+#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */
+#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */
+#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */
+#define EXTI_EXTICR4_EXTI15_Pos (24U)
+#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */
+#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */
+#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */
+#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
+
+/******************* Bit definition for EXTI_IMR1 register ******************/
+#define EXTI_IMR1_IM0_Pos (0U)
+#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos (1U)
+#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos (2U)
+#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos (3U)
+#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos (4U)
+#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos (5U)
+#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos (6U)
+#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos (7U)
+#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos (8U)
+#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos (9U)
+#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos (10U)
+#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos (11U)
+#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos (12U)
+#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos (13U)
+#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos (14U)
+#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos (15U)
+#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM19_Pos (19U)
+#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM21_Pos (21U)
+#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM23_Pos (23U)
+#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM25_Pos (25U)
+#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM31_Pos (31U)
+#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
+#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos (0U)
+#define EXTI_IMR1_IM_Msk (0x82A8FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x82A8FFFF */
+#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
+
+
+/******************* Bit definition for EXTI_EMR1 register ******************/
+#define EXTI_EMR1_EM0_Pos (0U)
+#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos (1U)
+#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos (2U)
+#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos (3U)
+#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos (4U)
+#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos (5U)
+#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos (6U)
+#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos (7U)
+#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos (8U)
+#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos (9U)
+#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos (10U)
+#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos (11U)
+#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos (12U)
+#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos (13U)
+#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos (14U)
+#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos (15U)
+#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM19_Pos (19U)
+#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM21_Pos (21U)
+#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM23_Pos (23U)
+#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM25_Pos (25U)
+#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM31_Pos (31U)
+#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
+#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
+
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/* Note: No specific macro feature on this device */
+
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_PROGEMPTY_Pos (16U)
+#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */
+#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_OPERR_Pos (1U)
+#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
+#define FLASH_SR_PROGERR_Pos (3U)
+#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
+#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_SIZERR_Pos (6U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_MISERR_Pos (8U)
+#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
+#define FLASH_SR_FASTERR_Pos (9U)
+#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
+#define FLASH_SR_OPTVERR_Pos (15U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
+#define FLASH_SR_BSY1_Pos (16U)
+#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk
+#define FLASH_SR_CFGBSY_Pos (18U)
+#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */
+#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk
+#define FLASH_CR_MER1_Pos (2U)
+#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
+#define FLASH_CR_PNB_Pos (3U)
+#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_PNB FLASH_CR_PNB_Msk
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_OPTSTRT_Pos (17U)
+#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
+#define FLASH_CR_FSTPG_Pos (18U)
+#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
+#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_ERRIE_Pos (25U)
+#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
+#define FLASH_CR_OBL_LAUNCH_Pos (27U)
+#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
+#define FLASH_CR_OPTLOCK_Pos (30U)
+#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_ECCR register ****************/
+#define FLASH_ECCR_ADDR_ECC_Pos (0U)
+#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
+#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
+#define FLASH_ECCR_SYSF_ECC_Pos (20U)
+#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
+#define FLASH_ECCR_ECCCIE_Pos (24U)
+#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
+#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
+#define FLASH_ECCR_ECCC_Pos (30U)
+#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
+#define FLASH_ECCR_ECCD_Pos (31U)
+#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
+
+/******************* Bits definition for FLASH_OPTR register ****************/
+#define FLASH_OPTR_RDP_Pos (0U)
+#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
+#define FLASH_OPTR_nRST_STOP_Pos (13U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
+#define FLASH_OPTR_nRST_STDBY_Pos (14U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
+#define FLASH_OPTR_IWDG_SW_Pos (16U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
+#define FLASH_OPTR_IWDG_STOP_Pos (17U)
+#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
+#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
+#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
+#define FLASH_OPTR_WWDG_SW_Pos (19U)
+#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
+#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
+#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
+#define FLASH_OPTR_nBOOT_SEL_Pos (24U)
+#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
+#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
+#define FLASH_OPTR_nBOOT1_Pos (25U)
+#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
+#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
+#define FLASH_OPTR_nBOOT0_Pos (26U)
+#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
+#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
+
+/****************** Bits definition for FLASH_WRP1AR register ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
+#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */
+#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
+#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
+#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */
+#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
+
+/****************** Bits definition for FLASH_WRP1BR register ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
+#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */
+#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
+#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
+#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */
+#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
+
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos (13U)
+#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */
+#define RTC_ICSR_ALRBWF_Pos (1U)
+#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
+#define RTC_ICSR_ALRAWF_Pos (0U)
+#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_OUT2EN_Pos (31U)
+#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
+#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */
+#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
+#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
+#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */
+#define RTC_CR_TAMPALRM_PU_Pos (29U)
+#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
+#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */
+#define RTC_CR_TAMPOE_Pos (26U)
+#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
+#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */
+#define RTC_CR_TAMPTS_Pos (25U)
+#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
+#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */
+#define RTC_CR_ITSE_Pos (24U)
+#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_SR register *******************/
+#define RTC_SR_ITSF_Pos (5U)
+#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
+#define RTC_SR_ITSF RTC_SR_ITSF_Msk
+#define RTC_SR_TSOVF_Pos (4U)
+#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
+#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */
+#define RTC_SR_TSF_Pos (3U)
+#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
+#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */
+#define RTC_SR_WUTF_Pos (2U)
+#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
+#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */
+#define RTC_SR_ALRBF_Pos (1U)
+#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
+#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
+#define RTC_SR_ALRAF_Pos (0U)
+#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
+#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
+
+/******************** Bits definition for RTC_MISR register *****************/
+#define RTC_MISR_ITSMF_Pos (5U)
+#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
+#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
+#define RTC_MISR_TSOVMF_Pos (4U)
+#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
+#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */
+#define RTC_MISR_TSMF_Pos (3U)
+#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
+#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */
+#define RTC_MISR_WUTMF_Pos (2U)
+#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
+#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */
+#define RTC_MISR_ALRBMF_Pos (1U)
+#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
+#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
+#define RTC_MISR_ALRAMF_Pos (0U)
+#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
+#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
+
+/******************** Bits definition for RTC_SCR register ******************/
+#define RTC_SCR_CITSF_Pos (5U)
+#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
+#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
+#define RTC_SCR_CTSOVF_Pos (4U)
+#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
+#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */
+#define RTC_SCR_CTSF_Pos (3U)
+#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
+#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */
+#define RTC_SCR_CWUTF_Pos (2U)
+#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
+#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */
+#define RTC_SCR_CALRBF_Pos (1U)
+#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
+#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
+#define RTC_SCR_CALRAF_Pos (0U)
+#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
+#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
+
+/******************************************************************************/
+/* */
+/* Tamper and backup register (TAMP) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for TAMP_CR1 register *****************/
+#define TAMP_CR1_TAMP1E_Pos (0U)
+#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
+#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
+#define TAMP_CR1_TAMP2E_Pos (1U)
+#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
+#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
+#define TAMP_CR1_ITAMP3E_Pos (18U)
+#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
+#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
+#define TAMP_CR1_ITAMP4E_Pos (19U)
+#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
+#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
+#define TAMP_CR1_ITAMP5E_Pos (20U)
+#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
+#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
+#define TAMP_CR1_ITAMP6E_Pos (21U)
+#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
+#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
+
+/******************** Bits definition for TAMP_CR2 register *****************/
+#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
+#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
+#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
+#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
+#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
+#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
+#define TAMP_CR2_TAMP1MSK_Pos (16U)
+#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP2MSK_Pos (17U)
+#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP1TRG_Pos (24U)
+#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
+#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
+#define TAMP_CR2_TAMP2TRG_Pos (25U)
+#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
+#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
+
+/******************** Bits definition for TAMP_FLTCR register ***************/
+#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U
+#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U
+#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U
+#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
+#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
+#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
+#define TAMP_FLTCR_TAMPFLT_0 0x00000008U
+#define TAMP_FLTCR_TAMPFLT_1 0x00000010U
+#define TAMP_FLTCR_TAMPFLT_Pos (3U)
+#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
+#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
+#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U
+#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U
+#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
+#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
+#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
+#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
+#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
+#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
+
+/******************** Bits definition for TAMP_IER register *****************/
+#define TAMP_IER_TAMP1IE_Pos (0U)
+#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
+#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
+#define TAMP_IER_TAMP2IE_Pos (1U)
+#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
+#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
+#define TAMP_IER_ITAMP3IE_Pos (18U)
+#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
+#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
+#define TAMP_IER_ITAMP4IE_Pos (19U)
+#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
+#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
+#define TAMP_IER_ITAMP5IE_Pos (20U)
+#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
+#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
+#define TAMP_IER_ITAMP6IE_Pos (21U)
+#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
+#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
+
+/******************** Bits definition for TAMP_SR register ******************/
+#define TAMP_SR_TAMP1F_Pos (0U)
+#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
+#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
+#define TAMP_SR_TAMP2F_Pos (1U)
+#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
+#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
+#define TAMP_SR_ITAMP3F_Pos (18U)
+#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
+#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
+#define TAMP_SR_ITAMP4F_Pos (19U)
+#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
+#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
+#define TAMP_SR_ITAMP5F_Pos (20U)
+#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
+#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
+#define TAMP_SR_ITAMP6F_Pos (21U)
+#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
+#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
+
+/******************** Bits definition for TAMP_MISR register ****************/
+#define TAMP_MISR_TAMP1MF_Pos (0U)
+#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
+#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
+#define TAMP_MISR_TAMP2MF_Pos (1U)
+#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
+#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
+#define TAMP_MISR_ITAMP3MF_Pos (18U)
+#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
+#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
+#define TAMP_MISR_ITAMP4MF_Pos (19U)
+#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
+#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
+#define TAMP_MISR_ITAMP5MF_Pos (20U)
+#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
+#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
+#define TAMP_MISR_ITAMP6MF_Pos (21U)
+#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
+#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
+
+/******************** Bits definition for TAMP_SCR register *****************/
+#define TAMP_SCR_CTAMP1F_Pos (0U)
+#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
+#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
+#define TAMP_SCR_CTAMP2F_Pos (1U)
+#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
+#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
+#define TAMP_SCR_CITAMP3F_Pos (18U)
+#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
+#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
+#define TAMP_SCR_CITAMP4F_Pos (19U)
+#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
+#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
+#define TAMP_SCR_CITAMP5F_Pos (20U)
+#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
+#define TAMP_SCR_CITAMP6F_Pos (21U)
+#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
+#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
+
+/******************** Bits definition for TAMP_BKP0R register ***************/
+#define TAMP_BKP0R_Pos (0U)
+#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP0R TAMP_BKP0R_Msk
+
+/******************** Bits definition for TAMP_BKP1R register ***************/
+#define TAMP_BKP1R_Pos (0U)
+#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP1R TAMP_BKP1R_Msk
+
+/******************** Bits definition for TAMP_BKP2R register ***************/
+#define TAMP_BKP2R_Pos (0U)
+#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP2R TAMP_BKP2R_Msk
+
+/******************** Bits definition for TAMP_BKP3R register ***************/
+#define TAMP_BKP3R_Pos (0U)
+#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP3R TAMP_BKP3R_Msk
+
+/******************** Bits definition for TAMP_BKP4R register ***************/
+#define TAMP_BKP4R_Pos (0U)
+#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP4R TAMP_BKP4R_Msk
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32G0 series)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[21] interrupt */
+#define SYSCFG_ITLINE2_SR_RTC_Pos (1U)
+#define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */
+#define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */
+#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U)
+#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */
+#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U)
+#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */
+#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */
+#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U)
+#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */
+#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)
+#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */
+#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U)
+#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
+#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */
+#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U)
+#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */
+#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U)
+#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
+#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */
+#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U)
+#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */
+#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U)
+#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
+#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */
+#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U)
+#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
+#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */
+#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U)
+#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
+#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */
+#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U)
+#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
+#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */
+#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U)
+#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
+#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */
+#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U)
+#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
+#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */
+#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U)
+#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
+#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */
+#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U)
+#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
+#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */
+#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U)
+#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
+#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */
+#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U)
+#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
+#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */
+#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U)
+#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
+#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */
+#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U)
+#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U)
+#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
+#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
+#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
+#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)
+#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
+#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U)
+#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */
+#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */
+#define SYSCFG_ITLINE12_SR_ADC_Pos (0U)
+#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U)
+#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U)
+#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */
+#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U)
+#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */
+#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U)
+#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */
+#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */
+#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U)
+#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */
+#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U)
+#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */
+#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U)
+#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */
+#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U)
+#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */
+#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U)
+#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */
+#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U)
+#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */
+#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U)
+#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt -> exti[22]*/
+#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U)
+#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */
+#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U)
+#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */
+#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)
+#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
+#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)
+#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
+#include "cfg.h"
+#include "flash.h"
+#include "fpga.h"
+#include "rtc.h"
+
+
+typedef enum {
+ CFG_ID_BOOTLOADER_SWITCH,
+ CFG_ID_ROM_WRITE_ENABLE,
+ CFG_ID_ROM_SHADOW_ENABLE,
+ CFG_ID_DD_ENABLE,
+ CFG_ID_ISV_ENABLE,
+ CFG_ID_BOOT_MODE,
+ CFG_ID_SAVE_TYPE,
+ CFG_ID_CIC_SEED,
+ CFG_ID_TV_TYPE,
+ CFG_ID_FLASH_ERASE_BLOCK,
+} cfg_id_t;
+
+typedef enum {
+ SAVE_TYPE_NONE = 0,
+ SAVE_TYPE_EEPROM_4K = 1,
+ SAVE_TYPE_EEPROM_16K = 2,
+ SAVE_TYPE_SRAM = 3,
+ SAVE_TYPE_FLASHRAM = 4,
+ SAVE_TYPE_SRAM_BANKED = 5
+} save_type_t;
+
+typedef enum {
+ BOOT_MODE_MENU_SD = 0,
+ BOOT_MODE_MENU_USB = 1,
+ BOOT_MODE_ROM = 2,
+ BOOT_MODE_DD = 3,
+ BOOT_MODE_DIRECT = 4
+} boot_mode_t;
+
+
+struct process {
+ boot_mode_t boot_mode;
+ save_type_t save_type;
+ uint16_t cic_seed;
+ uint8_t tv_type;
+};
+
+static struct process p;
+
+
+static void change_scr_bits (uint32_t mask, bool value) {
+ if (value) {
+ fpga_reg_set(REG_CFG_SCR, fpga_reg_get(REG_CFG_SCR) | mask);
+ } else {
+ fpga_reg_set(REG_CFG_SCR, fpga_reg_get(REG_CFG_SCR) & (~mask));
+ }
+}
+
+static void set_save_type (save_type_t save_type) {
+ uint32_t save_reset_mask = (
+ CFG_SCR_EEPROM_16K |
+ CFG_SCR_EEPROM_ENABLED |
+ CFG_SCR_FLASHRAM_ENABLED |
+ CFG_SCR_SRAM_BANKED |
+ CFG_SCR_SRAM_ENABLED
+ );
+
+ change_scr_bits(save_reset_mask, false);
+
+ switch (save_type) {
+ case SAVE_TYPE_NONE:
+ break;
+ case SAVE_TYPE_EEPROM_4K:
+ change_scr_bits(CFG_SCR_EEPROM_ENABLED, true);
+ break;
+ case SAVE_TYPE_EEPROM_16K:
+ change_scr_bits(CFG_SCR_EEPROM_16K | CFG_SCR_EEPROM_ENABLED, true);
+ break;
+ case SAVE_TYPE_SRAM:
+ change_scr_bits(CFG_SCR_SRAM_ENABLED, true);
+ break;
+ case SAVE_TYPE_FLASHRAM:
+ change_scr_bits(CFG_SCR_FLASHRAM_ENABLED, true);
+ break;
+ case SAVE_TYPE_SRAM_BANKED:
+ change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_ENABLED, true);
+ break;
+ default:
+ save_type = SAVE_TYPE_NONE;
+ break;
+ }
+
+ p.save_type = save_type;
+}
+
+
+uint32_t cfg_get_version (void) {
+ return fpga_reg_get(REG_CFG_VERSION);
+}
+
+void cfg_query (uint32_t *args) {
+ switch (args[0]) {
+ case CFG_ID_BOOTLOADER_SWITCH:
+ args[1] = (fpga_reg_get(REG_CFG_SCR) & CFG_SCR_BOOTLOADER_ENABLED);
+ break;
+ case CFG_ID_ROM_WRITE_ENABLE:
+ args[1] = (fpga_reg_get(REG_CFG_SCR) & CFG_SCR_ROM_WRITE_ENABLED);
+ break;
+ case CFG_ID_ROM_SHADOW_ENABLE:
+ args[1] = (fpga_reg_get(REG_CFG_SCR) & CFG_SCR_ROM_SHADOW_ENABLED);
+ break;
+ case CFG_ID_DD_ENABLE:
+ args[1] = (fpga_reg_get(REG_CFG_SCR) & CFG_SCR_DD_ENABLED);
+ break;
+ case CFG_ID_ISV_ENABLE:
+ break;
+ case CFG_ID_BOOT_MODE:
+ args[1] = p.boot_mode;
+ break;
+ case CFG_ID_SAVE_TYPE:
+ args[1] = p.save_type;
+ break;
+ case CFG_ID_CIC_SEED:
+ args[1] = p.cic_seed;
+ break;
+ case CFG_ID_TV_TYPE:
+ args[1] = p.tv_type;
+ break;
+ case CFG_ID_FLASH_ERASE_BLOCK:
+ break;
+ }
+}
+
+void cfg_update (uint32_t *args) {
+ switch (args[0]) {
+ case CFG_ID_BOOTLOADER_SWITCH:
+ change_scr_bits(CFG_SCR_BOOTLOADER_ENABLED, args[1]);
+ break;
+ case CFG_ID_ROM_WRITE_ENABLE:
+ change_scr_bits(CFG_SCR_ROM_WRITE_ENABLED, args[1]);
+ break;
+ case CFG_ID_ROM_SHADOW_ENABLE:
+ change_scr_bits(CFG_SCR_ROM_SHADOW_ENABLED, args[1]);
+ break;
+ case CFG_ID_DD_ENABLE:
+ change_scr_bits(CFG_SCR_DD_ENABLED, args[1]);
+ break;
+ case CFG_ID_ISV_ENABLE:
+ break;
+ case CFG_ID_BOOT_MODE:
+ p.boot_mode = args[1];
+ change_scr_bits(CFG_SCR_BOOTLOADER_SKIP, (args[1] == BOOT_MODE_DIRECT));
+ break;
+ case CFG_ID_SAVE_TYPE:
+ set_save_type((save_type_t) (args[1]));
+ break;
+ case CFG_ID_CIC_SEED:
+ p.cic_seed = (uint16_t) (args[1] & 0xFFFF);
+ break;
+ case CFG_ID_TV_TYPE:
+ p.tv_type = (uint8_t) (args[1] & 0x03);
+ break;
+ case CFG_ID_FLASH_ERASE_BLOCK:
+ flash_erase_block(args[1]);
+ break;
+ }
+}
+
+void cfg_get_time (uint32_t *args) {
+ rtc_time_t t;
+ rtc_get_time(&t);
+ args[0] = ((t.hour << 16) | (t.minute << 8) | t.second);
+ args[1] = ((t.weekday << 24) | (t.year << 16) | (t.month << 8) | t.day);
+}
+
+void cfg_set_time (uint32_t *args) {
+ rtc_time_t t;
+ t.second = (args[0] & 0xFF);
+ t.minute = ((args[0] >> 8) & 0xFF);
+ t.hour = ((args[0] >> 16) & 0xFF);
+ t.weekday = ((args[1] >> 24) & 0xFF);
+ t.day = (args[1] & 0xFF);
+ t.month = ((args[1] >> 8) & 0xFF);
+ t.year = ((args[1] >> 16) & 0xFF);
+ rtc_set_time(&t);
+}
+
+
+void cfg_init (void) {
+ // fpga_reg_set(REG_CFG_SCR, 0);
+ set_save_type(SAVE_TYPE_NONE);
+
+ p.cic_seed = 0xFFFF;
+ p.tv_type = 0x03;
+ p.boot_mode = BOOT_MODE_MENU_SD;
+}
+
+#include "stm32g030xx.h"
+
+void uart_print (const char *str) {
+ while (*str != '\0') {
+ while (!(USART1->ISR & USART_ISR_TXE_TXFNF));
+ USART1->TDR = *str++;
+ }
+}
+
+void cfg_process (void) {
+ uint32_t args[2];
+
+ if (fpga_reg_get(REG_STATUS) & STATUS_CFG_PENDING) {
+ args[0] = fpga_reg_get(REG_CFG_DATA_0);
+ args[1] = fpga_reg_get(REG_CFG_DATA_1);
+ char cmd = (char) fpga_reg_get(REG_CFG_CMD);
+ uart_print("GOT_CMD");
+ char tmp[2] = {cmd, 0};
+ uart_print(tmp);
+ uart_print("\n");
+ switch (cmd) {
+ case 'v':
+ args[0] = cfg_get_version();
+ break;
+
+ case 'c':
+ cfg_query(args);
+ break;
+
+ case 'C':
+ cfg_update(args);
+ break;
+
+ case 't':
+ cfg_get_time(args);
+ break;
+
+ case 'T':
+ cfg_set_time(args);
+ break;
+
+ case 'U':
+ // uart_put((char) (args[0] & 0xFF));
+ break;
+
+ default:
+ fpga_reg_set(REG_CFG_CMD, CFG_CMD_ERROR | CFG_CMD_DONE);
+ return;
+ }
+
+ fpga_reg_set(REG_CFG_DATA_0, args[0]);
+ fpga_reg_set(REG_CFG_DATA_1, args[1]);
+ fpga_reg_set(REG_CFG_CMD, CFG_CMD_DONE);
+ }
+}
diff --git a/sw/riscv/src/cfg.h b/sw/controller/src/cfg.h
similarity index 79%
rename from sw/riscv/src/cfg.h
rename to sw/controller/src/cfg.h
index 3a20cbf..8fa4b28 100644
--- a/sw/riscv/src/cfg.h
+++ b/sw/controller/src/cfg.h
@@ -2,7 +2,7 @@
#define CFG_H__
-#include "sys.h"
+#include
uint32_t cfg_get_version (void);
@@ -11,7 +11,7 @@ void cfg_update (uint32_t *args);
void cfg_get_time (uint32_t *args);
void cfg_set_time (uint32_t *args);
void cfg_init (void);
-void process_cfg (void);
+void cfg_process (void);
#endif
diff --git a/sw/controller/src/cic.c b/sw/controller/src/cic.c
new file mode 100644
index 0000000..42bfe9d
--- /dev/null
+++ b/sw/controller/src/cic.c
@@ -0,0 +1,359 @@
+#include "cic.h"
+#include "hw.h"
+#include "rtc.h"
+#include "task.h"
+
+
+typedef enum {
+ REGION_NTSC,
+ REGION_PAL,
+ __REGION_MAX
+} cic_region_t;
+
+
+static volatile bool cic_enabled = false;
+
+static volatile uint8_t cic_next_rd;
+static volatile uint8_t cic_next_wr;
+
+static volatile bool cic_dd_mode = false;
+static volatile uint8_t cic_seed = 0x3F;
+static volatile uint8_t cic_checksum[6] = { 0xA5, 0x36, 0xC0, 0xF1, 0xD8, 0x59 };
+
+static uint8_t cic_ram[32];
+static uint8_t cic_x105_ram[30];
+
+static const uint8_t cic_ram_init[2][32] = {{
+ 0x0E, 0x00, 0x09, 0x0A, 0x01, 0x08, 0x05, 0x0A, 0x01, 0x03, 0x0E, 0x01, 0x00, 0x0D, 0x0E, 0x0C,
+ 0x00, 0x0B, 0x01, 0x04, 0x0F, 0x08, 0x0B, 0x05, 0x07, 0x0C, 0x0D, 0x06, 0x01, 0x0E, 0x09, 0x08
+}, {
+ 0x0E, 0x00, 0x04, 0x0F, 0x05, 0x01, 0x02, 0x01, 0x07, 0x01, 0x09, 0x08, 0x05, 0x07, 0x05, 0x0A,
+ 0x00, 0x0B, 0x01, 0x02, 0x03, 0x0F, 0x08, 0x02, 0x07, 0x01, 0x09, 0x08, 0x01, 0x01, 0x05, 0x0C
+}};
+
+
+static void cic_irq_reset_falling (void) {
+ cic_enabled = false;
+ hw_gpio_set(GPIO_ID_N64_CIC_DQ);
+}
+
+static void cic_irq_reset_rising (void) {
+ cic_enabled = true;
+ task_set_ready_and_reset(TASK_ID_CIC);
+}
+
+static void cic_irq_clk_falling (void) {
+ if (cic_enabled) {
+ if (!cic_next_wr) {
+ hw_gpio_reset(GPIO_ID_N64_CIC_DQ);
+ }
+ cic_next_rd = hw_gpio_get(GPIO_ID_N64_CIC_DQ) ? 1 : 0;
+ task_set_ready(TASK_ID_CIC);
+ }
+}
+
+static void cic_irq_clk_rising (void) {
+ hw_gpio_set(GPIO_ID_N64_CIC_DQ);
+}
+
+static uint8_t cic_read (void) {
+ cic_next_wr = 1;
+ task_yield();
+ return cic_next_rd;
+}
+
+static void cic_write (uint8_t bit) {
+ cic_next_wr = bit;
+ task_yield();
+}
+
+static uint8_t cic_read_nibble (void) {
+ uint8_t data = 0;
+ for (int i = 0; i < 4; i++) {
+ data = ((data << 1) | cic_read());
+ }
+ return data;
+}
+
+static void cic_write_nibble (uint8_t data) {
+ cic_write(data & 0x08);
+ cic_write(data & 0x04);
+ cic_write(data & 0x02);
+ cic_write(data & 0x01);
+}
+
+static void cic_write_ram_nibbles (uint8_t index) {
+ do {
+ cic_write_nibble(cic_ram[index++]);
+ } while ((index & 0x0F) != 0);
+}
+
+static void cic_encode_round (uint8_t index) {
+ uint8_t data = cic_ram[index++];
+ do {
+ data = ((((data + 1) & 0x0F) + cic_ram[index]) & 0x0F);
+ cic_ram[index++] = data;
+ } while ((index & 0x0F) != 0);
+}
+
+static void cic_write_id (cic_region_t region) {
+ uint8_t id = 0x01;
+
+ if (cic_dd_mode) {
+ id |= 0x08;
+ }
+
+ if (region == REGION_PAL) {
+ id |= 0x04;
+ }
+
+ cic_write_nibble(id);
+}
+
+static void cic_write_id_failed (void) {
+ uint8_t current_region = rtc_get_region();
+ uint8_t next_region = (current_region == REGION_NTSC) ? REGION_PAL : REGION_NTSC;
+ rtc_set_region(next_region);
+ // TODO: blink some error code
+}
+
+static void cic_write_seed (void) {
+ cic_ram[0x0A] = 0x0B;
+ cic_ram[0x0B] = 0x05;
+ cic_ram[0x0C] = (cic_seed >> 4);
+ cic_ram[0x0D] = cic_seed;
+ cic_ram[0x0E] = (cic_seed >> 4);
+ cic_ram[0x0F] = cic_seed;
+ cic_encode_round(0x0A);
+ cic_encode_round(0x0A);
+ cic_write_ram_nibbles(0x0A);
+}
+
+static void cic_write_checksum (void) {
+ for (int i = 0; i < 4; i++) {
+ cic_ram[i] = 0x00;
+ }
+ for (int i = 0; i < 6; i++) {
+ cic_ram[(i * 2) + 4] = ((cic_checksum[i] >> 4) & 0x0F);
+ cic_ram[(i * 2) + 5] = (cic_checksum[i] & 0x0F);
+ }
+ cic_encode_round(0x00);
+ cic_encode_round(0x00);
+ cic_encode_round(0x00);
+ cic_encode_round(0x00);
+ cic_write(0);
+ cic_write_ram_nibbles(0x00);
+}
+
+static void cic_init_ram (cic_region_t region) {
+ if (region < __REGION_MAX) {
+ for (int i = 0; i < 32; i++) {
+ cic_ram[i] = cic_ram_init[region][i];
+ }
+ }
+ cic_ram[0x01] = cic_read_nibble();
+ cic_ram[0x11] = cic_read_nibble();
+}
+
+static void cic_exchange_bytes (uint8_t *a, uint8_t *b) {
+ uint8_t tmp = *a;
+ *a = *b;
+ *b = tmp;
+}
+
+static void cic_round (uint8_t *m) {
+ uint8_t a, b, x;
+
+ x = m[15];
+ a = x;
+
+ do {
+ b = 1;
+ a += (m[b] + 1);
+ m[b] = a;
+ b++;
+ a += (m[b] + 1);
+ cic_exchange_bytes(&a, &m[b]);
+ m[b] = ~(m[b]);
+ b++;
+ a &= 0x0F;
+ a += ((m[b] & 0x0F) + 1);
+ if (a < 16) {
+ cic_exchange_bytes(&a, &m[b]);
+ b++;
+ }
+ a += m[b];
+ m[b] = a;
+ b++;
+ a += m[b];
+ cic_exchange_bytes(&a, &m[b]);
+ b++;
+ a &= 0x0F;
+ a += 8;
+ if (a < 16) {
+ a += m[b];
+ }
+ cic_exchange_bytes(&a, &m[b]);
+ b++;
+ do {
+ a += (m[b] + 1);
+ m[b] = a;
+ b++;
+ b &= 0x0F;
+ } while (b != 0);
+ a = (x + 0x0F);
+ x = (a & 0x0F);
+ } while (x != 0x0F);
+}
+
+static void cic_compare_mode (cic_region_t region) {
+ cic_round(&cic_ram[0x10]);
+ cic_round(&cic_ram[0x10]);
+ cic_round(&cic_ram[0x10]);
+
+ uint8_t index = (cic_ram[0x17] & 0x0F);
+ if (index == 0) {
+ index = 1;
+ }
+ index |= 0x10;
+
+ do {
+ cic_read();
+ cic_write(cic_ram[index] & 0x01);
+ if (region == REGION_PAL) {
+ index--;
+ } else {
+ index++;
+ }
+ } while (index & 0x0F);
+}
+
+static void cic_x105_algorithm (void) {
+ uint8_t a = 5;
+ uint8_t carry = 1;
+
+ for (int i = 0; i < 30; ++i) {
+ if (!(cic_x105_ram[i] & 0x01)) {
+ a += 8;
+ }
+ if (!(a & 0x02)) {
+ a += 4;
+ }
+ a = ((a + cic_x105_ram[i]) & 0x0F);
+ cic_x105_ram[i] = a;
+ if (!carry) {
+ a += 7;
+ }
+ a = ((a + cic_x105_ram[i]) & 0x0F);
+ a = (a + cic_x105_ram[i] + carry);
+ if (a >= 0x10) {
+ carry = 1;
+ a -= 0x10;
+ } else {
+ carry = 0;
+ }
+ a = (~(a) & 0x0F);
+ cic_x105_ram[i] = a;
+ }
+}
+
+static void cic_x105_mode (void) {
+ cic_write_nibble(0x0A);
+ cic_write_nibble(0x0A);
+
+ for (int i = 0; i < 30; i++) {
+ cic_x105_ram[i] = cic_read_nibble();
+ }
+
+ cic_x105_algorithm();
+
+ cic_write(0);
+
+ for (int i = 0; i < 30; i++) {
+ cic_write_nibble(cic_x105_ram[i]);
+ }
+}
+
+static void cic_soft_reset_timeout (void) {
+ hw_gpio_reset(GPIO_ID_N64_CIC_DQ);
+ task_set_ready(TASK_ID_CIC);
+}
+
+static void cic_soft_reset (void) {
+ cic_read();
+ hw_tim_setup(TIM_ID_CIC, 550, cic_soft_reset_timeout);
+ task_yield();
+}
+
+void cic_set_dd_mode (bool enabled) {
+ cic_dd_mode = enabled;
+}
+
+void cic_set_seed (uint8_t seed) {
+ cic_seed = seed;
+}
+
+void cic_set_checksum (uint8_t *checksum) {
+ for (int i = 0; i < 6; i++) {
+ cic_checksum[i] = checksum[i];
+ }
+}
+
+void cic_hw_init (void) {
+ hw_gpio_irq_setup(GPIO_ID_N64_RESET, GPIO_IRQ_FALLING, cic_irq_reset_falling);
+ hw_gpio_irq_setup(GPIO_ID_N64_RESET, GPIO_IRQ_RISING, cic_irq_reset_rising);
+ hw_gpio_irq_setup(GPIO_ID_N64_CIC_CLK, GPIO_IRQ_FALLING, cic_irq_clk_falling);
+ hw_gpio_irq_setup(GPIO_ID_N64_CIC_CLK, GPIO_IRQ_RISING, cic_irq_clk_rising);
+}
+
+void cic_task (void) {
+ while (!hw_gpio_get(GPIO_ID_N64_RESET)) {
+ task_yield();
+ }
+
+ cic_region_t region = rtc_get_region();
+ if (region >= __REGION_MAX) {
+ region = REGION_NTSC;
+ rtc_set_region(region);
+ }
+
+ cic_write_id(region);
+
+ hw_tim_setup(TIM_ID_CIC, 1000, cic_write_id_failed);
+ cic_write_seed();
+ hw_tim_stop(TIM_ID_CIC);
+
+ cic_write_checksum();
+ cic_init_ram(region);
+
+ while(1) {
+ uint8_t cmd = 0;
+ cmd |= (cic_read() << 1);
+ cmd |= cic_read();
+
+ switch (cmd) {
+ case 0: {
+ cic_compare_mode(region);
+ break;
+ }
+
+ case 2: {
+ cic_x105_mode();
+ break;
+ }
+
+ case 3: {
+ cic_soft_reset();
+ break;
+ }
+
+ case 1:
+ default: {
+ while (1) {
+ task_yield();
+ }
+ break;
+ }
+ }
+ }
+}
diff --git a/sw/controller/src/cic.h b/sw/controller/src/cic.h
new file mode 100644
index 0000000..66031f8
--- /dev/null
+++ b/sw/controller/src/cic.h
@@ -0,0 +1,16 @@
+#ifndef CIC_H__
+#define CIC_H__
+
+
+#include
+#include
+
+
+void cic_set_dd_mode (bool enabled);
+void cic_set_seed (uint8_t seed);
+void cic_set_checksum (uint8_t *checksum);
+void cic_hw_init (void);
+void cic_task (void);
+
+
+#endif
diff --git a/sw/controller/src/flash.c b/sw/controller/src/flash.c
new file mode 100644
index 0000000..9144689
--- /dev/null
+++ b/sw/controller/src/flash.c
@@ -0,0 +1,11 @@
+#include "flash.h"
+#include "fpga.h"
+
+
+void flash_erase_block (uint32_t offset) {
+ uint8_t dummy[2];
+
+ while (fpga_reg_get(REG_FLASH_SCR) & FLASH_SCR_BUSY);
+ fpga_reg_set(REG_FLASH_SCR, offset);
+ fpga_mem_read(offset, 2, dummy);
+}
diff --git a/sw/controller/src/flash.h b/sw/controller/src/flash.h
new file mode 100644
index 0000000..8b7fa7e
--- /dev/null
+++ b/sw/controller/src/flash.h
@@ -0,0 +1,11 @@
+#ifndef FLASH_H__
+#define FLASH_H__
+
+
+#include
+
+
+void flash_erase_block (uint32_t offset);
+
+
+#endif
diff --git a/sw/controller/src/flashram.c b/sw/controller/src/flashram.c
new file mode 100644
index 0000000..04d5407
--- /dev/null
+++ b/sw/controller/src/flashram.c
@@ -0,0 +1,71 @@
+#include
+#include
+#include "fpga.h"
+
+
+#define FLASHRAM_SIZE (128 * 1024)
+#define FLASHRAM_SECTOR_SIZE (16 * 1024)
+#define FLASHRAM_PAGE_SIZE (128)
+
+enum operation {
+ OP_NONE,
+ OP_ERASE_ALL,
+ OP_ERASE_SECTOR,
+ OP_WRITE_PAGE
+};
+
+
+static enum operation flashram_operation_type (uint32_t scr) {
+ if (!(scr & FLASHRAM_SCR_PENDING)) {
+ return OP_NONE;
+ }
+
+ if (scr & FLASHRAM_SCR_WRITE_OR_ERASE) {
+ if (scr & FLASHRAM_SCR_SECTOR_OR_ALL) {
+ return OP_ERASE_ALL;
+ } else {
+ return OP_ERASE_SECTOR;
+ }
+ } else {
+ return OP_WRITE_PAGE;
+ }
+}
+
+
+void flashram_init (void) {
+ fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE);
+}
+
+
+void flashram_process (void) {
+ uint32_t scr = fpga_reg_get(REG_FLASHRAM_SCR);
+ enum operation op = flashram_operation_type(scr);
+ uint8_t buffer[FLASHRAM_PAGE_SIZE];
+ uint32_t address = (64 * 1024 * 1024) - (256 * 1024);
+ uint32_t erase_size = (op == OP_ERASE_SECTOR) ? FLASHRAM_SECTOR_SIZE : FLASHRAM_SIZE;
+ uint32_t sector = (op != OP_ERASE_ALL) ? ((scr & FLASHRAM_SCR_PAGE_MASK) >> FLASHRAM_SCR_PAGE_BIT) : 0;
+ address += sector * FLASHRAM_PAGE_SIZE;
+
+ switch (op) {
+ case OP_ERASE_ALL:
+ case OP_ERASE_SECTOR:
+ for (int i = 0; i < FLASHRAM_PAGE_SIZE; i++) {
+ buffer[i] = 0xFF;
+ }
+ for (int i = 0; i < erase_size; i += FLASHRAM_PAGE_SIZE) {
+ fpga_mem_write(address + i, FLASHRAM_PAGE_SIZE, buffer);
+ }
+ fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE);
+ break;
+
+ case OP_WRITE_PAGE:
+ fpga_flashram_buffer_read(buffer);
+ fpga_mem_write(address, FLASHRAM_PAGE_SIZE, buffer);
+ fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE);
+ break;
+
+ case OP_NONE:
+ default:
+ break;
+ }
+}
diff --git a/sw/riscv/src/flashram.h b/sw/controller/src/flashram.h
similarity index 67%
rename from sw/riscv/src/flashram.h
rename to sw/controller/src/flashram.h
index 4cd8425..4fdb24d 100644
--- a/sw/riscv/src/flashram.h
+++ b/sw/controller/src/flashram.h
@@ -3,7 +3,7 @@
void flashram_init (void);
-void process_flashram (void);
+void flashram_process (void);
#endif
diff --git a/sw/controller/src/fpga.c b/sw/controller/src/fpga.c
new file mode 100644
index 0000000..87bd7ea
--- /dev/null
+++ b/sw/controller/src/fpga.c
@@ -0,0 +1,134 @@
+#include "fpga.h"
+#include "hw.h"
+
+
+uint8_t fpga_id_get (void) {
+ fpga_cmd_t cmd = CMD_IDENTIFY;
+ uint8_t id;
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&id, 1, SPI_RX);
+ hw_spi_stop();
+
+ return id;
+}
+
+uint32_t fpga_reg_get (fpga_reg_t reg) {
+ fpga_cmd_t cmd = CMD_REG_READ;
+ uint32_t value;
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(®, 1, SPI_TX);
+ hw_spi_trx((uint8_t *) (&value), 4, SPI_RX);
+ hw_spi_stop();
+
+ return value;
+}
+
+void fpga_reg_set (fpga_reg_t reg, uint32_t value) {
+ fpga_cmd_t cmd = CMD_REG_WRITE;
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(®, 1, SPI_TX);
+ hw_spi_trx((uint8_t *) (&value), 4, SPI_TX);
+ hw_spi_stop();
+}
+
+void fpga_mem_read (uint32_t address, size_t length, uint8_t *buffer) {
+ fpga_cmd_t cmd = CMD_MEM_READ;
+ uint8_t buffer_address = 0;
+
+ fpga_reg_set(REG_MEM_ADDRESS, address);
+ fpga_reg_set(REG_MEM_SCR, (length << MEM_SCR_LENGTH_BIT) | MEM_SCR_START);
+ while (fpga_reg_get(REG_MEM_SCR) & MEM_SCR_BUSY);
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&buffer_address, 1, SPI_TX);
+ hw_spi_trx(buffer, length, SPI_RX);
+ hw_spi_stop();
+}
+
+void fpga_mem_write (uint32_t address, size_t length, uint8_t *buffer) {
+ fpga_cmd_t cmd = CMD_MEM_WRITE;
+ uint8_t buffer_address = 0;
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&buffer_address, 1, SPI_TX);
+ hw_spi_trx(buffer, length, SPI_TX);
+ hw_spi_stop();
+
+ fpga_reg_set(REG_MEM_ADDRESS, address);
+ fpga_reg_set(REG_MEM_SCR, (length << MEM_SCR_LENGTH_BIT) | MEM_SCR_DIRECTION | MEM_SCR_START);
+ while (fpga_reg_get(REG_MEM_SCR) & MEM_SCR_BUSY);
+}
+
+uint8_t fpga_usb_status_get (void) {
+ fpga_cmd_t cmd = CMD_USB_STATUS;
+ uint8_t status;
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&status, 1, SPI_RX);
+ hw_spi_stop();
+
+ return status;
+}
+
+uint8_t fpga_usb_pop (void) {
+ fpga_cmd_t cmd = CMD_USB_READ;
+ uint8_t data;
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&data, 1, SPI_RX);
+ hw_spi_stop();
+
+ return data;
+}
+
+void fpga_usb_push (uint8_t data) {
+ fpga_cmd_t cmd = CMD_USB_WRITE;
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&data, 1, SPI_TX);
+ hw_spi_stop();
+}
+
+void fpga_flashram_buffer_read (uint8_t *buffer) {
+ fpga_cmd_t cmd = CMD_FLASHRAM_READ;
+ uint8_t address = 0;
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&address, 1, SPI_TX);
+ hw_spi_trx(buffer, 128, SPI_RX);
+ hw_spi_stop();
+}
+
+void fpga_eeprom_read (uint16_t address, size_t length, uint8_t *buffer) {
+ fpga_cmd_t cmd = CMD_EEPROM_READ;
+ uint8_t adjusted_address = ((address >> 3) & 0xFF);
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&adjusted_address, 1, SPI_TX);
+ hw_spi_trx(buffer, length, SPI_RX);
+ hw_spi_stop();
+}
+
+void fpga_eeprom_write (uint16_t address, size_t length, uint8_t *buffer) {
+ fpga_cmd_t cmd = CMD_EEPROM_WRITE;
+ uint8_t adjusted_address = ((address >> 3) & 0xFF);
+
+ hw_spi_start();
+ hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX);
+ hw_spi_trx(&adjusted_address, 1, SPI_TX);
+ hw_spi_trx(buffer, length, SPI_TX);
+ hw_spi_stop();
+}
diff --git a/sw/controller/src/fpga.h b/sw/controller/src/fpga.h
new file mode 100644
index 0000000..8842c45
--- /dev/null
+++ b/sw/controller/src/fpga.h
@@ -0,0 +1,134 @@
+#ifndef FPGA_H__
+#define FPGA_H__
+
+
+#include
+#include
+
+
+typedef enum {
+ CMD_IDENTIFY,
+ CMD_REG_READ,
+ CMD_REG_WRITE,
+ CMD_MEM_READ,
+ CMD_MEM_WRITE,
+ CMD_USB_STATUS,
+ CMD_USB_READ,
+ CMD_USB_WRITE,
+ CMD_FLASHRAM_READ,
+ CMD_EEPROM_READ,
+ CMD_EEPROM_WRITE
+} fpga_cmd_t;
+
+typedef enum {
+ REG_STATUS,
+ REG_MEM_ADDRESS,
+ REG_MEM_SCR,
+ REG_USB_SCR,
+ REG_USB_DMA_ADDRESS,
+ REG_USB_DMA_LENGTH,
+ REG_USB_DMA_SCR,
+ REG_CFG_SCR,
+ REG_CFG_DATA_0,
+ REG_CFG_DATA_1,
+ REG_CFG_CMD,
+ REG_CFG_VERSION,
+ REG_FLASHRAM_SCR,
+ REG_FLASH_SCR,
+ REG_RTC_SCR,
+ REG_RTC_TIME_0,
+ REG_RTC_TIME_1,
+ REG_SD_SCR,
+ REG_SD_ARG,
+ REG_SD_CMD,
+ REG_SD_RSP_0,
+ REG_SD_RSP_1,
+ REG_SD_RSP_2,
+ REG_SD_RSP_3,
+ REG_SD_DAT,
+ REG_SD_DMA_ADDRESS,
+ REG_SD_DMA_LENGTH,
+ REG_SD_DMA_SCR,
+} fpga_reg_t;
+
+
+#define FPGA_ID (0x64)
+
+#define FPGA_MAX_MEM_TRANSFER (1024)
+
+#define MEM_SCR_START (1 << 0)
+#define MEM_SCR_STOP (1 << 1)
+#define MEM_SCR_DIRECTION (1 << 2)
+#define MEM_SCR_BUSY (1 << 3)
+#define MEM_SCR_LENGTH_BIT (4)
+
+#define USB_STATUS_RXNE (1 << 0)
+#define USB_STATUS_TXE (1 << 1)
+
+#define STATUS_BUTTON (1 << 0)
+#define STATUS_USB_RESET_PENDING (1 << 1)
+#define STATUS_DMA_BUSY (1 << 2)
+#define STATUS_CFG_PENDING (1 << 3)
+#define STATUS_FLASHRAM_PENDING (1 << 4)
+#define STATUS_USB_RXNE (1 << 5)
+#define STATUS_USB_TXE (1 << 6)
+
+#define USB_SCR_FIFO_FLUSH (1 << 0)
+#define USB_SCR_RXNE (1 << 1)
+#define USB_SCR_TXE (1 << 2)
+#define USB_SCR_RESET_PENDING (1 << 3)
+#define USB_SCR_RESET_ACK (1 << 4)
+#define USB_SCR_WRITE_FLUSH (1 << 5)
+
+#define DMA_SCR_START (1 << 0)
+#define DMA_SCR_STOP (1 << 1)
+#define DMA_SCR_DIRECTION (1 << 2)
+#define DMA_SCR_BUSY (1 << 3)
+
+#define CFG_SCR_BOOTLOADER_ENABLED (1 << 0)
+#define CFG_SCR_BOOTLOADER_SKIP (1 << 1)
+#define CFG_SCR_ROM_WRITE_ENABLED (1 << 2)
+#define CFG_SCR_ROM_SHADOW_ENABLED (1 << 3)
+#define CFG_SCR_SRAM_ENABLED (1 << 4)
+#define CFG_SCR_SRAM_BANKED (1 << 5)
+#define CFG_SCR_FLASHRAM_ENABLED (1 << 6)
+#define CFG_SCR_DD_ENABLED (1 << 7)
+#define CFG_SCR_EEPROM_ENABLED (1 << 8)
+#define CFG_SCR_EEPROM_16K (1 << 9)
+
+#define CFG_CMD_DONE (1 << 0)
+#define CFG_CMD_ERROR (1 << 1)
+#define CFG_CMD_IRQ (1 << 2)
+
+#define FLASHRAM_SCR_DONE (1 << 0)
+#define FLASHRAM_SCR_PENDING (1 << 1)
+#define FLASHRAM_SCR_PAGE_BIT (2)
+#define FLASHRAM_SCR_PAGE_MASK (0x3FF << FLASHRAM_SCR_PAGE_BIT)
+#define FLASHRAM_SCR_SECTOR_OR_ALL (1 << 12)
+#define FLASHRAM_SCR_WRITE_OR_ERASE (1 << 13)
+
+#define FLASH_SCR_BUSY (1 << 0)
+
+#define RTC_SCR_PENDING (1 << 0)
+#define RTC_SCR_DONE (1 << 1)
+
+#define SD_SCR_CLOCK_MODE_OFF (0 << 0)
+#define SD_SCR_CLOCK_MODE_400KHZ (1 << 0)
+#define SD_SCR_CLOCK_MODE_25MHZ (2 << 0)
+#define SD_SCR_CLOCK_MODE_50MHZ (3 << 0)
+
+
+uint8_t fpga_id_get (void);
+uint32_t fpga_reg_get (fpga_reg_t reg);
+void fpga_reg_set (fpga_reg_t reg, uint32_t value);
+void fpga_mem_read (uint32_t address, size_t length, uint8_t *buffer);
+void fpga_mem_write (uint32_t address, size_t length, uint8_t *buffer);
+uint8_t fpga_usb_status_get (void);
+uint8_t fpga_usb_pop (void);
+void fpga_usb_push (uint8_t data);
+void fpga_flashram_buffer_read (uint8_t *buffer);
+void fpga_eeprom_read (uint16_t address, size_t length, uint8_t *buffer);
+void fpga_eeprom_write (uint16_t address, size_t length, uint8_t *buffer);
+
+
+#endif
diff --git a/sw/controller/src/gvr.c b/sw/controller/src/gvr.c
new file mode 100644
index 0000000..184c0eb
--- /dev/null
+++ b/sw/controller/src/gvr.c
@@ -0,0 +1,57 @@
+#include "cfg.h"
+#include "flashram.h"
+#include "fpga.h"
+#include "rtc.h"
+#include "usb.h"
+
+
+void gvr_task (void) {
+ while (fpga_id_get() != FPGA_ID);
+
+ cfg_init();
+ flashram_init();
+ usb_init();
+
+ // fpga_reg_set(REG_SD_SCR, SD_SCR_CLOCK_MODE_25MHZ);
+
+ while (1) {
+ cfg_process();
+ flashram_process();
+ usb_process();
+ rtc_process();
+ }
+}
+
+
+// while (1) {
+// while (fpga_reg_get(REG_STATUS) & STATUS_BUTTON);
+// fpga_reg_set(REG_FLASH_SCR, 0x00E00000UL);
+// while (!(fpga_reg_get(REG_STATUS) & STATUS_BUTTON));
+// }
+
+// if (!(fpga_reg_get(REG_STATUS) & STATUS_BUTTON)) {
+// hw_gpio_set(GPIO_ID_LED);
+// fpga_reg_set(REG_FLASH_SCR, FLASH_SCR_ERASE_MODE);
+// for (int i = 0; i < ((2*1024)-128)*1024; i += 64*1024) {
+// fpga_mem_write(((64+14)*1024*1024) + i, 2, buffer);
+// }
+// fpga_reg_set(REG_FLASH_SCR, 0);
+// fpga_mem_read((64+14)*1024*1024, 2, buffer);
+// hw_gpio_reset(GPIO_ID_LED);
+// }
+// fpga_reg_set(REG_CFG_SCR, 0); //CFG_SCR_BOOTLOADER_ENABLED
+
+// uint8_t buffer[2];
+
+// fpga_mem_read(0*1024*1024, 16, buffer);
+// fpga_mem_read(64*1024*1024, 16, buffer);
+// fpga_mem_read(64*1024*1024 + 128, 16, buffer);
+// buffer[0] = 0x21;
+// buffer[1] = 0x37;
+// buffer[2] = 0x69;
+// buffer[3] = 0x42;
+// fpga_mem_write(((64 + 16)*1024*1024)-(128 * 1024), 4, buffer);
+// fpga_mem_read(((64 + 16)*1024*1024)-(128 * 1024)-8, 16, buffer);
+
+
+
diff --git a/sw/controller/src/gvr.h b/sw/controller/src/gvr.h
new file mode 100644
index 0000000..2a782d1
--- /dev/null
+++ b/sw/controller/src/gvr.h
@@ -0,0 +1,8 @@
+#ifndef GVR_H__
+#define GVR_H__
+
+
+void gvr_task (void);
+
+
+#endif
diff --git a/sw/controller/src/hw.c b/sw/controller/src/hw.c
new file mode 100644
index 0000000..db5f8e7
--- /dev/null
+++ b/sw/controller/src/hw.c
@@ -0,0 +1,445 @@
+#include
+#include "hw.h"
+
+
+typedef enum {
+ GPIO_INPUT = 0b00,
+ GPIO_OUTPUT = 0b01,
+ GPIO_ALT = 0b10,
+ GPIO_ANALOG = 0b11
+} gpio_mode_t;
+
+typedef enum {
+ GPIO_PP = 0b0,
+ GPIO_OD = 0b1
+} gpio_ot_t;
+
+typedef enum {
+ GPIO_SPEED_VLOW = 0b00,
+ GPIO_SPEED_LOW = 0b01,
+ GPIO_SPEED_HIGH = 0b10,
+ GPIO_SPEED_VHIGH = 0b11
+} gpio_ospeed_t;
+
+typedef enum {
+ GPIO_PULL_NONE = 0b00,
+ GPIO_PULL_UP = 0b01,
+ GPIO_PULL_DOWN = 0b10
+} gpio_pupd_t;
+
+typedef enum {
+ GPIO_AF_0 = 0x00,
+ GPIO_AF_1 = 0x01,
+ GPIO_AF_2 = 0x02,
+ GPIO_AF_3 = 0x03,
+ GPIO_AF_4 = 0x04,
+ GPIO_AF_5 = 0x05,
+ GPIO_AF_6 = 0x06,
+ GPIO_AF_7 = 0x07
+} gpio_af_t;
+
+typedef struct {
+ void (*volatile falling)(void);
+ void (*volatile rising)(void);
+} gpio_irq_callback_t;
+
+
+static const GPIO_TypeDef *gpios[] = { GPIOA, GPIOB };
+static gpio_irq_callback_t gpio_irq_callbacks[16];
+
+static volatile uint8_t *i2c_data_txptr;
+static volatile uint8_t *i2c_data_rxptr;
+static volatile uint32_t i2c_next_cr2;
+static void (*volatile i2c_callback)(void);
+
+static const TIM_TypeDef *tims[] = { TIM14, TIM16, TIM17 };
+static void (*volatile tim_callbacks[3])(void);
+
+
+void hw_gpio_init (gpio_id_t id, gpio_mode_t mode, gpio_ot_t ot, gpio_ospeed_t ospeed, gpio_pupd_t pupd, gpio_af_t af, int value) {
+ GPIO_TypeDef tmp;
+ GPIO_TypeDef *gpio = ((GPIO_TypeDef *) (gpios[(id >> 4) & 0x07]));
+ uint8_t pin = (id & 0x0F);
+ uint8_t afr = ((pin < 8) ? 0 : 1);
+
+ if (!gpio) {
+ return;
+ }
+
+ tmp.MODER = (gpio->MODER & ~(GPIO_MODER_MODE0_Msk << (pin * 2)));
+ tmp.OTYPER = (gpio->OTYPER & ~(GPIO_OTYPER_OT0_Msk << pin));
+ tmp.OSPEEDR = (gpio->OSPEEDR & ~(GPIO_OSPEEDR_OSPEED0_Msk << (pin * 2)));
+ tmp.PUPDR = (gpio->PUPDR & ~(GPIO_PUPDR_PUPD0_Msk << (pin * 2)));
+ tmp.AFR[afr] = (gpio->AFR[afr] & ~(GPIO_AFRL_AFSEL0_Msk << ((pin - (afr * 8)) * 4)));
+
+ gpio->MODER |= (GPIO_MODER_MODE0_Msk << (pin * 2));
+ gpio->OTYPER = (tmp.OTYPER | (ot << pin));
+ gpio->OSPEEDR = (tmp.OSPEEDR | (ospeed << (pin * 2)));
+ gpio->PUPDR = (tmp.PUPDR | (pupd << (pin * 2)));
+ gpio->AFR[afr] = (tmp.AFR[afr] | (af << ((pin - (afr * 8)) * 4)));
+ gpio->BSRR = ((value ? GPIO_BSRR_BS0 : GPIO_BSRR_BR0) << pin);
+ gpio->MODER = (tmp.MODER | (mode << (pin * 2)));
+}
+
+void hw_gpio_irq_setup (gpio_id_t id, gpio_irq_t irq, void (*callback)(void)) {
+ uint8_t port = ((id >> 4) & 0x0F);
+ uint8_t pin = (id & 0x0F);
+ if (irq == GPIO_IRQ_FALLING) {
+ EXTI->FTSR1 |= (EXTI_FTSR1_FT0 << pin);
+ gpio_irq_callbacks[pin].falling = callback;
+ } else {
+ EXTI->RTSR1 |= (EXTI_RTSR1_RT0 << pin);
+ gpio_irq_callbacks[pin].rising = callback;
+ }
+ EXTI->EXTICR[pin / 4] |= (port << (8 * (pin % 4)));
+ EXTI->IMR1 |= (EXTI_IMR1_IM0 << pin);
+}
+
+uint32_t hw_gpio_get (gpio_id_t id) {
+ GPIO_TypeDef *gpio = ((GPIO_TypeDef *) (gpios[(id >> 4) & 0x07]));
+ uint8_t pin = (id & 0x0F);
+ return gpio->IDR & (GPIO_IDR_ID0 << pin);
+}
+
+void hw_gpio_set (gpio_id_t id) {
+ GPIO_TypeDef *gpio = ((GPIO_TypeDef *) (gpios[(id >> 4) & 0x07]));
+ uint8_t pin = (id & 0x0F);
+ gpio->BSRR = (GPIO_BSRR_BS0 << pin);
+}
+
+void hw_gpio_reset (gpio_id_t id) {
+ GPIO_TypeDef *gpio = ((GPIO_TypeDef *) (gpios[(id >> 4) & 0x07]));
+ uint8_t pin = (id & 0x0F);
+ gpio->BSRR = (GPIO_BSRR_BR0 << pin);
+}
+
+void hw_spi_start (void) {
+ hw_gpio_reset(GPIO_ID_SPI_CS);
+}
+
+void hw_spi_stop (void) {
+ while (SPI1->SR & SPI_SR_BSY);
+ hw_gpio_set(GPIO_ID_SPI_CS);
+}
+
+void hw_spi_trx (uint8_t *data, int length, spi_direction_t direction) {
+ volatile uint8_t dummy __attribute__((unused));
+
+ DMA1_Channel1->CNDTR = length;
+ DMA1_Channel2->CNDTR = length;
+
+ if (direction == SPI_TX) {
+ DMA1_Channel1->CMAR = (uint32_t) (&dummy);
+ DMA1_Channel1->CCR = DMA_CCR_EN;
+
+ DMA1_Channel2->CMAR = (uint32_t) (data);
+ DMA1_Channel2->CCR = (DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_EN);
+ } else {
+ DMA1_Channel1->CMAR = (uint32_t) (data);
+ DMA1_Channel1->CCR = (DMA_CCR_MINC | DMA_CCR_EN);
+
+ DMA1_Channel2->CMAR = (uint32_t) (&dummy);
+ DMA1_Channel2->CCR = (DMA_CCR_DIR | DMA_CCR_EN);
+ }
+
+ while (DMA1_Channel1->CNDTR || DMA1_Channel2->CNDTR);
+
+ DMA1_Channel1->CCR = 0;
+ DMA1_Channel2->CCR = 0;
+}
+
+void hw_i2c_read (uint8_t i2c_address, uint8_t address, uint8_t *data, uint8_t length, void (*callback)(void)) {
+ i2c_data_rxptr = data;
+ i2c_callback = callback;
+ I2C1->TXDR = address;
+ i2c_next_cr2 = (
+ I2C_CR2_AUTOEND |
+ (length << I2C_CR2_NBYTES_Pos) |
+ I2C_CR2_START |
+ I2C_CR2_RD_WRN |
+ (i2c_address << I2C_CR2_SADD_Pos)
+ );
+ I2C1->CR2 = (
+ (1 << I2C_CR2_NBYTES_Pos) |
+ I2C_CR2_START |
+ (i2c_address << I2C_CR2_SADD_Pos)
+ );
+}
+
+void hw_i2c_write (uint8_t i2c_address, uint8_t address, uint8_t *data, uint8_t length, void (*callback)(void)) {
+ i2c_data_txptr = data;
+ i2c_callback = callback;
+ I2C1->TXDR = address;
+ I2C1->CR2 = (
+ I2C_CR2_AUTOEND |
+ ((length + 1) << I2C_CR2_NBYTES_Pos) |
+ I2C_CR2_START |
+ (i2c_address << I2C_CR2_SADD_Pos)
+ );
+}
+
+uint32_t hw_i2c_get_error (void) {
+ return I2C1->ISR & I2C_ISR_NACKF;
+}
+
+void hw_i2c_disable_irq (void) {
+ NVIC_DisableIRQ(I2C1_IRQn);
+}
+
+void hw_i2c_enable_irq (void) {
+ NVIC_EnableIRQ(I2C1_IRQn);
+}
+
+void hw_tim_setup (tim_id_t id, uint16_t delay, void (*callback)(void)) {
+ TIM_TypeDef *tim = ((TIM_TypeDef *) (tims[id]));
+ tim->CR1 = (TIM_CR1_OPM | TIM_CR1_URS);
+ tim->PSC = (64000 - 1);
+ tim->ARR = (delay - 1);
+ tim->DIER = TIM_DIER_UIE;
+ tim->EGR = TIM_EGR_UG;
+ tim->SR = 0;
+ tim->CR1 |= TIM_CR1_CEN;
+ tim_callbacks[id] = callback;
+}
+
+void hw_tim_disable_irq (tim_id_t id) {
+ switch (id) {
+ case TIM_ID_CIC:
+ NVIC_DisableIRQ(TIM14_IRQn);
+ break;
+ case TIM_ID_RTC:
+ NVIC_DisableIRQ(TIM16_IRQn);
+ break;
+ case TIM_ID_GVR:
+ NVIC_DisableIRQ(TIM17_IRQn);
+ break;
+ default:
+ break;
+ }
+}
+
+void hw_tim_enable_irq (tim_id_t id) {
+ switch (id) {
+ case TIM_ID_CIC:
+ NVIC_EnableIRQ(TIM14_IRQn);
+ break;
+ case TIM_ID_RTC:
+ NVIC_EnableIRQ(TIM16_IRQn);
+ break;
+ case TIM_ID_GVR:
+ NVIC_EnableIRQ(TIM17_IRQn);
+ break;
+ default:
+ break;
+ }
+}
+
+void hw_tim_stop (tim_id_t id) {
+ TIM_TypeDef *tim = ((TIM_TypeDef *) (tims[id]));
+ tim->CR1 &= ~(TIM_CR1_CEN);
+ tim_callbacks[id] = 0;
+}
+
+void hw_init (void) {
+ FLASH->ACR |= (FLASH_ACR_PRFTEN | (2 << FLASH_ACR_LATENCY_Pos));
+ while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (2 << FLASH_ACR_LATENCY_Pos));
+
+ RCC->PLLCFGR = (
+ ((2 - 1) << RCC_PLLCFGR_PLLR_Pos)
+ | RCC_PLLCFGR_PLLREN
+ | (16 << RCC_PLLCFGR_PLLN_Pos)
+ | ((2 - 1) << RCC_PLLCFGR_PLLM_Pos)
+ | RCC_PLLCFGR_PLLSRC_HSI
+ );
+
+ RCC->CR |= RCC_CR_PLLON;
+ while ((RCC->CR & RCC_CR_PLLRDY_Msk) != RCC_CR_PLLRDY);
+
+ RCC->CFGR = RCC_CFGR_SW_1;
+ while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_1);
+
+ RCC->AHBENR |= RCC_AHBENR_DMA1EN;
+ RCC->APBENR1 |= (
+ RCC_APBENR1_DBGEN |
+ RCC_APBENR1_I2C1EN
+ );
+ RCC->APBENR2 |= (
+ RCC_APBENR2_TIM17EN |
+ RCC_APBENR2_TIM16EN |
+ RCC_APBENR2_TIM14EN |
+ RCC_APBENR2_USART1EN |
+ RCC_APBENR2_SPI1EN |
+ RCC_APBENR2_SYSCFGEN
+ );
+
+ DBG->APBFZ2 = (
+ DBG_APB_FZ2_DBG_TIM17_STOP |
+ DBG_APB_FZ2_DBG_TIM16_STOP |
+ DBG_APB_FZ2_DBG_TIM14_STOP
+ );
+
+ RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN;
+
+ DMAMUX1_Channel0->CCR = (16 << DMAMUX_CxCR_DMAREQ_ID_Pos);
+ DMAMUX1_Channel1->CCR = (17 << DMAMUX_CxCR_DMAREQ_ID_Pos);
+
+ DMA1_Channel1->CPAR = (uint32_t) (&SPI1->DR);
+ DMA1_Channel2->CPAR = (uint32_t) (&SPI1->DR);
+
+ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_PA12_RMP | SYSCFG_CFGR1_PA11_RMP);
+
+ SPI1->CR2 = (
+ SPI_CR2_FRXTH |
+ (8 - 1) << SPI_CR2_DS_Pos |
+ SPI_CR2_TXDMAEN |
+ SPI_CR2_RXDMAEN
+ );
+ SPI1->CR1 = (
+ SPI_CR1_SSM |
+ SPI_CR1_SSI |
+ SPI_CR1_BR_1 |
+ SPI_CR1_SPE |
+ SPI_CR1_MSTR |
+ SPI_CR1_CPHA
+ );
+
+ USART1->BRR = (64000000UL) / 1000000;
+ USART1->CR1 = USART_CR1_FIFOEN | USART_CR1_TE | USART_CR1_UE;
+
+ I2C1->TIMINGR = 0x10B17DB5UL;
+ I2C1->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE | I2C_CR1_RXIE | I2C_CR1_TXIE | I2C_CR1_PE);
+
+ hw_gpio_init(GPIO_ID_N64_RESET, GPIO_INPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_DOWN, GPIO_AF_0, 0);
+ hw_gpio_init(GPIO_ID_N64_CIC_CLK, GPIO_INPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_DOWN, GPIO_AF_0, 0);
+ hw_gpio_init(GPIO_ID_N64_CIC_DQ, GPIO_OUTPUT, GPIO_OD, GPIO_SPEED_VLOW, GPIO_PULL_UP, GPIO_AF_0, 1);
+
+ hw_gpio_init(GPIO_ID_LED, GPIO_OUTPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_NONE, GPIO_AF_0, 0);
+
+ hw_gpio_init(GPIO_ID_SPI_CS, GPIO_OUTPUT, GPIO_PP, GPIO_SPEED_HIGH, GPIO_PULL_NONE, GPIO_AF_0, 1);
+ hw_gpio_init(GPIO_ID_SPI_CLK, GPIO_ALT, GPIO_PP, GPIO_SPEED_HIGH, GPIO_PULL_NONE, GPIO_AF_0, 0);
+ hw_gpio_init(GPIO_ID_SPI_MISO, GPIO_ALT, GPIO_PP, GPIO_SPEED_HIGH, GPIO_PULL_NONE, GPIO_AF_0, 0);
+ hw_gpio_init(GPIO_ID_SPI_MOSI, GPIO_ALT, GPIO_PP, GPIO_SPEED_HIGH, GPIO_PULL_NONE, GPIO_AF_0, 0);
+
+ hw_gpio_init(GPIO_ID_FPGA_INT, GPIO_INPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_UP, GPIO_AF_0, 0);
+
+ hw_gpio_init(GPIO_ID_UART_TX, GPIO_ALT, GPIO_PP, GPIO_SPEED_LOW, GPIO_PULL_NONE, GPIO_AF_1, 0);
+ hw_gpio_init(GPIO_ID_UART_RX, GPIO_ALT, GPIO_PP, GPIO_SPEED_LOW, GPIO_PULL_NONE, GPIO_AF_1, 0);
+
+ hw_gpio_init(GPIO_ID_I2C_SCL, GPIO_ALT, GPIO_OD, GPIO_SPEED_VLOW, GPIO_PULL_NONE, GPIO_AF_6, 0);
+ hw_gpio_init(GPIO_ID_I2C_SDA, GPIO_ALT, GPIO_OD, GPIO_SPEED_VLOW, GPIO_PULL_NONE, GPIO_AF_6, 0);
+
+ hw_gpio_init(GPIO_ID_RTC_MFP, GPIO_INPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_UP, GPIO_AF_0, 0);
+
+ NVIC_SetPriority(EXTI0_1_IRQn, 0);
+ NVIC_SetPriority(EXTI2_3_IRQn, 1);
+ NVIC_SetPriority(EXTI4_15_IRQn, 2);
+ NVIC_SetPriority(I2C1_IRQn, 1);
+ NVIC_SetPriority(TIM14_IRQn, 0);
+ NVIC_SetPriority(TIM16_IRQn, 1);
+ NVIC_SetPriority(TIM17_IRQn, 2);
+
+ NVIC_EnableIRQ(EXTI0_1_IRQn);
+ NVIC_EnableIRQ(EXTI2_3_IRQn);
+ NVIC_EnableIRQ(EXTI4_15_IRQn);
+ NVIC_EnableIRQ(I2C1_IRQn);
+ NVIC_EnableIRQ(TIM14_IRQn);
+ NVIC_EnableIRQ(TIM16_IRQn);
+ NVIC_EnableIRQ(TIM17_IRQn);
+}
+
+void EXTI0_1_IRQHandler (void) {
+ for (int i = 0; i <= 1; i++) {
+ if (EXTI->FPR1 & (EXTI_FPR1_FPIF0 << i)) {
+ EXTI->FPR1 = (EXTI_FPR1_FPIF0 << i);
+ if (gpio_irq_callbacks[i].falling) {
+ gpio_irq_callbacks[i].falling();
+ }
+ }
+ if (EXTI->RPR1 & (EXTI_RPR1_RPIF0 << i)) {
+ EXTI->RPR1 = (EXTI_RPR1_RPIF0 << i);
+ if (gpio_irq_callbacks[i].rising) {
+ gpio_irq_callbacks[i].rising();
+ }
+ }
+ }
+}
+
+void EXTI2_3_IRQHandler (void) {
+ for (int i = 2; i <= 3; i++) {
+ if (EXTI->FPR1 & (EXTI_FPR1_FPIF0 << i)) {
+ EXTI->FPR1 = (EXTI_FPR1_FPIF0 << i);
+ if (gpio_irq_callbacks[i].falling) {
+ gpio_irq_callbacks[i].falling();
+ }
+ }
+ if (EXTI->RPR1 & (EXTI_RPR1_RPIF0 << i)) {
+ EXTI->RPR1 = (EXTI_RPR1_RPIF0 << i);
+ if (gpio_irq_callbacks[i].rising) {
+ gpio_irq_callbacks[i].rising();
+ }
+ }
+ }
+}
+
+void EXTI4_15_IRQHandler (void) {
+ for (int i = 4; i <= 15; i++) {
+ if (EXTI->FPR1 & (EXTI_FPR1_FPIF0 << i)) {
+ EXTI->FPR1 = (EXTI_FPR1_FPIF0 << i);
+ if (gpio_irq_callbacks[i].falling) {
+ gpio_irq_callbacks[i].falling();
+ }
+ }
+ if (EXTI->RPR1 & (EXTI_RPR1_RPIF0 << i)) {
+ EXTI->RPR1 = (EXTI_RPR1_RPIF0 << i);
+ if (gpio_irq_callbacks[i].rising) {
+ gpio_irq_callbacks[i].rising();
+ }
+ }
+ }
+}
+
+void I2C1_IRQHandler (void) {
+ if (I2C1->ISR & I2C_ISR_TXIS) {
+ I2C1->TXDR = *i2c_data_txptr++;
+ }
+
+ if (I2C1->ISR & I2C_ISR_RXNE) {
+ *i2c_data_rxptr++ = I2C1->RXDR;
+ }
+
+ if (I2C1->ISR & I2C_ISR_TC) {
+ I2C1->CR2 = i2c_next_cr2;
+ }
+
+ if (I2C1->ISR & I2C_ISR_STOPF) {
+ I2C1->ICR = I2C_ICR_STOPCF;
+ if (i2c_callback) {
+ i2c_callback();
+ i2c_callback = 0;
+ }
+ }
+}
+
+void TIM14_IRQHandler (void) {
+ TIM14->SR &= ~(TIM_SR_UIF);
+ if (tim_callbacks[0]) {
+ tim_callbacks[0]();
+ tim_callbacks[0] = 0;
+ }
+}
+
+void TIM16_IRQHandler (void) {
+ TIM16->SR &= ~(TIM_SR_UIF);
+ if (tim_callbacks[1]) {
+ tim_callbacks[1]();
+ tim_callbacks[1] = 0;
+ }
+}
+
+void TIM17_IRQHandler (void) {
+ TIM17->SR &= ~(TIM_SR_UIF);
+ if (tim_callbacks[2]) {
+ tim_callbacks[2]();
+ tim_callbacks[2] = 0;
+ }
+}
diff --git a/sw/controller/src/hw.h b/sw/controller/src/hw.h
new file mode 100644
index 0000000..c156370
--- /dev/null
+++ b/sw/controller/src/hw.h
@@ -0,0 +1,63 @@
+#ifndef HW_H__
+#define HW_H__
+
+
+#include
+
+
+#define GPIO_PORT_PIN(p, n) ((((p) & 0x07) << 4) | ((n) & 0x0F))
+
+typedef enum {
+ GPIO_ID_N64_RESET = GPIO_PORT_PIN(0, 0),
+ GPIO_ID_N64_CIC_CLK = GPIO_PORT_PIN(0, 1),
+ GPIO_ID_N64_CIC_DQ = GPIO_PORT_PIN(0, 2),
+ GPIO_ID_LED = GPIO_PORT_PIN(0, 3),
+ GPIO_ID_SPI_CS = GPIO_PORT_PIN(0, 4),
+ GPIO_ID_SPI_CLK = GPIO_PORT_PIN(0, 5),
+ GPIO_ID_SPI_MISO = GPIO_PORT_PIN(0, 6),
+ GPIO_ID_SPI_MOSI = GPIO_PORT_PIN(0, 7),
+ GPIO_ID_UART_TX = GPIO_PORT_PIN(0, 9),
+ GPIO_ID_UART_RX = GPIO_PORT_PIN(0, 10),
+ GPIO_ID_FPGA_INT = GPIO_PORT_PIN(1, 2),
+ GPIO_ID_I2C_SCL = GPIO_PORT_PIN(1, 6),
+ GPIO_ID_I2C_SDA = GPIO_PORT_PIN(1, 7),
+ GPIO_ID_RTC_MFP = GPIO_PORT_PIN(1, 9),
+} gpio_id_t;
+
+typedef enum {
+ GPIO_IRQ_FALLING = 0b01,
+ GPIO_IRQ_RISING = 0b10,
+} gpio_irq_t;
+
+typedef enum {
+ TIM_ID_CIC = 0,
+ TIM_ID_RTC = 1,
+ TIM_ID_GVR = 2,
+} tim_id_t;
+
+typedef enum {
+ SPI_TX,
+ SPI_RX,
+} spi_direction_t;
+
+
+void hw_gpio_irq_setup (gpio_id_t id, gpio_irq_t irq, void (*callback)(void));
+uint32_t hw_gpio_get (gpio_id_t id);
+void hw_gpio_set (gpio_id_t id);
+void hw_gpio_reset (gpio_id_t id);
+void hw_spi_start (void);
+void hw_spi_stop (void);
+void hw_spi_trx (uint8_t *data, int length, spi_direction_t direction);
+void hw_i2c_read (uint8_t i2c_address, uint8_t address, uint8_t *data, uint8_t length, void (*callback)(void));
+void hw_i2c_write (uint8_t i2c_address, uint8_t address, uint8_t *data, uint8_t length, void (*callback)(void));
+uint32_t hw_i2c_get_error (void);
+void hw_i2c_disable_irq (void);
+void hw_i2c_enable_irq (void);
+void hw_tim_setup (tim_id_t id, uint16_t delay, void (*callback)(void));
+void hw_tim_stop (tim_id_t id);
+void hw_tim_disable_irq (tim_id_t id);
+void hw_tim_enable_irq (tim_id_t id);
+void hw_init (void);
+
+
+#endif
diff --git a/sw/controller/src/main.c b/sw/controller/src/main.c
new file mode 100644
index 0000000..caf8aaf
--- /dev/null
+++ b/sw/controller/src/main.c
@@ -0,0 +1,30 @@
+#include
+#include "cic.h"
+#include "gvr.h"
+#include "hw.h"
+#include "rtc.h"
+#include "task.h"
+
+
+#define CIC_STACK_SIZE (256)
+#define RTC_STACK_SIZE (256)
+#define GVR_STACK_SIZE (1024)
+
+
+uint8_t cic_stack[CIC_STACK_SIZE] __attribute__((aligned(8)));
+uint8_t rtc_stack[RTC_STACK_SIZE] __attribute__((aligned(8)));
+uint8_t gvr_stack[GVR_STACK_SIZE] __attribute__((aligned(8)));
+
+
+void main (void) {
+ hw_init();
+ cic_hw_init();
+
+ task_create(TASK_ID_CIC, cic_task, cic_stack, CIC_STACK_SIZE);
+ task_create(TASK_ID_RTC, rtc_task, rtc_stack, RTC_STACK_SIZE);
+ task_create(TASK_ID_GVR, gvr_task, gvr_stack, GVR_STACK_SIZE);
+
+ task_scheduler_start();
+
+ while (1);
+}
diff --git a/sw/controller/src/rtc.c b/sw/controller/src/rtc.c
new file mode 100644
index 0000000..5f3fecc
--- /dev/null
+++ b/sw/controller/src/rtc.c
@@ -0,0 +1,287 @@
+#include "fpga.h"
+#include "hw.h"
+#include "rtc.h"
+#include "task.h"
+
+
+#define RTC_I2C_ADDRESS (0xDE)
+
+#define RTC_ADDRESS_RTCSEC (0x00)
+#define RTC_ADDRESS_RTCMIN (0x01)
+#define RTC_ADDRESS_RTCHOUR (0x02)
+#define RTC_ADDRESS_RTCWKDAY (0x03)
+#define RTC_ADDRESS_RTCDATE (0x04)
+#define RTC_ADDRESS_RTCMTH (0x05)
+#define RTC_ADDRESS_RTCYEAR (0x06)
+#define RTC_ADDRESS_CONTROL (0x07)
+#define RTC_ADDRESS_OSCTRIM (0x08)
+#define RTC_ADDRESS_SRAM_MAGIC (0x20)
+#define RTC_ADDRESS_SRAM_REGION (0x24)
+
+#define RTC_RTCSEC_ST (1 << 7)
+
+#define RTC_RTCWKDAY_VBATEN (1 << 3)
+#define RTC_RTCWKDAY_OSCRUN (1 << 5)
+
+
+static uint8_t rtc_region = 0xFF;
+static volatile bool rtc_region_pending = false;
+
+static rtc_time_t rtc_time = {
+ .second = 0x00,
+ .minute = 0x00,
+ .hour = 0x12,
+ .weekday = 0x02,
+ .day = 0x01,
+ .month = 0x03,
+ .year = 0x22
+};
+static bool rtc_time_valid = false;
+static volatile bool rtc_time_pending = false;
+
+static const uint8_t rtc_regs_bit_mask[7] = {
+ 0b01111111,
+ 0b01111111,
+ 0b00111111,
+ 0b00000111,
+ 0b00111111,
+ 0b00011111,
+ 0b11111111
+};
+
+
+static void rtc_task_resume (void) {
+ task_set_ready(TASK_ID_RTC);
+}
+
+static void rtc_on_error (void) {
+ rtc_time_valid = false;
+ // TODO: blink some error code
+ task_yield();
+}
+
+static void rtc_read (uint8_t address, uint8_t *data, uint8_t length) {
+ hw_i2c_read(RTC_I2C_ADDRESS, address, data, length, rtc_task_resume);
+ task_yield();
+ if (hw_i2c_get_error()) {
+ rtc_on_error();
+ }
+}
+
+static void rtc_write (uint8_t address, uint8_t *data, uint8_t length) {
+ hw_i2c_write(RTC_I2C_ADDRESS, address, data, length, rtc_task_resume);
+ task_yield();
+ if (hw_i2c_get_error()) {
+ rtc_on_error();
+ }
+}
+
+static void rtc_sanitize_time (uint8_t *regs) {
+ for (int i = 0; i < 7; i++) {
+ regs[i] &= rtc_regs_bit_mask[i];
+ }
+}
+
+static void rtc_wait_osc (bool running) {
+ uint8_t rtcwkday;
+
+ while (1) {
+ rtc_read(RTC_ADDRESS_RTCWKDAY, &rtcwkday, 1);
+
+ if (running && (rtcwkday & RTC_RTCWKDAY_OSCRUN)) {
+ return;
+ } else if (!running && (!(rtcwkday & RTC_RTCWKDAY_OSCRUN))) {
+ return;
+ }
+ }
+}
+
+static void rtc_read_time (void) {
+ uint8_t regs[7];
+
+ rtc_read(RTC_ADDRESS_RTCSEC, regs, 7);
+
+ rtc_sanitize_time(regs);
+
+ if (!rtc_time_pending) {
+ rtc_time.second = regs[0];
+ rtc_time.minute = regs[1];
+ rtc_time.hour = regs[2];
+ rtc_time.weekday = regs[3];
+ rtc_time.day = regs[4];
+ rtc_time.month = regs[5];
+ rtc_time.year = regs[6];
+
+ rtc_time_valid = true;
+ }
+}
+
+static void rtc_write_time (void) {
+ uint8_t regs[7];
+
+ regs[0] = 0x00;
+
+ rtc_write(RTC_ADDRESS_RTCSEC, regs, 1);
+
+ rtc_wait_osc(false);
+
+ regs[0] = rtc_time.second;
+ regs[1] = rtc_time.minute;
+ regs[2] = rtc_time.hour;
+ regs[3] = rtc_time.weekday;
+ regs[4] = rtc_time.day;
+ regs[5] = rtc_time.month;
+ regs[6] = rtc_time.year;
+
+ rtc_sanitize_time(regs);
+
+ regs[0] |= RTC_RTCSEC_ST;
+ regs[3] |= (RTC_RTCWKDAY_OSCRUN | RTC_RTCWKDAY_VBATEN);
+
+ rtc_write(RTC_ADDRESS_RTCSEC, regs, 7);
+
+ rtc_wait_osc(true);
+}
+
+static void rtc_read_region (void) {
+ rtc_read(RTC_ADDRESS_SRAM_REGION, &rtc_region, 1);
+}
+
+static void rtc_write_region (void) {
+ rtc_write(RTC_ADDRESS_SRAM_REGION, &rtc_region, 1);
+}
+
+static void rtc_init (void) {
+ bool uninitialized = false;
+ const char *magic = "SC64";
+ uint8_t buffer[4];
+
+ rtc_read(RTC_ADDRESS_SRAM_MAGIC, buffer, 4);
+
+ for (int i = 0; i < 4; i++) {
+ if (buffer[i] != magic[i]) {
+ uninitialized = true;
+ break;
+ }
+ }
+
+ if (uninitialized) {
+ buffer[0] = 0;
+ rtc_write(RTC_ADDRESS_SRAM_MAGIC, (uint8_t *) (magic), 4);
+ rtc_write(RTC_ADDRESS_OSCTRIM, buffer, 1);
+ rtc_write_time();
+ rtc_write_region();
+ }
+}
+
+bool rtc_get_time (rtc_time_t *time) {
+ bool vaild;
+
+ hw_i2c_disable_irq();
+ hw_tim_disable_irq(TIM_ID_RTC);
+
+ time->second = rtc_time.second;
+ time->minute = rtc_time.minute;
+ time->hour = rtc_time.hour;
+ time->weekday = rtc_time.weekday;
+ time->day = rtc_time.day;
+ time->month = rtc_time.month;
+ time->year = rtc_time.year;
+ vaild = rtc_time_valid;
+
+ hw_tim_enable_irq(TIM_ID_RTC);
+ hw_i2c_enable_irq();
+
+ return vaild;
+}
+
+void rtc_set_time (rtc_time_t *time) {
+ hw_i2c_disable_irq();
+ hw_tim_disable_irq(TIM_ID_RTC);
+
+ rtc_time.second = time->second;
+ rtc_time.minute = time->minute;
+ rtc_time.hour = time->hour;
+ rtc_time.weekday = time->weekday;
+ rtc_time.day = time->day;
+ rtc_time.month = time->month;
+ rtc_time.year = time->year;
+ rtc_time_pending = true;
+
+ hw_tim_enable_irq(TIM_ID_RTC);
+ hw_i2c_enable_irq();
+}
+
+uint8_t rtc_get_region (void) {
+ return rtc_region;
+}
+
+void rtc_set_region (uint8_t region) {
+ rtc_region = region;
+ rtc_region_pending = true;
+}
+
+void rtc_task (void) {
+ rtc_init();
+
+ rtc_read_region();
+
+ while (1) {
+ if (rtc_time_pending) {
+ rtc_time_pending = false;
+ rtc_write_time();
+ }
+
+ if (rtc_region_pending) {
+ rtc_region_pending = false;
+ rtc_write_region();
+ }
+
+ rtc_read_time();
+
+ hw_tim_setup(TIM_ID_RTC, 50, rtc_task_resume);
+
+ task_yield();
+ }
+}
+
+void rtc_process (void) {
+ rtc_time_t time;
+ uint32_t data[2];
+
+ if (fpga_reg_get(REG_RTC_SCR) & RTC_SCR_PENDING) {
+ data[0] = fpga_reg_get(REG_RTC_TIME_0);
+ data[1] = fpga_reg_get(REG_RTC_TIME_1);
+
+ time.weekday = ((data[0] >> 24) & 0xFF) + 1;
+ time.hour = ((data[0] >> 16) & 0xFF);
+ time.minute = ((data[0] >> 8) & 0xFF);
+ time.second = ((data[0] >> 0) & 0xFF);
+ time.year = ((data[1] >> 16) & 0xFF);
+ time.month = ((data[1] >> 8) & 0xFF);
+ time.day = ((data[1] >> 0) & 0xFF);
+
+ rtc_set_time(&time);
+
+ fpga_reg_set(REG_RTC_TIME_0, data[0]);
+ fpga_reg_set(REG_RTC_TIME_1, data[1]);
+ fpga_reg_set(REG_RTC_SCR, RTC_SCR_DONE);
+ }
+
+ rtc_get_time(&time);
+
+ data[0] = (
+ ((time.weekday - 1) << 24) |
+ (time.hour << 16) |
+ (time.minute << 8) |
+ (time.second << 0)
+ );
+ data[1] = (
+ (time.year << 16) |
+ (time.month << 8) |
+ (time.day << 0)
+ );
+
+ fpga_reg_set(REG_RTC_TIME_0, data[0]);
+ fpga_reg_set(REG_RTC_TIME_1, data[1]);
+}
diff --git a/sw/riscv/src/rtc.h b/sw/controller/src/rtc.h
similarity index 52%
rename from sw/riscv/src/rtc.h
rename to sw/controller/src/rtc.h
index 02937e4..3df6502 100644
--- a/sw/riscv/src/rtc.h
+++ b/sw/controller/src/rtc.h
@@ -2,7 +2,8 @@
#define RTC_H__
-#include "sys.h"
+#include
+#include
typedef struct {
@@ -16,12 +17,12 @@ typedef struct {
} rtc_time_t;
-rtc_time_t *rtc_get_time (void);
-bool rtc_is_time_valid (void);
-bool rtc_is_time_running (void);
+bool rtc_get_time (rtc_time_t *time);
void rtc_set_time (rtc_time_t *time);
-void rtc_init (void);
-void process_rtc (void);
+uint8_t rtc_get_region (void);
+void rtc_set_region (uint8_t region);
+void rtc_task (void);
+void rtc_process (void);
#endif
diff --git a/sw/controller/src/startup.S b/sw/controller/src/startup.S
new file mode 100644
index 0000000..669c83f
--- /dev/null
+++ b/sw/controller/src/startup.S
@@ -0,0 +1,158 @@
+.syntax unified
+.cpu cortex-m0plus
+.fpu softvfp
+.thumb
+
+.section .text.Reset_Handler
+.type Reset_Handler, %function
+Reset_Handler:
+ .global Reset_Handler
+ cpsid i
+
+init_data:
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b 2f
+1:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+2:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc 1b
+
+init_bss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b 2f
+1:
+ str r3, [r2]
+ adds r2, r2, #4
+2:
+ cmp r2, r4
+ bcc 1b
+
+run:
+ bl main
+
+loop:
+ b loop
+
+
+.section .text.Default_Handler, "ax", %progbits
+Default_Handler:
+ .global Default_Handler
+ b Default_Handler
+
+
+.section .isr_vector, "a", %progbits
+.type g_pfnVectors, %object
+g_pfnVectors:
+ .global g_pfnVectors
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word 0
+ .word RTC_TAMP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_1_IRQHandler
+ .word EXTI2_3_IRQHandler
+ .word EXTI4_15_IRQHandler
+ .word 0
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_3_IRQHandler
+ .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
+ .word ADC1_IRQHandler
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word 0
+ .word TIM3_IRQHandler
+ .word 0
+ .word 0
+ .word TIM14_IRQHandler
+ .word 0
+ .word TIM16_IRQHandler
+ .word TIM17_IRQHandler
+ .word I2C1_IRQHandler
+ .word I2C2_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word 0
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler, Default_Handler
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler, Default_Handler
+ .weak SVC_Handler
+ .thumb_set SVC_Handler, Default_Handler
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler, Default_Handler
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler, Default_Handler
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler, Default_Handler
+ .weak RTC_TAMP_IRQHandler
+ .thumb_set RTC_TAMP_IRQHandler, Default_Handler
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler, Default_Handler
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler, Default_Handler
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler, Default_Handler
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler, Default_Handler
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler, Default_Handler
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler, Default_Handler
+ .weak DMA1_Channel2_3_IRQHandler
+ .thumb_set DMA1_Channel2_3_IRQHandler, Default_Handler
+ .weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
+ .thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler, Default_Handler
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler, Default_Handler
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler, Default_Handler
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler, Default_Handler
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler, Default_Handler
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler, Default_Handler
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler, Default_Handler
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler, Default_Handler
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler, Default_Handler
+ .weak I2C2_IRQHandler
+ .thumb_set I2C2_IRQHandler, Default_Handler
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler, Default_Handler
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler, Default_Handler
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler, Default_Handler
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler, Default_Handler
diff --git a/sw/controller/src/task.c b/sw/controller/src/task.c
new file mode 100644
index 0000000..3c5aa6c
--- /dev/null
+++ b/sw/controller/src/task.c
@@ -0,0 +1,141 @@
+#include
+#include "task.h"
+
+
+#define TASK_INITIAL_XPSR (0x21000000UL)
+#define TASK_CONTEXT_SWITCH() { SCB->ICSR = (1 << SCB_ICSR_PENDSVSET_Pos); }
+
+
+typedef enum {
+ TASK_FLAG_NONE = 0,
+ TASK_FLAG_READY = (1 << 0),
+ TASK_FLAG_RESET = (1 << 1),
+} task_flags_t;
+
+typedef struct {
+ uint32_t initial_pc;
+ uint32_t initial_sp;
+ uint32_t sp;
+ task_flags_t flags;
+} task_t;
+
+
+static task_t task_table[__TASK_ID_MAX];
+static volatile task_id_t task_current = 0;
+
+
+static void task_exit (void) {
+ task_table[task_current].flags = TASK_FLAG_NONE;
+ task_yield();
+ while (1);
+}
+
+static void task_initialize (task_id_t id) {
+ task_t *task = &task_table[id];
+ uint32_t *sp = ((uint32_t *) (task->initial_sp));
+ *--sp = TASK_INITIAL_XPSR;
+ *--sp = task->initial_pc;
+ *--sp = ((uint32_t) (task_exit));
+ sp -= 13;
+ task->sp = ((uint32_t) (sp));
+}
+
+static void task_reset (task_id_t id) {
+ task_table[id].flags &= ~(TASK_FLAG_RESET);
+ task_initialize(id);
+}
+
+static uint32_t task_switch_context (uint32_t sp) {
+ task_table[task_current].sp = sp;
+
+ for (task_id_t id = 0; id < __TASK_ID_MAX; id++) {
+ if (task_table[id].flags & TASK_FLAG_READY) {
+ task_current = id;
+ break;
+ }
+ }
+
+ if (task_table[task_current].flags & TASK_FLAG_RESET) {
+ task_reset(task_current);
+ }
+
+ return task_table[task_current].sp;
+}
+
+void task_create (task_id_t id, void (*code)(void), void *stack, size_t stack_size) {
+ if (id < __TASK_ID_MAX) {
+ task_t *task = &task_table[id];
+ task->initial_pc = (uint32_t) (code);
+ task->initial_sp = (((uint32_t) (stack)) + stack_size);
+ task->flags = TASK_FLAG_READY;
+ task_initialize(id);
+ }
+}
+
+void task_yield (void) {
+ task_table[task_current].flags &= ~(TASK_FLAG_READY);
+ TASK_CONTEXT_SWITCH();
+}
+
+void task_set_ready (task_id_t id) {
+ task_table[id].flags |= TASK_FLAG_READY;
+ TASK_CONTEXT_SWITCH();
+}
+
+void task_set_ready_and_reset (task_id_t id) {
+ task_table[id].flags |= (TASK_FLAG_RESET | TASK_FLAG_READY);
+ TASK_CONTEXT_SWITCH();
+}
+
+__attribute__((naked)) void task_scheduler_start (void) {
+ uint32_t sp = task_table[task_current].sp;
+
+ NVIC_SetPriority(PendSV_IRQn, 3);
+
+ asm volatile (
+ "add %[sp], #32 \n"
+ "msr psp, %[sp] \n"
+ "movs r0, #2 \n"
+ "msr CONTROL, r0 \n"
+ "isb \n"
+ "pop {r0-r5} \n"
+ "mov lr, r5 \n"
+ "pop {r3} \n"
+ "pop {r2} \n"
+ "cpsie i \n"
+ "bx r3 \n"
+ :: [sp] "r" (sp)
+ );
+
+ while (1);
+}
+
+__attribute__((naked)) void PendSV_Handler (void) {
+ asm volatile (
+ "mrs r1, psp \n"
+ "sub r1, r1, #32 \n"
+ "mov r0, r1 \n"
+ "stmia r1!, {r4-r7} \n"
+ "mov r4, r8 \n"
+ "mov r5, r9 \n"
+ "mov r6, r10 \n"
+ "mov r7, r11 \n"
+ "stmia r1!, {r4-r7} \n"
+ "push {lr} \n"
+ "cpsid i \n"
+ "blx %[task_switch_context] \n"
+ "cpsie i \n"
+ "pop {r2} \n"
+ "add r0, #16 \n"
+ "ldmia r0!, {r4-r7} \n"
+ "mov r8, r4 \n"
+ "mov r9, r5 \n"
+ "mov r10, r6 \n"
+ "mov r11, r7 \n"
+ "msr psp, r0 \n"
+ "sub r0, #32 \n"
+ "ldmia r0!, {r4-r7} \n"
+ "bx r2 \n"
+ :: [task_switch_context] "r" (task_switch_context)
+ );
+}
diff --git a/sw/controller/src/task.h b/sw/controller/src/task.h
new file mode 100644
index 0000000..0a2bf24
--- /dev/null
+++ b/sw/controller/src/task.h
@@ -0,0 +1,23 @@
+#ifndef TASK_H__
+#define TASK_H__
+
+
+#include
+
+
+typedef enum {
+ TASK_ID_CIC,
+ TASK_ID_RTC,
+ TASK_ID_GVR,
+ __TASK_ID_MAX
+} task_id_t;
+
+
+void task_create (task_id_t id, void (*code)(void), void *stack, size_t stack_size);
+void task_yield (void);
+void task_set_ready (task_id_t id);
+void task_set_ready_and_reset (task_id_t id);
+void task_scheduler_start (void);
+
+
+#endif
diff --git a/sw/controller/src/usb.c b/sw/controller/src/usb.c
new file mode 100644
index 0000000..00443a1
--- /dev/null
+++ b/sw/controller/src/usb.c
@@ -0,0 +1,243 @@
+#include
+#include
+#include "cfg.h"
+#include "fpga.h"
+#include "rtc.h"
+#include "usb.h"
+#include "flash.h"
+
+
+enum state {
+ STATE_IDLE,
+ STATE_ARGS,
+ STATE_DATA,
+ STATE_RESPONSE
+};
+
+struct process {
+ enum state state;
+ uint32_t counter;
+ uint8_t cmd;
+ uint32_t args[2];
+ bool error;
+ bool dma_in_progress;
+};
+
+static struct process p;
+
+
+static const char CMD_TOKEN[3] = { 'C', 'M', 'D' };
+static const uint32_t CMP_TOKEN = (0x434D5000UL);
+static const uint32_t ERR_TOKEN = (0x45525200UL);
+
+static bool usb_rx_byte (uint8_t *data) {
+ if (fpga_usb_status_get() & USB_STATUS_RXNE) {
+ *data = fpga_usb_pop();
+ return true;
+ }
+ return false;
+}
+
+static bool usb_tx_byte (uint8_t data) {
+ if (fpga_usb_status_get() & USB_STATUS_TXE) {
+ fpga_usb_push(data);
+ return true;
+ }
+ return false;
+}
+
+static uint8_t usb_rx_word_counter = 0;
+static uint32_t usb_rx_word_buffer = 0;
+
+static bool usb_rx_word (uint32_t *data) {
+ uint8_t tmp;
+ while (usb_rx_byte(&tmp)) {
+ usb_rx_word_buffer = (usb_rx_word_buffer << 8) | tmp;
+ usb_rx_word_counter += 1;
+ if (usb_rx_word_counter == 4) {
+ usb_rx_word_counter = 0;
+ *data = usb_rx_word_buffer;
+ usb_rx_word_buffer = 0;
+ return true;
+ }
+ }
+ return false;
+}
+
+static uint8_t usb_tx_word_counter = 0;
+
+static bool usb_tx_word (uint32_t data) {
+ while (usb_tx_byte(data >> ((3 - usb_tx_word_counter) * 8))) {
+ usb_tx_word_counter += 1;
+ if (usb_tx_word_counter == 4) {
+ usb_tx_word_counter = 0;
+ return true;
+ }
+ }
+ return false;
+}
+
+static uint8_t usb_rx_cmd_counter = 0;
+
+static bool usb_rx_cmd (uint8_t *cmd) {
+ uint8_t data;
+ while (usb_rx_byte(&data)) {
+ if (usb_rx_cmd_counter == 3) {
+ *cmd = data;
+ usb_rx_cmd_counter = 0;
+ return true;
+ }
+ if (data != CMD_TOKEN[usb_rx_cmd_counter++]) {
+ usb_rx_cmd_counter = 0;
+ return false;
+ }
+ }
+ return false;
+}
+
+
+void usb_init (void) {
+ fpga_reg_set(REG_USB_DMA_SCR, DMA_SCR_STOP);
+ fpga_reg_set(REG_USB_SCR, USB_SCR_FIFO_FLUSH);
+
+ p.state = STATE_IDLE;
+
+ usb_rx_word_counter = 0;
+ usb_rx_word_buffer = 0;
+ usb_tx_word_counter = 0;
+ usb_rx_cmd_counter = 0;
+}
+
+void usb_process (void) {
+ uint32_t scr = fpga_reg_get(REG_USB_SCR);
+
+ if (scr & USB_SCR_RESET_PENDING) {
+ usb_init();
+ fpga_reg_set(REG_USB_SCR, USB_SCR_RESET_ACK);
+ return;
+ }
+
+ switch (p.state) {
+ case STATE_IDLE: {
+ if (usb_rx_cmd(&p.cmd)) {
+ p.counter = 0;
+ p.error = false;
+ p.dma_in_progress = false;
+ p.state = STATE_ARGS;
+ }
+ break;
+ }
+
+ case STATE_ARGS: {
+ if (usb_rx_word(&p.args[p.counter])) {
+ p.counter += 1;
+ if (p.counter == 2) {
+ p.counter = 0;
+ p.state = STATE_DATA;
+ }
+ }
+ break;
+ }
+
+ case STATE_DATA: {
+ switch (p.cmd) {
+ case 'v':
+ if (usb_tx_word(cfg_get_version())) {
+ p.state = STATE_RESPONSE;
+ }
+ break;
+
+ case 'c':
+ if (p.counter == 0) {
+ cfg_query(p.args);
+ p.counter += 1;
+ }
+ if (usb_tx_word(p.args[1])) {
+ p.state = STATE_RESPONSE;
+ }
+ break;
+
+ case 'C':
+ cfg_update(p.args);
+ p.state = STATE_RESPONSE;
+ break;
+
+ case 't':
+ if (p.counter == 0) {
+ cfg_get_time(p.args);
+ p.counter += 1;
+ }
+ if ((p.counter == 1) && usb_tx_word(p.args[0])) {
+ p.counter += 1;
+ }
+ if ((p.counter == 2) && usb_tx_word(p.args[1])) {
+ p.state = STATE_RESPONSE;
+ }
+ break;
+
+ case 'T':
+ cfg_set_time(p.args);
+ p.state = STATE_RESPONSE;
+ break;
+
+ case 'e':
+ if (p.args[1] == 0) {
+ p.state = STATE_RESPONSE;
+ } else {
+ uint8_t data[8];
+ int length = (p.args[1] > 8) ? 8 : p.args[1];
+ fpga_eeprom_read(p.args[0], length, data);
+ for (int i = 0; i < length; i++) {
+ while (!usb_tx_byte(data[i]));
+ }
+ p.args[0] += length;
+ p.args[1] -= length;
+ }
+ break;
+
+ case 'E':
+ if (p.args[1] == 0) {
+ p.state = STATE_RESPONSE;
+ } else {
+ uint8_t data[8];
+ int length = (p.args[1] > 8) ? 8 : p.args[1];
+ for (int i = 0; i < length; i++) {
+ while (!usb_rx_byte(&data[i]));
+ }
+ fpga_eeprom_write(p.args[0], length, data);
+ p.args[0] += length;
+ p.args[1] -= length;
+ }
+ break;
+
+ case 'm':
+ case 'M':
+ if (!((fpga_reg_get(REG_USB_DMA_SCR) & DMA_SCR_BUSY))) {
+ if (!p.dma_in_progress) {
+ fpga_reg_set(REG_USB_DMA_ADDRESS, p.args[0]);
+ fpga_reg_set(REG_USB_DMA_LENGTH, p.args[1]);
+ fpga_reg_set(REG_USB_DMA_SCR, (p.cmd == 'M' ? DMA_SCR_DIRECTION : 0) | DMA_SCR_START);
+ p.dma_in_progress = true;
+ } else {
+ p.state = STATE_RESPONSE;
+ }
+ }
+ break;
+
+ default:
+ p.error = true;
+ p.state = STATE_RESPONSE;
+ break;
+ }
+ break;
+ }
+
+ case STATE_RESPONSE: {
+ if (usb_tx_word((p.error ? ERR_TOKEN : CMP_TOKEN) | p.cmd)) {
+ p.state = STATE_IDLE;
+ fpga_reg_set(REG_USB_SCR, USB_SCR_WRITE_FLUSH);
+ }
+ break;
+ }
+ }
+}
diff --git a/sw/controller/src/usb.h b/sw/controller/src/usb.h
new file mode 100644
index 0000000..915f1bb
--- /dev/null
+++ b/sw/controller/src/usb.h
@@ -0,0 +1,9 @@
+#ifndef USB_H__
+#define USB_H__
+
+
+void usb_init (void);
+void usb_process (void);
+
+
+#endif
diff --git a/sw/pc/sc64.py b/sw/pc/sc64.py
index c2ed6d4..1957618 100644
--- a/sw/pc/sc64.py
+++ b/sw/pc/sc64.py
@@ -22,25 +22,41 @@ class SC64Exception(Exception):
class SC64:
+ # __CFG_ID_DD_ENABLE = 3
+ # __CFG_ID_SAVE_TYPE = 4
+ # __CFG_ID_CIC_SEED = 5
+ # __CFG_ID_TV_TYPE = 6
+ # __CFG_ID_SAVE_OFFEST = 7
+ # __CFG_ID_DDIPL_OFFEST = 8
+ # __CFG_ID_BOOT_MODE = 9
+ # __CFG_ID_FLASH_SIZE = 10
+ # __CFG_ID_FLASH_READ = 11
+ # __CFG_ID_FLASH_PROGRAM = 12
+ # __CFG_ID_RECONFIGURE = 13
+ # __CFG_ID_DD_DRIVE_ID = 14
+ # __CFG_ID_DD_DISK_STATE = 15
+ # __CFG_ID_DD_THB_TABLE_OFFSET = 16
+ # __CFG_ID_IS_VIEWER_ENABLE = 17
+
+
+ __CFG_ID_BOOTLOADER_SWITCH = 0
+ __CFG_ID_ROM_WRITE_ENABLE = 1
+ __CFG_ID_ROM_SHADOW_ENABLE = 2
__CFG_ID_DD_ENABLE = 3
- __CFG_ID_SAVE_TYPE = 4
- __CFG_ID_CIC_SEED = 5
- __CFG_ID_TV_TYPE = 6
- __CFG_ID_SAVE_OFFEST = 7
- __CFG_ID_DDIPL_OFFEST = 8
- __CFG_ID_BOOT_MODE = 9
- __CFG_ID_FLASH_SIZE = 10
- __CFG_ID_FLASH_READ = 11
- __CFG_ID_FLASH_PROGRAM = 12
- __CFG_ID_RECONFIGURE = 13
- __CFG_ID_DD_DRIVE_ID = 14
- __CFG_ID_DD_DISK_STATE = 15
- __CFG_ID_DD_THB_TABLE_OFFSET = 16
- __CFG_ID_IS_VIEWER_ENABLE = 17
+ __CFG_ID_ISV_ENABLE = 4
+ __CFG_ID_BOOT_MODE = 5
+ __CFG_ID_SAVE_TYPE = 6
+ __CFG_ID_CIC_SEED = 7
+ __CFG_ID_TV_TYPE = 8
+ __CFG_ID_FLASH_ERASE_BLOCK = 9
+
+ __FLASH_ERASE_BLOCK_SIZE = 64 * 1024
__SC64_VERSION_V2 = 0x53437632
- __UPDATE_OFFSET = 0x03B00000
+ __BOOTLOADER_OFFSET = (64 + 14) * 1024 * 1024
+ __SAVE_OFFSET = (64 * 1024 * 1024) - (256 * 1024)
+ __DDIPL_OFFSET = 0x3bc0000 # (64 - 16 - 4) * 1024 * 1024
__CHUNK_SIZE = 256 * 1024
@@ -159,7 +175,7 @@ class SC64:
for p in ports:
if (p.vid == 0x0403 and p.pid == 0x6014 and p.serial_number.startswith("SC64")):
try:
- self.__usb = Serial(p.device, timeout=1.0, write_timeout=1.0)
+ self.__usb = Serial(p.device, timeout=10.0, write_timeout=10.0)
self.reset_link()
self.__probe_device()
except (SerialException, SC64Exception):
@@ -174,17 +190,17 @@ class SC64:
def __probe_device(self) -> None:
- self.__write_cmd("V", 0, 0)
+ self.__write_cmd("v", 0, 0)
version = self.__read_int()
- self.__read_cmd_status("V")
+ self.__read_cmd_status("v")
if (version != self.__SC64_VERSION_V2):
raise SC64Exception(f"Unknown hardware version: {hex(version)}")
def __query_config(self, id: int) -> int:
- self.__write_cmd("Q", id, 0)
+ self.__write_cmd("c", id, 0)
value = self.__read_int()
- self.__read_cmd_status("Q")
+ self.__read_cmd_status("c")
return value
@@ -197,12 +213,25 @@ class SC64:
def __read_file_from_sdram(self, file: str, offset: int, length: int) -> None:
with open(file, "wb") as f:
self.__set_progress_init(length, os.path.basename(f.name))
- self.__write_cmd("R", offset, length)
+ self.__write_cmd("m", offset, length)
while (f.tell() < length):
chunk_size = min(self.__CHUNK_SIZE, length - f.tell())
f.write(self.__read(chunk_size))
self.__set_progress_value(f.tell())
- self.__read_cmd_status("R")
+ self.__read_cmd_status("m")
+ self.__set_progress_finish()
+
+
+ def __read_file_from_eeprom(self, file: str) -> None:
+ length = 2048
+ with open(file, "wb") as f:
+ self.__set_progress_init(length, os.path.basename(f.name))
+ self.__write_cmd("e", 0, length)
+ while (f.tell() < length):
+ chunk_size = min(self.__CHUNK_SIZE, length - f.tell())
+ f.write(self.__read(chunk_size))
+ self.__set_progress_value(f.tell())
+ self.__read_cmd_status("e")
self.__set_progress_finish()
@@ -211,13 +240,51 @@ class SC64:
length = os.fstat(f.fileno()).st_size
transfer_size = max(length, min_length)
self.__set_progress_init(transfer_size, os.path.basename(f.name))
- self.__write_cmd("W", offset, transfer_size)
+ self.__write_cmd("M", offset, transfer_size)
while (f.tell() < length):
self.__write(f.read(min(self.__CHUNK_SIZE, length - f.tell())))
self.__set_progress_value(f.tell())
if (transfer_size != length):
self.__write_dummy(transfer_size - length)
- self.__read_cmd_status("W")
+ self.__read_cmd_status("M")
+ self.__set_progress_finish()
+
+
+ def __write_file_to_eeprom(self, file: str) -> None:
+ length = 2048
+ with open(file, "rb") as f:
+ file_length = os.fstat(f.fileno()).st_size
+ # transfer_size = max(length, min_length)
+ self.__set_progress_init(file_length, os.path.basename(f.name))
+ self.__write_cmd("E", 0, length)
+ while (f.tell() < file_length):
+ self.__write(f.read(min(self.__CHUNK_SIZE, file_length - f.tell())))
+ self.__set_progress_value(f.tell())
+ if (file_length != length):
+ self.__write_dummy(length - file_length)
+ self.__read_cmd_status("E")
+ self.__set_progress_finish()
+
+
+ def upload_bootloader(self, file: str, min_length: int = 1028 * 1024) -> None:
+ offset = self.__BOOTLOADER_OFFSET
+ with open(file, "rb") as f:
+ length = os.fstat(f.fileno()).st_size
+ transfer_size = max(length, min_length)
+ self.__set_progress_init(transfer_size, "Erase...")
+ for block in range(offset, offset + transfer_size, self.__FLASH_ERASE_BLOCK_SIZE):
+ self.__change_config(self.__CFG_ID_FLASH_ERASE_BLOCK, block)
+ self.__set_progress_value(block - offset)
+ self.__set_progress_finish()
+
+ self.__set_progress_init(transfer_size, os.path.basename(f.name))
+ self.__write_cmd("M", offset, transfer_size)
+ while (f.tell() < length):
+ self.__write(f.read(min(self.__CHUNK_SIZE, length - f.tell())))
+ self.__set_progress_value(f.tell())
+ if (transfer_size != length):
+ self.__write_dummy(transfer_size - length)
+ self.__read_cmd_status("M")
self.__set_progress_finish()
@@ -229,30 +296,32 @@ class SC64:
2: 2048,
3: (32 * 1024),
4: (128 * 1024),
- 5: (3 * 32 * 1024),
- 6: (128 * 1024)
+ 5: (3 * 32 * 1024)
}[save_type]
def __reconfigure(self) -> None:
- magic = self.__query_config(self.__CFG_ID_RECONFIGURE)
- self.__change_config(self.__CFG_ID_RECONFIGURE, magic, ignore_response=True)
- time.sleep(0.5)
+ pass
+ # magic = self.__query_config(self.__CFG_ID_RECONFIGURE)
+ # self.__change_config(self.__CFG_ID_RECONFIGURE, magic, ignore_response=True)
+ # time.sleep(0.5)
def backup_firmware(self, file: str) -> None:
- length = self.__query_config(self.__CFG_ID_FLASH_SIZE)
- self.__change_config(self.__CFG_ID_FLASH_READ, self.__UPDATE_OFFSET)
- self.__read_file_from_sdram(file, self.__UPDATE_OFFSET, length)
+ pass
+ # length = self.__query_config(self.__CFG_ID_FLASH_SIZE)
+ # self.__change_config(self.__CFG_ID_FLASH_READ, self.__UPDATE_OFFSET)
+ # self.__read_file_from_sdram(file, self.__UPDATE_OFFSET, length)
def update_firmware(self, file: str) -> None:
- self.__write_file_to_sdram(file, self.__UPDATE_OFFSET)
- saved_timeout = self.__usb.timeout
- self.__usb.timeout = 20.0
- self.__change_config(self.__CFG_ID_FLASH_PROGRAM, self.__UPDATE_OFFSET)
- self.__usb.timeout = saved_timeout
- self.__reconfigure()
+ pass
+ # self.__write_file_to_sdram(file, self.__UPDATE_OFFSET)
+ # saved_timeout = self.__usb.timeout
+ # self.__usb.timeout = 20.0
+ # self.__change_config(self.__CFG_ID_FLASH_PROGRAM, self.__UPDATE_OFFSET)
+ # self.__usb.timeout = saved_timeout
+ # self.__reconfigure()
def set_rtc(self, t: datetime) -> None:
@@ -261,8 +330,8 @@ class SC64:
(to_bcd(t.weekday() + 1) << 24) | (to_bcd(t.hour) << 16) | (to_bcd(t.minute) << 8) | to_bcd(t.second),
(to_bcd(t.year) << 16) | (to_bcd(t.month) << 8) | to_bcd(t.day),
]
- self.__write_cmd(0xEF, args[0], args[1])
- self.__read_cmd_status(0xEF)
+ self.__write_cmd("T", args[0], args[1])
+ self.__read_cmd_status("T")
def set_boot_mode(self, mode: int) -> None:
@@ -321,14 +390,14 @@ class SC64:
def set_save_type(self, type: int) -> None:
- if (type >= 0 and type <= 6):
+ if (type >= 0 and type <= 5):
self.__change_config(self.__CFG_ID_SAVE_TYPE, type)
else:
raise SC64Exception("Save type outside of supported values")
def get_save_type_label(self, type: int) -> None:
- if (type < 0 or type > 6):
+ if (type < 0 or type > 5):
return "Unknown"
return {
0: "No save",
@@ -336,30 +405,30 @@ class SC64:
2: "EEPROM 16Kb",
3: "SRAM 256Kb",
4: "FlashRAM 1Mb",
- 5: "SRAM 768Kb",
- 6: "FlashRAM 1Mb (Pokemon Stadium 2 special case)"
+ 5: "SRAM 768Kb"
}[type]
def download_save(self, file: str) -> None:
- length = self.__get_save_length()
- if (length > 0):
- offset = self.__query_config(self.__CFG_ID_SAVE_OFFEST)
- self.__read_file_from_sdram(file, offset, length)
- else:
- raise SC64Exception("Can't read save data - no save type is set")
+ self.__read_file_from_eeprom(file)
+ # length = self.__get_save_length()
+ # if (length > 0):
+ # self.__read_file_from_sdram(file, self.__SAVE_OFFSET, length)
+
+ # else:
+ # raise SC64Exception("Can't read save data - no save type is set")
def upload_save(self, file: str) -> None:
- length = self.__get_save_length()
- save_length = os.path.getsize(file)
- if (length <= 0):
- raise SC64Exception("Can't write save data - no save type is set")
- elif (length != save_length):
- raise SC64Exception("Can't write save data - save file size is different than expected")
- else:
- offset = self.__query_config(self.__CFG_ID_SAVE_OFFEST)
- self.__write_file_to_sdram(file, offset)
+ self.__write_file_to_eeprom(file)
+ # length = self.__get_save_length()
+ # save_length = os.path.getsize(file)
+ # if (length <= 0):
+ # raise SC64Exception("Can't write save data - no save type is set")
+ # elif (length != save_length):
+ # raise SC64Exception("Can't write save data - save file size is different than expected")
+ # else:
+ # self.__write_file_to_sdram(file, self.__SAVE_OFFSET)
def set_dd_enable(self, enable: bool) -> None:
@@ -367,294 +436,290 @@ class SC64:
def download_dd_ipl(self, file: str) -> None:
- dd_ipl_offset = self.__query_config(self.__CFG_ID_DDIPL_OFFEST)
- self.__read_file_from_sdram(file, dd_ipl_offset, length=self.__DDIPL_ROM_LENGTH)
+ self.__read_file_from_sdram(file, self.__DDIPL_OFFSET, length=self.__DDIPL_ROM_LENGTH)
- def upload_dd_ipl(self, file: str, offset: int = None) -> None:
- if (offset != None):
- self.__change_config(self.__CFG_ID_DDIPL_OFFEST, offset)
- dd_ipl_offset = self.__query_config(self.__CFG_ID_DDIPL_OFFEST)
- self.__write_file_to_sdram(file, dd_ipl_offset, min_length=self.__DDIPL_ROM_LENGTH)
+ def upload_dd_ipl(self, file: str) -> None:
+ self.__write_file_to_sdram(file, self.__DDIPL_OFFSET, min_length=self.__DDIPL_ROM_LENGTH)
- def set_dd_disk_state(self, state: str) -> None:
- state_mapping = {
- "ejected": self.__DD_DISK_STATE_EJECTED,
- "inserted": self.__DD_DISK_STATE_INSERTED,
- "changed": self.__DD_DISK_STATE_CHANGED,
- }
- if (state in state_mapping):
- self.__change_config(self.__CFG_ID_DD_DISK_STATE, state_mapping[state])
- else:
- raise SC64Exception("DD disk state outside of supported values")
+ # def set_dd_disk_state(self, state: str) -> None:
+ # state_mapping = {
+ # "ejected": self.__DD_DISK_STATE_EJECTED,
+ # "inserted": self.__DD_DISK_STATE_INSERTED,
+ # "changed": self.__DD_DISK_STATE_CHANGED,
+ # }
+ # if (state in state_mapping):
+ # self.__change_config(self.__CFG_ID_DD_DISK_STATE, state_mapping[state])
+ # else:
+ # raise SC64Exception("DD disk state outside of supported values")
- def __dd_create_configuration(self, handle: TextIOWrapper) -> tuple[str, int, list[tuple[int, int]]]:
- DISK_HEADS = 2
- DISK_TRACKS = 1175
- DISK_BLOCKS_PER_TRACK = 2
- DISK_SECTORS_PER_BLOCK = 85
- DISK_BAD_TRACKS_PER_ZONE = 12
- DISK_SYSTEM_SECTOR_SIZE = 232
+ # def __dd_create_configuration(self, handle: TextIOWrapper) -> tuple[str, int, list[tuple[int, int]]]:
+ # DISK_HEADS = 2
+ # DISK_TRACKS = 1175
+ # DISK_BLOCKS_PER_TRACK = 2
+ # DISK_SECTORS_PER_BLOCK = 85
+ # DISK_BAD_TRACKS_PER_ZONE = 12
+ # DISK_SYSTEM_SECTOR_SIZE = 232
- DISK_ZONES = [
- (0, 232, 158, 0),
- (0, 216, 158, 158),
- (0, 208, 149, 316),
- (0, 192, 149, 465),
- (0, 176, 149, 614),
- (0, 160, 149, 763),
- (0, 144, 149, 912),
- (0, 128, 114, 1061),
- (1, 216, 158, 157),
- (1, 208, 158, 315),
- (1, 192, 149, 464),
- (1, 176, 149, 613),
- (1, 160, 149, 762),
- (1, 144, 149, 911),
- (1, 128, 149, 1060),
- (1, 112, 114, 1174),
- ]
+ # DISK_ZONES = [
+ # (0, 232, 158, 0),
+ # (0, 216, 158, 158),
+ # (0, 208, 149, 316),
+ # (0, 192, 149, 465),
+ # (0, 176, 149, 614),
+ # (0, 160, 149, 763),
+ # (0, 144, 149, 912),
+ # (0, 128, 114, 1061),
+ # (1, 216, 158, 157),
+ # (1, 208, 158, 315),
+ # (1, 192, 149, 464),
+ # (1, 176, 149, 613),
+ # (1, 160, 149, 762),
+ # (1, 144, 149, 911),
+ # (1, 128, 149, 1060),
+ # (1, 112, 114, 1174),
+ # ]
- DISK_VZONE_TO_PZONE = [
- [0, 1, 2, 9, 8, 3, 4, 5, 6, 7, 15, 14, 13, 12, 11, 10],
- [0, 1, 2, 3, 10, 9, 8, 4, 5, 6, 7, 15, 14, 13, 12, 11],
- [0, 1, 2, 3, 4, 11, 10, 9, 8, 5, 6, 7, 15, 14, 13, 12],
- [0, 1, 2, 3, 4, 5, 12, 11, 10, 9, 8, 6, 7, 15, 14, 13],
- [0, 1, 2, 3, 4, 5, 6, 13, 12, 11, 10, 9, 8, 7, 15, 14],
- [0, 1, 2, 3, 4, 5, 6, 7, 14, 13, 12, 11, 10, 9, 8, 15],
- [0, 1, 2, 3, 4, 5, 6, 7, 15, 14, 13, 12, 11, 10, 9, 8],
- ]
+ # DISK_VZONE_TO_PZONE = [
+ # [0, 1, 2, 9, 8, 3, 4, 5, 6, 7, 15, 14, 13, 12, 11, 10],
+ # [0, 1, 2, 3, 10, 9, 8, 4, 5, 6, 7, 15, 14, 13, 12, 11],
+ # [0, 1, 2, 3, 4, 11, 10, 9, 8, 5, 6, 7, 15, 14, 13, 12],
+ # [0, 1, 2, 3, 4, 5, 12, 11, 10, 9, 8, 6, 7, 15, 14, 13],
+ # [0, 1, 2, 3, 4, 5, 6, 13, 12, 11, 10, 9, 8, 7, 15, 14],
+ # [0, 1, 2, 3, 4, 5, 6, 7, 14, 13, 12, 11, 10, 9, 8, 15],
+ # [0, 1, 2, 3, 4, 5, 6, 7, 15, 14, 13, 12, 11, 10, 9, 8],
+ # ]
- DISK_DRIVE_TYPES = [(
- "development",
- 192,
- [11, 10, 3, 2],
- [0, 1, 8, 9, 16, 17, 18, 19, 20, 21, 22, 23],
- ), (
- "retail",
- 232,
- [9, 8, 1, 0],
- [2, 3, 10, 11, 12, 16, 17, 18, 19, 20, 21, 22, 23],
- )]
+ # DISK_DRIVE_TYPES = [(
+ # "development",
+ # 192,
+ # [11, 10, 3, 2],
+ # [0, 1, 8, 9, 16, 17, 18, 19, 20, 21, 22, 23],
+ # ), (
+ # "retail",
+ # 232,
+ # [9, 8, 1, 0],
+ # [2, 3, 10, 11, 12, 16, 17, 18, 19, 20, 21, 22, 23],
+ # )]
- def __check_system_block(lba: int, sector_size: int, check_disk_type: bool) -> tuple[bool, bytes]:
- handle.seek(lba * DISK_SYSTEM_SECTOR_SIZE * DISK_SECTORS_PER_BLOCK)
- system_block_data = handle.read(sector_size * DISK_SECTORS_PER_BLOCK)
- system_data = system_block_data[:sector_size]
- for sector in range(1, DISK_SECTORS_PER_BLOCK):
- sector_data = system_block_data[(sector * sector_size):][:sector_size]
- if (system_data != sector_data):
- return (False, None)
- if (check_disk_type):
- if (system_data[4] != 0x10):
- return (False, None)
- if ((system_data[5] & 0xF0) != 0x10):
- return (False, None)
- return (True, system_data)
+ # def __check_system_block(lba: int, sector_size: int, check_disk_type: bool) -> tuple[bool, bytes]:
+ # handle.seek(lba * DISK_SYSTEM_SECTOR_SIZE * DISK_SECTORS_PER_BLOCK)
+ # system_block_data = handle.read(sector_size * DISK_SECTORS_PER_BLOCK)
+ # system_data = system_block_data[:sector_size]
+ # for sector in range(1, DISK_SECTORS_PER_BLOCK):
+ # sector_data = system_block_data[(sector * sector_size):][:sector_size]
+ # if (system_data != sector_data):
+ # return (False, None)
+ # if (check_disk_type):
+ # if (system_data[4] != 0x10):
+ # return (False, None)
+ # if ((system_data[5] & 0xF0) != 0x10):
+ # return (False, None)
+ # return (True, system_data)
- disk_drive_type = None
- disk_system_data = None
- disk_id_data = None
- disk_bad_lbas = []
+ # disk_drive_type = None
+ # disk_system_data = None
+ # disk_id_data = None
+ # disk_bad_lbas = []
- drive_index = 0
- while (disk_system_data == None) and (drive_index < len(DISK_DRIVE_TYPES)):
- (drive_type, system_sector_size, system_data_lbas, bad_lbas) = DISK_DRIVE_TYPES[drive_index]
- disk_bad_lbas.clear()
- disk_bad_lbas.extend(bad_lbas)
- for system_lba in system_data_lbas:
- (valid, system_data) = __check_system_block(system_lba, system_sector_size, check_disk_type=True)
- if (valid):
- disk_drive_type = drive_type
- disk_system_data = system_data
- else:
- disk_bad_lbas.append(system_lba)
- drive_index += 1
+ # drive_index = 0
+ # while (disk_system_data == None) and (drive_index < len(DISK_DRIVE_TYPES)):
+ # (drive_type, system_sector_size, system_data_lbas, bad_lbas) = DISK_DRIVE_TYPES[drive_index]
+ # disk_bad_lbas.clear()
+ # disk_bad_lbas.extend(bad_lbas)
+ # for system_lba in system_data_lbas:
+ # (valid, system_data) = __check_system_block(system_lba, system_sector_size, check_disk_type=True)
+ # if (valid):
+ # disk_drive_type = drive_type
+ # disk_system_data = system_data
+ # else:
+ # disk_bad_lbas.append(system_lba)
+ # drive_index += 1
- for id_lba in [15, 14]:
- (valid, id_data) = __check_system_block(id_lba, DISK_SYSTEM_SECTOR_SIZE, check_disk_type=False)
- if (valid):
- disk_id_data = id_data
- else:
- disk_bad_lbas.append(id_lba)
+ # for id_lba in [15, 14]:
+ # (valid, id_data) = __check_system_block(id_lba, DISK_SYSTEM_SECTOR_SIZE, check_disk_type=False)
+ # if (valid):
+ # disk_id_data = id_data
+ # else:
+ # disk_bad_lbas.append(id_lba)
- if not (disk_system_data and disk_id_data):
- raise SC64Exception("Provided 64DD disk file is not valid")
+ # if not (disk_system_data and disk_id_data):
+ # raise SC64Exception("Provided 64DD disk file is not valid")
- disk_zone_bad_tracks = []
+ # disk_zone_bad_tracks = []
- for zone in range(len(DISK_ZONES)):
- zone_bad_tracks = []
- start = 0 if zone == 0 else system_data[0x07 + zone]
- stop = system_data[0x07 + zone + 1]
- for offset in range(start, stop):
- zone_bad_tracks.append(system_data[0x20 + offset])
- for ignored_track in range(DISK_BAD_TRACKS_PER_ZONE - len(zone_bad_tracks)):
- zone_bad_tracks.append(DISK_ZONES[zone][2] - ignored_track - 1)
- disk_zone_bad_tracks.append(zone_bad_tracks)
+ # for zone in range(len(DISK_ZONES)):
+ # zone_bad_tracks = []
+ # start = 0 if zone == 0 else system_data[0x07 + zone]
+ # stop = system_data[0x07 + zone + 1]
+ # for offset in range(start, stop):
+ # zone_bad_tracks.append(system_data[0x20 + offset])
+ # for ignored_track in range(DISK_BAD_TRACKS_PER_ZONE - len(zone_bad_tracks)):
+ # zone_bad_tracks.append(DISK_ZONES[zone][2] - ignored_track - 1)
+ # disk_zone_bad_tracks.append(zone_bad_tracks)
- thb_lba_table = [(0xFFFFFFFF, -1)] * (DISK_HEADS * DISK_TRACKS * DISK_BLOCKS_PER_TRACK)
+ # thb_lba_table = [(0xFFFFFFFF, -1)] * (DISK_HEADS * DISK_TRACKS * DISK_BLOCKS_PER_TRACK)
- disk_type = disk_system_data[5] & 0x0F
+ # disk_type = disk_system_data[5] & 0x0F
- current_lba = 0
- starting_block = 0
- disk_file_offset = 0
+ # current_lba = 0
+ # starting_block = 0
+ # disk_file_offset = 0
- for zone in DISK_VZONE_TO_PZONE[disk_type]:
- (head, sector_size, tracks, track) = DISK_ZONES[zone]
+ # for zone in DISK_VZONE_TO_PZONE[disk_type]:
+ # (head, sector_size, tracks, track) = DISK_ZONES[zone]
- for zone_track in range(tracks):
- current_zone_track = ((tracks - 1) - zone_track) if head else zone_track
+ # for zone_track in range(tracks):
+ # current_zone_track = ((tracks - 1) - zone_track) if head else zone_track
- if (current_zone_track in disk_zone_bad_tracks[zone]):
- track += (-1) if head else 1
- continue
+ # if (current_zone_track in disk_zone_bad_tracks[zone]):
+ # track += (-1) if head else 1
+ # continue
- for block in range(DISK_BLOCKS_PER_TRACK):
- if (current_lba not in disk_bad_lbas):
- index = (track << 2) | (head << 1) | (starting_block ^ block)
- thb_lba_table[index] = (disk_file_offset, current_lba)
- disk_file_offset += sector_size * DISK_SECTORS_PER_BLOCK
- current_lba += 1
+ # for block in range(DISK_BLOCKS_PER_TRACK):
+ # if (current_lba not in disk_bad_lbas):
+ # index = (track << 2) | (head << 1) | (starting_block ^ block)
+ # thb_lba_table[index] = (disk_file_offset, current_lba)
+ # disk_file_offset += sector_size * DISK_SECTORS_PER_BLOCK
+ # current_lba += 1
- track += (-1) if head else 1
- starting_block ^= 1
+ # track += (-1) if head else 1
+ # starting_block ^= 1
- return (disk_drive_type, thb_lba_table)
+ # return (disk_drive_type, thb_lba_table)
- def set_dd_configuration_for_disk(self, file: str = None) -> None:
- if (file):
- with open(file, "rb+") as handle:
- (disk_drive_type, thb_lba_table) = self.__dd_create_configuration(handle)
- thb_table_offset = self.__query_config(self.__CFG_ID_DD_THB_TABLE_OFFSET)
- data = bytearray()
- self.__disk_lba_table = [0xFFFFFFFF] * len(thb_lba_table)
- for (offset, lba) in thb_lba_table:
- data += struct.pack(">I", offset)
- self.__disk_lba_table[lba] = offset
- self.__write_cmd("W", thb_table_offset, len(data))
- self.__write(bytes(data))
- self.__read_cmd_status("W")
- id_mapping = {
- "retail": self.__DD_DRIVE_ID_RETAIL,
- "development": self.__DD_DRIVE_ID_DEVELOPMENT,
- }
- if (disk_drive_type in id_mapping):
- self.__change_config(self.__CFG_ID_DD_DRIVE_ID, id_mapping[disk_drive_type])
- else:
- raise SC64Exception("DD drive type outside of supported values")
- else:
- raise SC64Exception("No DD disk file provided for disk info creation")
+ # def set_dd_configuration_for_disk(self, file: str = None) -> None:
+ # if (file):
+ # with open(file, "rb+") as handle:
+ # (disk_drive_type, thb_lba_table) = self.__dd_create_configuration(handle)
+ # thb_table_offset = self.__query_config(self.__CFG_ID_DD_THB_TABLE_OFFSET)
+ # data = bytearray()
+ # self.__disk_lba_table = [0xFFFFFFFF] * len(thb_lba_table)
+ # for (offset, lba) in thb_lba_table:
+ # data += struct.pack(">I", offset)
+ # self.__disk_lba_table[lba] = offset
+ # self.__write_cmd("W", thb_table_offset, len(data))
+ # self.__write(bytes(data))
+ # self.__read_cmd_status("W")
+ # id_mapping = {
+ # "retail": self.__DD_DRIVE_ID_RETAIL,
+ # "development": self.__DD_DRIVE_ID_DEVELOPMENT,
+ # }
+ # if (disk_drive_type in id_mapping):
+ # self.__change_config(self.__CFG_ID_DD_DRIVE_ID, id_mapping[disk_drive_type])
+ # else:
+ # raise SC64Exception("DD drive type outside of supported values")
+ # else:
+ # raise SC64Exception("No DD disk file provided for disk info creation")
- def __debug_process_fsd_read(self, data: bytes) -> None:
- sector = int.from_bytes(data[0:4], byteorder="little")
- offset = int.from_bytes(data[4:8], byteorder="little")
- count = int.from_bytes(data[8:12], byteorder="little")
+ # def __debug_process_fsd_read(self, data: bytes) -> None:
+ # sector = int.from_bytes(data[0:4], byteorder="little")
+ # offset = int.from_bytes(data[4:8], byteorder="little")
+ # count = int.from_bytes(data[8:12], byteorder="little")
- if (self.__fsd_file):
- self.__fsd_file.seek(sector * 512)
- self.__write_cmd("S", offset, count * 512)
- self.__write(self.__fsd_file.read(count * 512))
- else:
- self.__write_cmd("S", offset, 0)
+ # if (self.__fsd_file):
+ # self.__fsd_file.seek(sector * 512)
+ # self.__write_cmd("S", offset, count * 512)
+ # self.__write(self.__fsd_file.read(count * 512))
+ # else:
+ # self.__write_cmd("S", offset, 0)
- def __debug_process_fsd_write(self, data: bytes) -> None:
- sector = int.from_bytes(data[0:4], byteorder="little")
- offset = int.from_bytes(data[4:8], byteorder="little")
- count = int.from_bytes(data[8:12], byteorder="little")
+ # def __debug_process_fsd_write(self, data: bytes) -> None:
+ # sector = int.from_bytes(data[0:4], byteorder="little")
+ # offset = int.from_bytes(data[4:8], byteorder="little")
+ # count = int.from_bytes(data[8:12], byteorder="little")
- if (self.__fsd_file):
- with helpers.lock_volume(self.__fsd_file):
- self.__fsd_file.seek(sector * 512)
- self.__write_cmd("L", offset, count * 512)
- self.__fsd_file.write(self.__read(count * 512))
- else:
- self.__write_cmd("L", offset, 0)
+ # if (self.__fsd_file):
+ # with helpers.lock_volume(self.__fsd_file):
+ # self.__fsd_file.seek(sector * 512)
+ # self.__write_cmd("L", offset, count * 512)
+ # self.__fsd_file.write(self.__read(count * 512))
+ # else:
+ # self.__write_cmd("L", offset, 0)
- def __debug_process_dd_block(self, data: bytes) -> None:
- transfer_mode = int.from_bytes(data[0:4], byteorder="little")
- sdram_offset = int.from_bytes(data[4:8], byteorder="little")
- disk_file_offset = int.from_bytes(data[8:12], byteorder="big")
- block_length = int.from_bytes(data[12:16], byteorder="little")
- print(f"DD BLOCK {disk_file_offset:08X} {block_length}")
- if (self.__disk_file):
- self.__disk_file.seek(disk_file_offset)
- if (transfer_mode):
- if (not self.__dd_turbo):
- # Fixes weird bug in Mario Artist Paint Studio prototype minigame
- time.sleep(0.016)
- self.__write_cmd("S", sdram_offset, block_length)
- self.__write(self.__disk_file.read(block_length))
- else:
- self.__write_cmd("L", sdram_offset, block_length)
- self.__disk_file.write(self.__read(block_length))
+ # def __debug_process_dd_block(self, data: bytes) -> None:
+ # transfer_mode = int.from_bytes(data[0:4], byteorder="little")
+ # sdram_offset = int.from_bytes(data[4:8], byteorder="little")
+ # disk_file_offset = int.from_bytes(data[8:12], byteorder="big")
+ # block_length = int.from_bytes(data[12:16], byteorder="little")
+ # print(f"DD BLOCK {disk_file_offset:08X} {block_length}")
+ # if (self.__disk_file):
+ # self.__disk_file.seek(disk_file_offset)
+ # if (transfer_mode):
+ # if (not self.__dd_turbo):
+ # # Fixes weird bug in Mario Artist Paint Studio prototype minigame
+ # time.sleep(0.016)
+ # self.__write_cmd("S", sdram_offset, block_length)
+ # self.__write(self.__disk_file.read(block_length))
+ # else:
+ # self.__write_cmd("L", sdram_offset, block_length)
+ # self.__disk_file.write(self.__read(block_length))
- def __debug_process_is_viewer(self, data: bytes) -> None:
- length = int.from_bytes(data[0:4], byteorder="little")
- address = int.from_bytes(data[4:8], byteorder="little")
- self.__write_cmd("L", address, length)
- text = self.__read(length)
- print(text.decode("EUC-JP", errors="backslashreplace"), end="")
+ # def __debug_process_is_viewer(self, data: bytes) -> None:
+ # length = int.from_bytes(data[0:4], byteorder="little")
+ # address = int.from_bytes(data[4:8], byteorder="little")
+ # self.__write_cmd("L", address, length)
+ # text = self.__read(length)
+ # print(text.decode("EUC-JP", errors="backslashreplace"), end="")
- def debug_init(self, fsd_file: str = None, disk_file: str = None, dd_turbo: bool = False) -> None:
- if (fsd_file):
- self.__fsd_file = open(fsd_file, "rb+")
- if (disk_file):
- self.__disk_file = open(disk_file, "rb+")
- self.__dd_turbo = dd_turbo
+ # def debug_init(self, fsd_file: str = None, disk_file: str = None, dd_turbo: bool = False) -> None:
+ # if (fsd_file):
+ # self.__fsd_file = open(fsd_file, "rb+")
+ # if (disk_file):
+ # self.__disk_file = open(disk_file, "rb+")
+ # self.__dd_turbo = dd_turbo
- def debug_loop(self, is_viewer_enabled: bool = False) -> None:
- self.__change_config(self.__CFG_ID_IS_VIEWER_ENABLE, is_viewer_enabled)
+ # def debug_loop(self, is_viewer_enabled: bool = False) -> None:
+ # self.__change_config(self.__CFG_ID_IS_VIEWER_ENABLE, is_viewer_enabled)
- print("\r\n\033[34m --- Debug server started --- \033[0m\r\n")
+ # print("\r\n\033[34m --- Debug server started --- \033[0m\r\n")
- start_indicator = bytearray()
- dropped_bytes = 0
+ # start_indicator = bytearray()
+ # dropped_bytes = 0
- while (True):
- while (start_indicator != b"DMA@"):
- start_indicator.append(self.__read_long(1)[0])
- if (len(start_indicator) > 4):
- dropped_bytes += 1
- start_indicator.pop(0)
- start_indicator.clear()
+ # while (True):
+ # while (start_indicator != b"DMA@"):
+ # start_indicator.append(self.__read_long(1)[0])
+ # if (len(start_indicator) > 4):
+ # dropped_bytes += 1
+ # start_indicator.pop(0)
+ # start_indicator.clear()
- if (dropped_bytes):
- print(f"\033[35mWarning - dropped {dropped_bytes} bytes from stream\033[0m", file=sys.stderr)
- dropped_bytes = 0
+ # if (dropped_bytes):
+ # print(f"\033[35mWarning - dropped {dropped_bytes} bytes from stream\033[0m", file=sys.stderr)
+ # dropped_bytes = 0
- header = self.__read_long(4)
- id = int(header[0])
- length = int.from_bytes(header[1:4], byteorder="big")
- data = self.__read_long(length)
- self.__read_long(self.__align(length, 4) - length)
- end_indicator = self.__read_long(4)
+ # header = self.__read_long(4)
+ # id = int(header[0])
+ # length = int.from_bytes(header[1:4], byteorder="big")
+ # data = self.__read_long(length)
+ # self.__read_long(self.__align(length, 4) - length)
+ # end_indicator = self.__read_long(4)
- if (end_indicator != b"CMPH"):
- print(f"\033[35mGot unknown end indicator: {end_indicator.decode(encoding='ascii', errors='backslashreplace')}\033[0m", file=sys.stderr)
- else:
- if (id == self.__DEBUG_ID_TEXT):
- print(data.decode(encoding="ascii", errors="backslashreplace"), end="")
- elif (id == self.__EVENT_ID_FSD_READ):
- self.__debug_process_fsd_read(data)
- elif (id == self.__EVENT_ID_FSD_WRITE):
- self.__debug_process_fsd_write(data)
- elif (id == self.__EVENT_ID_DD_BLOCK):
- self.__debug_process_dd_block(data)
- elif (id == self.__EVENT_ID_IS_VIEWER):
- self.__debug_process_is_viewer(data)
- else:
- print(f"\033[35mGot unknown id: {id}, length: {length}\033[0m", file=sys.stderr)
+ # if (end_indicator != b"CMPH"):
+ # print(f"\033[35mGot unknown end indicator: {end_indicator.decode(encoding='ascii', errors='backslashreplace')}\033[0m", file=sys.stderr)
+ # else:
+ # if (id == self.__DEBUG_ID_TEXT):
+ # print(data.decode(encoding="ascii", errors="backslashreplace"), end="")
+ # elif (id == self.__EVENT_ID_FSD_READ):
+ # self.__debug_process_fsd_read(data)
+ # elif (id == self.__EVENT_ID_FSD_WRITE):
+ # self.__debug_process_fsd_write(data)
+ # elif (id == self.__EVENT_ID_DD_BLOCK):
+ # self.__debug_process_dd_block(data)
+ # elif (id == self.__EVENT_ID_IS_VIEWER):
+ # self.__debug_process_is_viewer(data)
+ # else:
+ # print(f"\033[35mGot unknown id: {id}, length: {length}\033[0m", file=sys.stderr)
@@ -768,16 +833,17 @@ if __name__ == "__main__":
with SC64ProgressBar(sc64):
if (update_file):
- if (is_read):
- sc64.backup_firmware(update_file)
- else:
- sc64.backup_firmware(firmware_backup_file)
- if (not filecmp.cmp(update_file, firmware_backup_file)):
- print("Update file different than contents of flash - updating SummerCart64")
- sc64.update_firmware(update_file)
- else:
- print("SummerCart64 is already updated to latest version")
- os.remove(firmware_backup_file)
+ sc64.upload_bootloader(update_file)
+ # if (is_read):
+ # sc64.backup_firmware(update_file)
+ # else:
+ # sc64.backup_firmware(firmware_backup_file)
+ # if (not filecmp.cmp(update_file, firmware_backup_file)):
+ # print("Update file different than contents of flash - updating SummerCart64")
+ # sc64.update_firmware(update_file)
+ # else:
+ # print("SummerCart64 is already updated to latest version")
+ # os.remove(firmware_backup_file)
if (rtc):
now = datetime.now()
@@ -806,7 +872,7 @@ if __name__ == "__main__":
sc64.set_dd_enable(dd_enable)
if (rom_file):
- if (is_read):
+ if (is_read):
if (rom_length > 0):
sc64.download_rom(rom_file, rom_length)
else:
@@ -826,27 +892,27 @@ if __name__ == "__main__":
else:
sc64.upload_save(save_file)
- if (debug_server):
- sc64.debug_init(sd_file, disk_file, dd_turbo)
- if (is_viewer_enabled):
- print(f"Setting IS-Viewer 64 emulation to [Enabled]")
- if (sd_file):
- print(f"Using fake SD emulation file [{sd_file}]")
- if (disk_file):
- print(f"Using 64DD disk image file [{disk_file}]")
- sc64.set_dd_configuration_for_disk(disk_file)
- print(f"Setting 64DD disk state to [Inserted]")
- sc64.set_dd_disk_state("inserted" if disk_file else "ejected")
- sc64.debug_loop(is_viewer_enabled)
+ # if (debug_server):
+ # sc64.debug_init(sd_file, disk_file, dd_turbo)
+ # if (is_viewer_enabled):
+ # print(f"Setting IS-Viewer 64 emulation to [Enabled]")
+ # if (sd_file):
+ # print(f"Using fake SD emulation file [{sd_file}]")
+ # if (disk_file):
+ # print(f"Using 64DD disk image file [{disk_file}]")
+ # sc64.set_dd_configuration_for_disk(disk_file)
+ # print(f"Setting 64DD disk state to [Inserted]")
+ # sc64.set_dd_disk_state("inserted" if disk_file else "ejected")
+ # sc64.debug_loop(is_viewer_enabled)
except SC64Exception as e:
print(f"Error: {e}")
parser.exit(1)
except KeyboardInterrupt:
pass
- finally:
- if (sc64):
- if (disk_file):
- print(f"Setting 64DD disk state to [Ejected]")
- sc64.set_dd_disk_state("ejected")
- sys.stdout.write("\033[0m")
+ # finally:
+ # if (sc64):
+ # if (disk_file):
+ # print(f"Setting 64DD disk state to [Ejected]")
+ # sc64.set_dd_disk_state("ejected")
+ # sys.stdout.write("\033[0m")
diff --git a/sw/riscv/.gitignore b/sw/riscv/.gitignore
deleted file mode 100644
index 3543521..0000000
--- a/sw/riscv/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/build
diff --git a/sw/riscv/SC64.ld b/sw/riscv/SC64.ld
deleted file mode 100644
index c71e22b..0000000
--- a/sw/riscv/SC64.ld
+++ /dev/null
@@ -1,49 +0,0 @@
-MEMORY {
- rom (rx) : org = 0x00010000, len = 26k
- ram (rwx) : org = 0x10000000, len = 16k
-}
-
-ENTRY(reset_handler)
-
-SECTIONS {
- .text.reset_handler : {
- *(.text.reset_handler)
- } > rom
-
- .text : {
- _sitext = LOADADDR(.text);
- . = ALIGN(4);
- _stext = .;
- *(.text .text.* .gnu.linkonce.t.*)
- *(.rodata .rodata.* .gnu.linkonce.r.*)
- . = ALIGN(4);
- _etext = .;
- } > ram AT > rom
-
- .data : {
- _sidata = LOADADDR(.data);
- . = ALIGN(4);
- _sdata = .;
- *(.data .data.* .gnu.linkonce.d.*)
- . = ALIGN(4);
- _ssdata = .;
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- . = ALIGN(4);
- _edata = .;
- } > ram AT > rom
-
- .bss : {
- . = ALIGN(4);
- _sbss = .;
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon .scommon.*)
- *(.bss .bss.* .gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = .;
- } > ram
-
- __global_pointer$ = MIN(_ssdata + 0x800, MAX(_sdata + 0x800, _ebss - 0x800));
- __stack_pointer$ = ORIGIN(ram) + LENGTH(ram);
-}
diff --git a/sw/riscv/src/cfg.c b/sw/riscv/src/cfg.c
deleted file mode 100644
index a59326f..0000000
--- a/sw/riscv/src/cfg.c
+++ /dev/null
@@ -1,356 +0,0 @@
-#include "cfg.h"
-#include "dd.h"
-#include "flash.h"
-#include "isv.h"
-#include "joybus.h"
-#include "rtc.h"
-#include "uart.h"
-#include "usb.h"
-
-
-enum cfg_id {
- CFG_ID_SCR,
- CFG_ID_SDRAM_SWITCH,
- CFG_ID_SDRAM_WRITABLE,
- CFG_ID_DD_ENABLE,
- CFG_ID_SAVE_TYPE,
- CFG_ID_CIC_SEED,
- CFG_ID_TV_TYPE,
- CFG_ID_SAVE_OFFEST,
- CFG_ID_DDIPL_OFFEST,
- CFG_ID_BOOT_MODE,
- CFG_ID_FLASH_SIZE,
- CFG_ID_FLASH_READ,
- CFG_ID_FLASH_PROGRAM,
- CFG_ID_RECONFIGURE,
- CFG_ID_DD_DRIVE_ID,
- CFG_ID_DD_DISK_STATE,
- CFG_ID_DD_THB_TABLE_OFFSET,
- CFG_ID_IS_VIEWER_ENABLE,
-};
-
-enum save_type {
- SAVE_TYPE_NONE = 0,
- SAVE_TYPE_EEPROM_4K = 1,
- SAVE_TYPE_EEPROM_16K = 2,
- SAVE_TYPE_SRAM = 3,
- SAVE_TYPE_FLASHRAM = 4,
- SAVE_TYPE_SRAM_BANKED = 5,
- SAVE_TYPE_FLASHRAM_PKST2 = 6,
-};
-
-enum boot_mode {
- BOOT_MODE_MENU_SD = 0,
- BOOT_MODE_MENU_USB = 1,
- BOOT_MODE_ROM = 2,
- BOOT_MODE_DD = 3,
- BOOT_MODE_DIRECT = 4,
-};
-
-
-struct process {
- enum save_type save_type;
- uint16_t cic_seed;
- uint8_t tv_type;
- enum boot_mode boot_mode;
- bool usb_drive_busy;
-};
-
-static struct process p;
-
-
-static void change_scr_bits (uint32_t mask, bool value) {
- if (value) {
- CFG->SCR |= mask;
- } else {
- CFG->SCR &= ~(mask);
- }
-}
-
-static void set_usb_drive_not_busy (void) {
- p.usb_drive_busy = false;
-}
-
-static void set_save_type (enum save_type save_type) {
- change_scr_bits(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, false);
- joybus_set_eeprom(EEPROM_NONE);
-
- switch (save_type) {
- case SAVE_TYPE_NONE:
- break;
- case SAVE_TYPE_EEPROM_4K:
- joybus_set_eeprom(EEPROM_4K);
- break;
- case SAVE_TYPE_EEPROM_16K:
- joybus_set_eeprom(EEPROM_16K);
- break;
- case SAVE_TYPE_SRAM:
- change_scr_bits(CFG_SCR_SRAM_EN, true);
- break;
- case SAVE_TYPE_FLASHRAM:
- change_scr_bits(CFG_SCR_FLASHRAM_EN, true);
- break;
- case SAVE_TYPE_SRAM_BANKED:
- change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, true);
- break;
- default:
- save_type = SAVE_TYPE_NONE;
- break;
- }
-
- p.save_type = save_type;
-}
-
-
-uint32_t cfg_get_version (void) {
- return CFG->VERSION;
-}
-
-void cfg_query (uint32_t *args) {
- switch (args[0]) {
- case CFG_ID_SCR:
- args[1] = CFG->SCR;
- break;
- case CFG_ID_SDRAM_SWITCH:
- args[1] = CFG->SCR & CFG_SCR_SDRAM_SWITCH;
- break;
- case CFG_ID_SDRAM_WRITABLE:
- args[1] = CFG->SCR & CFG_SCR_SDRAM_WRITABLE;
- break;
- case CFG_ID_DD_ENABLE:
- args[1] = CFG->SCR & CFG_SCR_DD_EN;
- break;
- case CFG_ID_SAVE_TYPE:
- args[1] = (uint32_t) (p.save_type);
- break;
- case CFG_ID_CIC_SEED:
- args[1] = (uint32_t) (p.cic_seed);
- break;
- case CFG_ID_TV_TYPE:
- args[1] = (uint32_t) (p.tv_type);
- break;
- case CFG_ID_SAVE_OFFEST:
- args[1] = SAVE_OFFSET;
- break;
- case CFG_ID_DDIPL_OFFEST:
- args[1] = DDIPL_OFFSET;
- break;
- case CFG_ID_BOOT_MODE:
- args[1] = p.boot_mode;
- break;
- case CFG_ID_FLASH_SIZE:
- args[1] = flash_size();
- break;
- case CFG_ID_RECONFIGURE:
- args[1] = CFG->RECONFIGURE;
- break;
- case CFG_ID_DD_DISK_STATE:
- args[1] = dd_get_disk_state();
- break;
- case CFG_ID_DD_DRIVE_ID:
- args[1] = dd_get_drive_id();
- break;
- case CFG_ID_DD_THB_TABLE_OFFSET:
- args[1] = dd_get_thb_table_offset();
- break;
- case CFG_ID_IS_VIEWER_ENABLE:
- args[1] = isv_get_enabled();
- break;
- }
-}
-
-void cfg_update (uint32_t *args) {
- switch (args[0]) {
- case CFG_ID_SCR:
- CFG->SCR = args[1];
- break;
- case CFG_ID_SDRAM_SWITCH:
- change_scr_bits(CFG_SCR_SDRAM_SWITCH, args[1]);
- break;
- case CFG_ID_SDRAM_WRITABLE:
- change_scr_bits(CFG_SCR_SDRAM_WRITABLE, args[1]);
- break;
- case CFG_ID_DD_ENABLE:
- change_scr_bits(CFG_SCR_DD_EN, args[1]);
- break;
- case CFG_ID_SAVE_TYPE:
- set_save_type((enum save_type) (args[1]));
- break;
- case CFG_ID_CIC_SEED:
- p.cic_seed = (uint16_t) (args[1] & 0xFFFF);
- break;
- case CFG_ID_TV_TYPE:
- p.tv_type = (uint8_t) (args[1] & 0x03);
- break;
- case CFG_ID_SAVE_OFFEST:
- break;
- case CFG_ID_DDIPL_OFFEST:
- break;
- case CFG_ID_BOOT_MODE:
- p.boot_mode = args[1];
- change_scr_bits(CFG_SCR_SKIP_BOOTLOADER, args[1] == BOOT_MODE_DIRECT);
- break;
- case CFG_ID_FLASH_READ:
- flash_read(args[1]);
- break;
- case CFG_ID_FLASH_PROGRAM:
- flash_program(args[1]);
- break;
- case CFG_ID_RECONFIGURE:
- if (args[1] == CFG->RECONFIGURE) {
- CFG->RECONFIGURE = args[1];
- asm volatile (
- "ebreak \n"
- );
- }
- break;
- case CFG_ID_DD_DISK_STATE:
- dd_set_disk_state(args[1]);
- break;
- case CFG_ID_DD_DRIVE_ID:
- dd_set_drive_id((uint16_t) (args[1]));
- break;
- case CFG_ID_DD_THB_TABLE_OFFSET:
- break;
- case CFG_ID_IS_VIEWER_ENABLE:
- isv_set_enabled(args[1]);
- break;
- }
-}
-
-void cfg_get_time (uint32_t *args) {
- rtc_time_t *t = rtc_get_time();
- args[0] = ((t->hour << 16) | (t->minute << 8) | t->second);
- args[1] = ((t->weekday << 24) | (t->year << 16) | (t->month << 8) | t->day);
-}
-
-void cfg_set_time (uint32_t *args) {
- rtc_time_t t;
- t.second = (args[0] & 0xFF);
- t.minute = ((args[0] >> 8) & 0xFF);
- t.hour = ((args[0] >> 16) & 0xFF);
- t.weekday = ((args[1] >> 24) & 0xFF);
- t.day = (args[1] & 0xFF);
- t.month = ((args[1] >> 8) & 0xFF);
- t.year = ((args[1] >> 16) & 0xFF);
- rtc_set_time(&t);
-}
-
-
-void cfg_init (void) {
- set_save_type(SAVE_TYPE_NONE);
-
- CFG->SCR = CFG_SCR_CPU_READY;
-
- p.cic_seed = 0xFFFF;
- p.tv_type = 0x03;
- p.boot_mode = BOOT_MODE_MENU_SD;
- p.usb_drive_busy = false;
-}
-
-
-void process_cfg (void) {
- uint32_t args[2];
-
- if (CFG->SCR & CFG_SCR_CPU_BUSY) {
- change_scr_bits(CFG_SCR_CMD_ERROR, false);
-
- args[0] = CFG->DATA[0];
- args[1] = CFG->DATA[1];
-
- switch (CFG->CMD) {
- case 'V':
- args[0] = cfg_get_version();
- break;
-
- case 'Q':
- cfg_query(args);
- break;
-
- case 'C':
- cfg_update(args);
- break;
-
- case 0xEE:
- cfg_get_time(args);
- break;
-
- case 0xEF:
- cfg_set_time(args);
- break;
-
- case 0xF0:
- if (args[0] & (1 << 31)) {
- p.usb_drive_busy = false;
- } else {
- change_scr_bits(CFG_SCR_CMD_ERROR, true);
- }
- break;
-
- case 0xF1:
- if (args[0] & (1 << 31)) {
- args[0] = p.usb_drive_busy;
- } else {
- args[0] = 0;
- change_scr_bits(CFG_SCR_CMD_ERROR, true);
- }
- args[1] = 0;
- break;
-
- case 0xF2:
- if (args[0] & (1 << 31)) {
- if (!p.usb_drive_busy) {
- usb_event_t event;
- event.id = EVENT_ID_FSD_READ;
- event.trigger = CALLBACK_SDRAM_WRITE;
- event.callback = set_usb_drive_not_busy;
- uint32_t data[3] = { args[1], (args[0] & 0x7FFFFFFF), 1 };
- if (usb_put_event(&event, data, sizeof(data))) {
- p.usb_drive_busy = true;
- } else {
- return;
- }
- } else {
- change_scr_bits(CFG_SCR_CMD_ERROR, true);
- }
- } else {
- change_scr_bits(CFG_SCR_CMD_ERROR, true);
- }
- break;
-
- case 0xF3:
- if (args[0] & (1 << 31)) {
- if (!p.usb_drive_busy) {
- usb_event_t event;
- event.id = EVENT_ID_FSD_WRITE;
- event.trigger = CALLBACK_SDRAM_READ;
- event.callback = set_usb_drive_not_busy;
- uint32_t data[3] = { args[1], (args[0] & 0x7FFFFFFF), 1 };
- if (usb_put_event(&event, data, sizeof(data))) {
- p.usb_drive_busy = true;
- } else {
- return;
- }
- } else {
- change_scr_bits(CFG_SCR_CMD_ERROR, true);
- }
- } else {
- change_scr_bits(CFG_SCR_CMD_ERROR, true);
- }
- break;
-
- case 0xFF:
- uart_put((char) (args[0] & 0xFF));
- break;
-
- default:
- change_scr_bits(CFG_SCR_CMD_ERROR, true);
- break;
- }
-
- CFG->DATA[0] = args[0];
- CFG->DATA[1] = args[1];
-
- change_scr_bits(CFG_SCR_CPU_BUSY, false);
- }
-}
diff --git a/sw/riscv/src/dd.c b/sw/riscv/src/dd.c
deleted file mode 100644
index 376b07a..0000000
--- a/sw/riscv/src/dd.c
+++ /dev/null
@@ -1,446 +0,0 @@
-#include "dd.h"
-#include "rtc.h"
-#include "usb.h"
-
-
-#define DD_USER_SECTORS_PER_BLOCK (85)
-
-#define DD_BUFFERS_OFFSET (SDRAM_BASE + 0x07E5A7F8UL)
-#define DD_STORAGE_TABLE_OFFSET (DD_BUFFERS_OFFSET + 0x00000000UL)
-#define DD_THB_TABLE_OFFSET (DD_BUFFERS_OFFSET + 0x0007BD90UL)
-#define DD_BLOCK_BUFFER_OFFSET (DD_BUFFERS_OFFSET + 0x00080700UL)
-
-#define USB_DEBUG_ID_DD_BLOCK (0xF5)
-
-#define DD_DRIVE_ID_RETAIL (0x0003)
-#define DD_DRIVE_ID_DEVELOPMENT (0x0004)
-#define DD_VERSION_RETAIL (0x0114)
-
-#define DD_POWER_UP_DELAY_TICKS (200000000UL) // 2 s
-#define DD_TRACK_SEEK_TIME_TICKS (10000) // 0.1 ms
-
-
-typedef enum {
- DD_CMD_SEEK_READ = 0x01,
- DD_CMD_SEEK_WRITE = 0x02,
- DD_CMD_CLEAR_DISK_CHANGE = 0x08,
- DD_CMD_CLEAR_RESET_STATE = 0x09,
- DD_CMD_READ_VERSION = 0x0A,
- DD_CMD_SET_DISK_TYPE = 0x0B,
- DD_CMD_REQUEST_STATUS = 0x0C,
- DD_CMD_SET_RTC_YEAR_MONTH = 0x0F,
- DD_CMD_SET_RTC_DAY_HOUR = 0x10,
- DD_CMD_SET_RTC_MINUTE_SECOND = 0x11,
- DD_CMD_GET_RTC_YEAR_MONTH = 0x12,
- DD_CMD_GET_RTC_DAY_HOUR = 0x13,
- DD_CMD_GET_RTC_MINUTE_SECOND = 0x14,
- DD_CMD_READ_PROGRAM_VERSION = 0x1B,
-} dd_cmd_t;
-
-
-enum state {
- STATE_IDLE,
- STATE_START,
- STATE_BLOCK_READ,
- STATE_BLOCK_READ_WAIT,
- STATE_SECTOR_READ,
- STATE_SECTOR_WRITE,
- STATE_BLOCK_WRITE,
- STATE_BLOCK_WRITE_WAIT,
- STATE_NEXT_BLOCK,
- STATE_STOP,
-};
-
-struct process {
- enum state state;
- uint32_t track_seek_time;
- uint32_t next_seek_time;
- bool power_up_delay;
- bool deffered_cmd_ready;
- bool bm_running;
- bool transfer_mode;
- bool full_track_transfer;
- bool starting_block;
- uint8_t current_sector;
- rtc_time_t time;
- io32_t *thb_table;
- io32_t *block_buffer;
- bool block_ready;
-};
-
-static struct process p;
-
-
-static uint16_t dd_track_head_block (void) {
- uint32_t head_track = DD->HEAD_TRACK;
- uint16_t track = ((head_track & DD_TRACK_MASK) << 2);
- uint16_t head = (((head_track & DD_HEAD_MASK) ? 1 : 0) << 1);
- uint16_t block = (p.starting_block ? 1 : 0);
-
- return (track | head | block);
-}
-
-static bool dd_block_valid (void) {
- return (p.thb_table[dd_track_head_block()] != 0xFFFFFFFF);
-}
-
-static void dd_set_block_ready (void) {
- p.block_ready = true;
-}
-
-static bool dd_block_request (void) {
-if (!(DD->SCR & DD_SCR_DISK_INSERTED)) {
- return true;
- }
-
- io32_t offset = p.thb_table[dd_track_head_block()];
- uint32_t length = ((DD->SECTOR_SIZE + 1) * DD_USER_SECTORS_PER_BLOCK);
-
- uint32_t data[4] = {
- p.transfer_mode,
- (uint32_t) (p.block_buffer),
- offset,
- length,
- };
-
- usb_event_t event;
- event.id = EVENT_ID_DD_BLOCK;
- event.trigger = p.transfer_mode ? CALLBACK_SDRAM_WRITE : CALLBACK_SDRAM_READ;
- event.callback = dd_set_block_ready;
-
- if (usb_put_event(&event, data, sizeof(data))) {
- p.block_ready = false;
- return true;
- }
-
- return false;
-}
-
-static bool dd_block_ready (void) {
- if (!(DD->SCR & DD_SCR_DISK_INSERTED)) {
- return true;
- }
-
- return p.block_ready;
-}
-
-static void dd_sector_read (void) {
- io32_t *src = p.block_buffer;
- io32_t *dst = DD->SECTOR_BUFFER;
-
- uint8_t sector_size = ((DD->SECTOR_SIZE + 1) / sizeof(io32_t));
-
- src += (sector_size * p.current_sector);
-
- for (int i = 0; i < sector_size; i++) {
- *dst++ = *src++;
- }
-}
-
-static void dd_sector_write (void) {
- io32_t *src = DD->SECTOR_BUFFER;
- io32_t *dst = p.block_buffer;
-
- uint8_t sector_size = ((DD->SECTOR_SIZE + 1) / sizeof(io32_t));
-
- dst += (sector_size * p.current_sector);
-
- for (int i = 0; i < sector_size; i++) {
- *dst++ = *src++;
- }
-}
-
-
-void dd_set_disk_state (disk_state_t disk_state) {
- uint32_t scr = (DD->SCR & (~(DD_SCR_DISK_CHANGED | DD_SCR_DISK_INSERTED)));
-
- switch (disk_state) {
- case DD_DISK_EJECTED:
- break;
- case DD_DISK_INSERTED:
- scr |= DD_SCR_DISK_INSERTED;
- break;
- case DD_DISK_CHANGED:
- scr |= (DD_SCR_DISK_CHANGED | DD_SCR_DISK_INSERTED);
- break;
- }
-
- DD->SCR = scr;
-}
-
-disk_state_t dd_get_disk_state (void) {
- uint32_t scr = (DD->SCR & (DD_SCR_DISK_CHANGED | DD_SCR_DISK_INSERTED));
-
- if (scr == (DD_SCR_DISK_CHANGED | DD_SCR_DISK_INSERTED)) {
- return DD_DISK_CHANGED;
- } else if (scr == DD_SCR_DISK_INSERTED) {
- return DD_DISK_INSERTED;
- } else {
- return DD_DISK_EJECTED;
- }
-}
-
-void dd_set_drive_id (uint16_t id) {
- DD->DRIVE_ID = id;
-}
-
-uint16_t dd_get_drive_id (void) {
- return DD->DRIVE_ID;
-}
-
-uint32_t dd_get_thb_table_offset (void) {
- return (((uint32_t) (p.thb_table)) & 0x0FFFFFFF);
-}
-
-
-void dd_init (void) {
- DD->SCR = 0;
- DD->HEAD_TRACK = 0;
- DD->DRIVE_ID = DD_DRIVE_ID_RETAIL;
- p.state = STATE_IDLE;
- p.track_seek_time = DD_TRACK_SEEK_TIME_TICKS;
- p.power_up_delay = true;
- p.deffered_cmd_ready = false;
- p.bm_running = false;
- p.thb_table = (io32_t *) (DD_THB_TABLE_OFFSET);
- p.block_buffer = (io32_t *) (DD_BLOCK_BUFFER_OFFSET);
-}
-
-
-void process_dd (void) {
- uint32_t scr = DD->SCR;
-
- if (scr & DD_SCR_HARD_RESET) {
- DD->SCR &= ~(DD_SCR_DISK_CHANGED);
- DD->HEAD_TRACK = 0;
- p.state = STATE_IDLE;
- p.power_up_delay = true;
- p.deffered_cmd_ready = false;
- p.bm_running = false;
- }
-
- if (scr & DD_SCR_CMD_PENDING) {
- dd_cmd_t cmd = DD->CMD;
- uint16_t data = DD->DATA;
-
- DD->DATA = data;
-
- if (p.deffered_cmd_ready) {
- if (DD->SEEK_TIMER >= p.next_seek_time) {
- p.deffered_cmd_ready = false;
- DD->HEAD_TRACK = DD_HEAD_TRACK_INDEX_LOCK | data;
- DD->SCR |= DD_SCR_CMD_READY;
- }
- } else if ((cmd == DD_CMD_SEEK_READ) || (cmd == DD_CMD_SEEK_WRITE)) {
- int track_distance = abs((DD->HEAD_TRACK & DD_TRACK_MASK) - (data & DD_TRACK_MASK));
- if (p.power_up_delay) {
- p.power_up_delay = false;
- p.next_seek_time = DD_POWER_UP_DELAY_TICKS;
- } else {
- p.next_seek_time = (track_distance * p.track_seek_time);
- }
- p.deffered_cmd_ready = true;
- DD->HEAD_TRACK &= ~(DD_HEAD_TRACK_INDEX_LOCK);
- DD->SCR |= DD_SCR_SEEK_TIMER_RESET;
- } else {
- switch (cmd) {
- case DD_CMD_CLEAR_DISK_CHANGE:
- DD->SCR &= ~(DD_SCR_DISK_CHANGED);
- break;
-
- case DD_CMD_CLEAR_RESET_STATE:
- DD->SCR &= ~(DD_SCR_DISK_CHANGED);
- DD->SCR |= DD_SCR_HARD_RESET_CLEAR;
- break;
-
- case DD_CMD_READ_VERSION:
- DD->DATA = DD_VERSION_RETAIL;
- break;
-
- case DD_CMD_SET_DISK_TYPE:
- break;
-
- case DD_CMD_REQUEST_STATUS:
- DD->DATA = 0;
- break;
-
- case DD_CMD_SET_RTC_YEAR_MONTH:
- p.time.year = ((data >> 8) & 0xFF);
- p.time.month = (data & 0xFF);
- break;
-
- case DD_CMD_SET_RTC_DAY_HOUR:
- p.time.day = ((data >> 8) & 0xFF);
- p.time.hour = (data & 0xFF);
- break;
-
- case DD_CMD_SET_RTC_MINUTE_SECOND:
- p.time.minute = ((data >> 8) & 0xFF);
- p.time.second = (data & 0xFF);
- rtc_set_time(&p.time);
- break;
-
- case DD_CMD_GET_RTC_YEAR_MONTH:
- DD->DATA = ((p.time.year << 8) | p.time.month);
- break;
-
- case DD_CMD_GET_RTC_DAY_HOUR:
- DD->DATA = ((p.time.day << 8) | p.time.hour);
- break;
-
- case DD_CMD_GET_RTC_MINUTE_SECOND:
- p.time = *rtc_get_time();
- DD->DATA = ((p.time.minute << 8) | p.time.second);
- break;
-
- case DD_CMD_READ_PROGRAM_VERSION:
- DD->DATA = 0;
- break;
-
- default:
- break;
- }
-
- DD->SCR |= DD_SCR_CMD_READY;
- }
- } else {
- if (scr & DD_SCR_BM_STOP) {
- DD->SCR |= DD_SCR_BM_STOP_CLEAR;
- DD->SCR &= ~(DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA);
- p.state = STATE_STOP;
- } else if (scr & DD_SCR_BM_START) {
- DD->SCR |= DD_SCR_BM_CLEAR | DD_SCR_BM_ACK_CLEAR | DD_SCR_BM_START_CLEAR;
- DD->SCR &= ~(DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA);
- p.state = STATE_START;
- p.transfer_mode = (scr & DD_SCR_BM_TRANSFER_MODE);
- p.full_track_transfer = (scr & DD_SCR_BM_TRANSFER_BLOCKS);
- p.starting_block = (DD->SECTOR_NUM == (DD->SECTORS_IN_BLOCK + 1));
- } else if (p.bm_running) {
- if (scr & DD_SCR_BM_PENDING) {
- DD->SCR |= DD_SCR_BM_CLEAR;
- if (p.transfer_mode) {
- if (p.current_sector < (DD->SECTORS_IN_BLOCK - 4)) {
- p.state = STATE_SECTOR_READ;
- } else if (p.current_sector == (DD->SECTORS_IN_BLOCK - 4)) {
- p.current_sector += 1;
- DD->SCR &= ~(DD_SCR_BM_TRANSFER_DATA);
- DD->SCR |= DD_SCR_BM_READY;
- } else if (p.current_sector == DD->SECTORS_IN_BLOCK) {
- p.state = STATE_NEXT_BLOCK;
- }
- } else {
- if (p.current_sector < (DD->SECTORS_IN_BLOCK - 4)) {
- p.state = STATE_SECTOR_WRITE;
- }
- }
- }
- if (scr & DD_SCR_BM_ACK) {
- DD->SCR |= DD_SCR_BM_ACK_CLEAR;
- if (p.transfer_mode) {
- if ((p.current_sector <= (DD->SECTORS_IN_BLOCK - 4))) {
- } else if (p.current_sector < (DD->SECTORS_IN_BLOCK - 1)) {
- p.current_sector += 1;
- DD->SCR |= DD_SCR_BM_READY;
- } else if (p.current_sector < DD->SECTORS_IN_BLOCK) {
- p.current_sector += 1;
- DD->SCR |= DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_READY;
- }
- } else {
- if (p.current_sector == (DD->SECTORS_IN_BLOCK - 4)) {
- p.state = STATE_STOP;
- }
- }
- }
- }
- }
-
- switch (p.state) {
- case STATE_IDLE:
- break;
-
- case STATE_START:
- p.bm_running = true;
- p.current_sector = 0;
- if (p.transfer_mode) {
- if (dd_block_valid()) {
- p.state = STATE_BLOCK_READ;
- DD->SCR |= DD_SCR_BM_TRANSFER_DATA;
- } else {
- p.state = STATE_SECTOR_READ;
- DD->SCR |= DD_SCR_BM_MICRO_ERROR;
- }
- } else {
- p.state = STATE_IDLE;
- if (dd_block_valid()) {
- DD->SCR |= DD_SCR_BM_TRANSFER_DATA | DD_SCR_BM_READY;
- } else {
- DD->SCR |= DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_READY;
- }
- }
- break;
-
- case STATE_BLOCK_READ:
- if (dd_block_request()) {
- p.state = STATE_BLOCK_READ_WAIT;
- }
- break;
-
- case STATE_BLOCK_READ_WAIT:
- if (dd_block_ready()) {
- p.state = STATE_SECTOR_READ;
- }
- break;
-
- case STATE_SECTOR_READ:
- dd_sector_read();
- p.state = STATE_IDLE;
- p.current_sector += 1;
- DD->SCR |= DD_SCR_BM_READY;
- break;
-
- case STATE_SECTOR_WRITE:
- dd_sector_write();
- p.current_sector += 1;
- if (p.current_sector < (DD->SECTORS_IN_BLOCK - 4)) {
- p.state = STATE_IDLE;
- DD->SCR |= DD_SCR_BM_READY;
- } else {
- p.state = STATE_BLOCK_WRITE;
- }
- break;
-
- case STATE_BLOCK_WRITE:
- if (dd_block_request()) {
- p.state = STATE_BLOCK_WRITE_WAIT;
- }
- break;
-
- case STATE_BLOCK_WRITE_WAIT:
- if (dd_block_ready()) {
- p.state = STATE_NEXT_BLOCK;
- }
- break;
-
- case STATE_NEXT_BLOCK:
- if (p.full_track_transfer) {
- p.state = STATE_START;
- p.full_track_transfer = false;
- p.starting_block = !p.starting_block;
- DD->SCR &= ~(DD_SCR_BM_TRANSFER_C2);
- } else {
- if (p.transfer_mode) {
- p.state = STATE_STOP;
- } else {
- p.state = STATE_IDLE;
- DD->SCR &= ~(DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA);
- DD->SCR |= DD_SCR_BM_READY;
- }
- }
- break;
-
- case STATE_STOP:
- p.state = STATE_IDLE;
- p.bm_running = false;
- break;
- }
-}
diff --git a/sw/riscv/src/dd.h b/sw/riscv/src/dd.h
deleted file mode 100644
index cb45fc8..0000000
--- a/sw/riscv/src/dd.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef DD_H__
-#define DD_H__
-
-
-#include "sys.h"
-
-
-typedef enum {
- DD_DISK_EJECTED,
- DD_DISK_INSERTED,
- DD_DISK_CHANGED,
-} disk_state_t;
-
-
-void dd_set_disk_state (disk_state_t disk_state);
-disk_state_t dd_get_disk_state (void);
-void dd_set_drive_id (uint16_t id);
-uint16_t dd_get_drive_id (void);
-uint32_t dd_get_thb_table_offset (void);
-void dd_init (void);
-void process_dd (void);
-
-
-#endif
diff --git a/sw/riscv/src/flash.c b/sw/riscv/src/flash.c
deleted file mode 100644
index 69a7b86..0000000
--- a/sw/riscv/src/flash.c
+++ /dev/null
@@ -1,41 +0,0 @@
-#include "flash.h"
-
-
-static io32_t dummy;
-
-
-uint32_t flash_size (void) {
- return FLASH_SIZE;
-}
-
-void flash_read (uint32_t sdram_offset) {
- io32_t *flash = (io32_t *) (FLASH_BASE);
- io32_t *sdram = (io32_t *) (SDRAM_BASE + sdram_offset);
-
- for (size_t i = 0; i < FLASH_SIZE; i += sizeof(io32_t)) {
- *sdram++ = *flash++;
- }
-}
-
-void flash_program (uint32_t sdram_offset) {
- io32_t *flash = (io32_t *) (FLASH_BASE);
- io32_t *sdram = (io32_t *) (SDRAM_BASE + sdram_offset);
-
- CFG->SCR |= CFG_SCR_FLASH_WP_DISABLE;
-
- CFG->SCR |= CFG_SCR_FLASH_ERASE_START;
-
- while (CFG->SCR & CFG_SCR_FLASH_ERASE_BUSY);
-
- for (int i = 0; i < FLASH_SIZE; i += sizeof(io32_t)) {
- *flash++ = *sdram++;
- }
-
- CFG->SCR |= CFG_SCR_FLASH_WP_ENABLE;
-
- flash = (io32_t *) (FLASH_BASE);
-
- dummy = *flash;
-
- return;
-}
diff --git a/sw/riscv/src/flash.h b/sw/riscv/src/flash.h
deleted file mode 100644
index e368fdb..0000000
--- a/sw/riscv/src/flash.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef FLASH_H__
-#define FLASH_H__
-
-
-#include "sys.h"
-
-
-uint32_t flash_size (void);
-void flash_read (uint32_t sdram_offset);
-void flash_program (uint32_t sdram_offset);
-
-
-#endif
diff --git a/sw/riscv/src/flashram.c b/sw/riscv/src/flashram.c
deleted file mode 100644
index 7aeeb12..0000000
--- a/sw/riscv/src/flashram.c
+++ /dev/null
@@ -1,92 +0,0 @@
-#include "sys.h"
-
-
-#define FLASHRAM_SIZE (128 * 1024)
-#define FLASHRAM_SECTOR_SIZE (16 * 1024)
-#define FLASHRAM_PAGE_SIZE (128)
-#define FLASHRAM_ERASE_VALUE (0xFFFFFFFF)
-
-enum operation {
- OP_NONE,
- OP_ERASE_ALL,
- OP_ERASE_SECTOR,
- OP_WRITE_PAGE
-};
-
-
-struct process {
- bool save_in_progress;
- enum operation op;
- io32_t *save_pointer;
- uint32_t num_words;
- uint32_t current_word;
-};
-
-static struct process p;
-
-
-static enum operation get_operation_type (void) {
- uint32_t scr = FLASHRAM->SCR;
-
- if (!(scr & FLASHRAM_OPERATION_PENDING)) {
- return OP_NONE;
- }
-
- if (scr & FLASHRAM_WRITE_OR_ERASE) {
- if (scr & FLASHRAM_SECTOR_OR_ALL) {
- return OP_ERASE_ALL;
- } else {
- return OP_ERASE_SECTOR;
- }
- } else {
- return OP_WRITE_PAGE;
- }
-}
-
-static size_t get_operation_length (enum operation op) {
- switch (op) {
- case OP_ERASE_ALL: return FLASHRAM_SIZE;
- case OP_ERASE_SECTOR: return FLASHRAM_SECTOR_SIZE;
- case OP_WRITE_PAGE: return FLASHRAM_PAGE_SIZE;
- default: return 0;
- }
-}
-
-
-void flashram_init (void) {
- FLASHRAM->SCR = FLASHRAM_OPERATION_DONE;
-
- p.save_in_progress = false;
-}
-
-
-void process_flashram (void) {
- if (!p.save_in_progress) {
- p.op = get_operation_type();
-
- if (p.op != OP_NONE) {
- uint32_t sdram_address = SDRAM_BASE + SAVE_OFFSET;
-
- p.save_in_progress = true;
- if (p.op != OP_ERASE_ALL) {
- sdram_address += (FLASHRAM->SCR >> FLASHRAM_PAGE_BIT) * FLASHRAM_PAGE_SIZE;
- }
- p.save_pointer = (io32_t *) (sdram_address);
- p.num_words = get_operation_length(p.op) / sizeof(uint32_t);
- p.current_word = 0;
- }
- } else {
- if (p.op == OP_WRITE_PAGE) {
- *p.save_pointer++ &= FLASHRAM->BUFFER[p.current_word];
- } else {
- *p.save_pointer++ = FLASHRAM_ERASE_VALUE;
- }
-
- p.current_word += 1;
-
- if (p.current_word >= p.num_words) {
- p.save_in_progress = false;
- FLASHRAM->SCR = FLASHRAM_OPERATION_DONE;
- }
- }
-}
diff --git a/sw/riscv/src/i2c.c b/sw/riscv/src/i2c.c
deleted file mode 100644
index fd34472..0000000
--- a/sw/riscv/src/i2c.c
+++ /dev/null
@@ -1,113 +0,0 @@
-#include "i2c.h"
-
-
-enum phase {
- PHASE_START,
- PHASE_ADDRESS,
- PHASE_DATA,
- PHASE_STOP,
-};
-
-struct process {
- enum phase phase;
- uint8_t address;
- uint8_t *data;
- uint8_t length;
- bool write;
- bool generate_stop;
- bool first_byte_transferred;
- bool busy;
- bool done;
- bool failed;
-};
-
-static struct process p;
-
-
-bool i2c_busy (void) {
- return p.busy;
-}
-
-bool i2c_done (void) {
- return p.done;
-}
-
-bool i2c_failed (void) {
- return p.failed;
-}
-
-void i2c_trx (uint8_t address, uint8_t *data, uint8_t length, bool write, bool generate_stop) {
- p.phase = PHASE_START;
- p.address = address;
- p.data = data;
- p.length = length;
- p.write = write;
- p.generate_stop = generate_stop;
- p.first_byte_transferred = false;
- p.busy = true;
- p.done = false;
- p.failed = false;
-}
-
-
-void i2c_init (void) {
- I2C->SCR = I2C_SCR_STOP;
- p.busy = false;
- p.done = false;
- p.failed = false;
-}
-
-
-void process_i2c (void) {
- if (p.busy && (!(I2C->SCR & I2C_SCR_BUSY))) {
- switch (p.phase) {
- case PHASE_START:
- I2C->SCR = I2C_SCR_START;
- p.phase = PHASE_ADDRESS;
- break;
-
- case PHASE_ADDRESS:
- I2C->SCR = 0;
- I2C->DR = p.address | (p.write ? 0 : (1 << 0));
- p.phase = PHASE_DATA;
- break;
-
- case PHASE_DATA:
- if (p.write) {
- p.failed |= (!(I2C->SCR & I2C_SCR_ACK));
- I2C->DR = *p.data++;
- if (p.length == 1) {
- if (p.generate_stop) {
- p.phase = PHASE_STOP;
- } else {
- p.busy = false;
- p.done = true;
- }
- }
- } else {
- if (p.first_byte_transferred) {
- *(p.data++) = I2C->DR;
- }
- if (p.length >= 1) {
- I2C->SCR = (p.length > 1) ? I2C_SCR_MACK : 0;
- I2C->DR = 0xFF;
- p.first_byte_transferred = true;
- }
- if (p.length == 0) {
- p.phase = PHASE_STOP;
- }
- }
- p.length -= 1;
- break;
-
- case PHASE_STOP:
- if (p.write) {
- p.failed |= (!(I2C->SCR & I2C_SCR_ACK));
- }
- I2C->SCR = I2C_SCR_STOP;
- p.busy = false;
- p.done = true;
- break;
- }
- }
-}
diff --git a/sw/riscv/src/i2c.h b/sw/riscv/src/i2c.h
deleted file mode 100644
index 8869685..0000000
--- a/sw/riscv/src/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef I2C_H__
-#define I2C_H__
-
-
-#include "sys.h"
-
-
-bool i2c_busy (void);
-bool i2c_done (void);
-bool i2c_failed (void);
-void i2c_trx (uint8_t address, uint8_t *data, uint8_t length, bool write, bool generate_stop);
-void i2c_init (void);
-void process_i2c (void);
-
-
-#endif
diff --git a/sw/riscv/src/isv.c b/sw/riscv/src/isv.c
deleted file mode 100644
index 296ade3..0000000
--- a/sw/riscv/src/isv.c
+++ /dev/null
@@ -1,74 +0,0 @@
-#include "isv.h"
-#include "usb.h"
-
-
-typedef struct {
- io32_t __padding_1[5];
- io32_t RD_PTR;
- io32_t __padding_2[2];
- io8_t BUFFER[(64 * 1024) - 0x20];
-} isv_t;
-
-#define ISV_BASE (SDRAM_BASE + 0x03FF0000UL)
-#define ISV ((isv_t *) ISV_BASE)
-
-
-struct process {
- bool enabled;
- bool ready;
- uint16_t current_read_pointer;
-};
-
-static struct process p;
-
-
-static void isv_set_ready (void) {
- p.ready = true;
-}
-
-void isv_set_enabled (bool enabled) {
- if (enabled) {
- CFG->SCR |= CFG_SCR_WRITES_ON_RESET_EN;
- ISV->RD_PTR = SWAP32(0);
- p.enabled = true;
- p.ready = true;
- p.current_read_pointer = 0;
- } else {
- CFG->SCR &= ~(CFG_SCR_WRITES_ON_RESET_EN);
- p.enabled = false;
- }
-}
-
-bool isv_get_enabled (void) {
- return p.enabled;
-}
-
-
-void isv_init (void) {
- p.enabled = false;
-}
-
-
-void process_isv (void) {
- if (p.enabled && p.ready) {
- uint16_t read_pointer = (uint16_t) (SWAP32(ISV->RD_PTR));
-
- if (read_pointer != p.current_read_pointer) {
- bool wrap = read_pointer < p.current_read_pointer;
-
- uint32_t length = ((wrap ? sizeof(ISV->BUFFER) : read_pointer) - p.current_read_pointer);
- uint32_t offset = (((uint32_t) (&ISV->BUFFER[p.current_read_pointer])) & 0x0FFFFFFF);
-
- usb_event_t event;
- event.id = EVENT_ID_IS_VIEWER;
- event.trigger = CALLBACK_SDRAM_READ;
- event.callback = isv_set_ready;
- uint32_t data[2] = { length, offset };
-
- if (usb_put_event(&event, data, sizeof(data))) {
- p.current_read_pointer = wrap ? 0 : read_pointer;
- p.ready = false;
- }
- }
- }
-}
diff --git a/sw/riscv/src/isv.h b/sw/riscv/src/isv.h
deleted file mode 100644
index 4b4a521..0000000
--- a/sw/riscv/src/isv.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef ISV_H__
-#define ISV_H__
-
-
-#include "sys.h"
-
-
-void isv_set_enabled (bool enabled);
-bool isv_get_enabled (void);
-void isv_init (void);
-void process_isv (void);
-
-
-#endif
diff --git a/sw/riscv/src/joybus.c b/sw/riscv/src/joybus.c
deleted file mode 100644
index f70f931..0000000
--- a/sw/riscv/src/joybus.c
+++ /dev/null
@@ -1,161 +0,0 @@
-#include "joybus.h"
-#include "rtc.h"
-#include "sys.h"
-
-
-#define CMD_EEPROM_STATUS (0x00)
-#define CMD_EEPROM_READ (0x04)
-#define CMD_EEPROM_WRITE (0x05)
-#define CMD_RTC_STATUS (0x06)
-#define CMD_RTC_READ (0x07)
-#define CMD_RTC_WRITE (0x08)
-
-#define EEPROM_ID_4K (0x80)
-#define EEPROM_ID_16K (0xC0)
-#define RTC_ID (0x10)
-
-#define EEPROM_PAGE_SIZE (8)
-
-#define RTC_STATUS_STOPPED (0x80)
-#define RTC_STATUS_RUNNING (0x00)
-#define RTC_STATUS(running) (running ? RTC_STATUS_RUNNING : RTC_STATUS_STOPPED)
-
-#define RTC_BLOCK_CFG (0)
-#define RTC_BLOCK_BACKUP (1)
-#define RTC_BLOCK_TIME (2)
-
-#define RTC_WP_BACKUP (1 << 0)
-#define RTC_WP_TIME (1 << 1)
-#define RTC_WP_MASK (RTC_WP_TIME | RTC_WP_BACKUP)
-#define RTC_ST (1 << 2)
-#define RTC_CENTURY_20XX (0x01)
-
-
-static void joybus_rx (uint8_t *data) {
- size_t rx_length = (JOYBUS->SCR & JOYBUS_SCR_RX_LENGTH_MASK) >> JOYBUS_SCR_RX_LENGTH_BIT;
- for (size_t i = 0; i < rx_length; i++) {
- data[i] = ((uint8_t *) (JOYBUS->DATA))[(10 - rx_length) + i];
- }
-}
-
-static void joybus_tx (uint8_t *data, size_t length) {
- for (size_t i = 0; i < ((length + 3) / 4); i++) {
- JOYBUS->DATA[i] = ((uint32_t *) (data))[i];
- }
- JOYBUS->SCR = ((length * 8) << JOYBUS_SCR_TX_LENGTH_BIT) | JOYBUS_SCR_TX_START;
-}
-
-
-struct process {
- enum eeprom_type eeprom_type;
- bool rtc_running;
- uint8_t rtc_write_protect;
-};
-
-static struct process p;
-
-
-void joybus_set_eeprom (enum eeprom_type eeprom_type) {
- p.eeprom_type = eeprom_type;
-}
-
-
-void joybus_init (void) {
- JOYBUS->SCR = JOYBUS_SCR_TX_RESET | JOYBUS_SCR_RX_RESET;
-
- p.eeprom_type = EEPROM_NONE;
- p.rtc_running = true;
- p.rtc_write_protect = RTC_WP_MASK;
-}
-
-
-void process_joybus (void) {
- uint8_t rx_data[10];
- uint8_t tx_data[12];
- io32_t *save_data;
- uint32_t *data_offset;
-
- if (JOYBUS->SCR & JOYBUS_SCR_RX_READY) {
- if (JOYBUS->SCR & JOYBUS_SCR_RX_STOP_BIT) {
- joybus_rx(rx_data);
-
- for (size_t i = 0; i < sizeof(tx_data); i++) {
- tx_data[i] = 0x00;
- }
-
- if (p.eeprom_type != EEPROM_NONE) {
- save_data = (io32_t *) (SDRAM_BASE + SAVE_OFFSET + (rx_data[1] * EEPROM_PAGE_SIZE));
- switch (rx_data[0]) {
- case CMD_EEPROM_STATUS:
- tx_data[1] = p.eeprom_type == EEPROM_16K ? EEPROM_ID_16K : EEPROM_ID_4K;
- joybus_tx(tx_data, 3);
- break;
-
- case CMD_EEPROM_READ:
- data_offset = (uint32_t *) (&tx_data[0]);
- data_offset[0] = save_data[0];
- data_offset[1] = save_data[1];
- joybus_tx(tx_data, 8);
- break;
-
- case CMD_EEPROM_WRITE:
- data_offset = (uint32_t *) (&rx_data[2]);
- save_data[0] = data_offset[0];
- save_data[1] = data_offset[1];
- joybus_tx(tx_data, 1);
- break;
- }
- }
-
- switch (rx_data[0]) {
- case CMD_RTC_STATUS:
- tx_data[1] = RTC_ID;
- tx_data[2] = RTC_STATUS(p.rtc_running);
- joybus_tx(tx_data, 3);
- break;
-
- case CMD_RTC_READ:
- if (rx_data[1] == RTC_BLOCK_CFG) {
- tx_data[0] = p.rtc_write_protect;
- if (!p.rtc_running) {
- tx_data[1] = RTC_ST;
- }
- } else if (rx_data[1] == RTC_BLOCK_TIME) {
- rtc_time_t *rtc_time = rtc_get_time();
- tx_data[0] = rtc_time->second;
- tx_data[1] = rtc_time->minute;
- tx_data[2] = rtc_time->hour | 0x80;
- tx_data[4] = rtc_time->weekday - 1;
- tx_data[3] = rtc_time->day;
- tx_data[5] = rtc_time->month;
- tx_data[6] = rtc_time->year;
- tx_data[7] = RTC_CENTURY_20XX;
- }
- tx_data[8] = RTC_STATUS(p.rtc_running);
- joybus_tx(tx_data, 9);
- break;
-
- case CMD_RTC_WRITE:
- if (rx_data[1] == RTC_BLOCK_CFG) {
- p.rtc_write_protect = rx_data[2] & RTC_WP_MASK;
- p.rtc_running = (!(rx_data[3] & RTC_ST));
- } else if (rx_data[1] == RTC_BLOCK_TIME && (!(p.rtc_write_protect & RTC_WP_TIME))) {
- rtc_time_t rtc_time;
- rtc_time.second = rx_data[2];
- rtc_time.minute = rx_data[3];
- rtc_time.hour = rx_data[4] & 0x7F;
- rtc_time.weekday = rx_data[6] + 1;
- rtc_time.day = rx_data[5];
- rtc_time.month = rx_data[7];
- rtc_time.year = rx_data[8];
- rtc_set_time(&rtc_time);
- }
- tx_data[0] = RTC_STATUS(p.rtc_running);
- joybus_tx(tx_data, 1);
- break;
- }
- }
-
- JOYBUS->SCR = JOYBUS_SCR_RX_RESET;
- }
-}
diff --git a/sw/riscv/src/joybus.h b/sw/riscv/src/joybus.h
deleted file mode 100644
index 8a9f703..0000000
--- a/sw/riscv/src/joybus.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef JOYBUS_H__
-#define JOYBUS_H__
-
-
-enum eeprom_type {
- EEPROM_NONE,
- EEPROM_4K,
- EEPROM_16K,
-};
-
-
-void joybus_init (void);
-void joybus_set_eeprom (enum eeprom_type eeprom_type);
-void process_joybus (void);
-
-
-#endif
diff --git a/sw/riscv/src/process.c b/sw/riscv/src/process.c
deleted file mode 100644
index c5dfe10..0000000
--- a/sw/riscv/src/process.c
+++ /dev/null
@@ -1,46 +0,0 @@
-#include "process.h"
-#include "usb.h"
-#include "cfg.h"
-#include "joybus.h"
-#include "rtc.h"
-#include "i2c.h"
-#include "flashram.h"
-#include "dd.h"
-#include "uart.h"
-#include "isv.h"
-
-
-static const void (*process_table[])(void) = {
- process_usb,
- process_cfg,
- process_rtc,
- process_i2c,
- process_flashram,
- process_dd,
- process_uart,
- process_isv,
- NULL,
-};
-
-
-__attribute__((naked)) void process_loop (void) {
- void (**process_func)(void) = process_table;
-
- usb_init();
- cfg_init();
- joybus_init();
- rtc_init();
- i2c_init();
- flashram_init();
- dd_init();
- uart_init();
- isv_init();
-
- while (1) {
- process_joybus();
- (*process_func++)();
- if (*process_func == NULL) {
- process_func = process_table;
- }
- }
-}
diff --git a/sw/riscv/src/process.h b/sw/riscv/src/process.h
deleted file mode 100644
index e0df2a1..0000000
--- a/sw/riscv/src/process.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef PROCESS_H__
-#define PROCESS_H__
-
-
-void process_init (void);
-void process_loop (void);
-
-
-#endif
diff --git a/sw/riscv/src/rtc.c b/sw/riscv/src/rtc.c
deleted file mode 100644
index 4c203c2..0000000
--- a/sw/riscv/src/rtc.c
+++ /dev/null
@@ -1,231 +0,0 @@
-#include "rtc.h"
-#include "i2c.h"
-
-
-enum rtc_regs {
- RTCSEC,
- RTCMIN,
- RTCHOUR,
- RTCWKDAY,
- RTCDATE,
- RTCMTH,
- RTCYEAR,
-};
-
-#define RTC_I2C_ADDR (0xDE)
-
-#define RTCSEC_ST (1 << 7)
-#define RTCWKDAY_OSCRUN (1 << 5)
-#define RTCWKDAY_VBAT (1 << 3)
-
-
-enum rtc_phase {
- RTC_PHASE_READ_START,
- RTC_PHASE_READ_READY,
- RTC_PHASE_STOP,
- RTC_PHASE_WAIT_STOP,
- RTC_PHASE_UPDATE,
- RTC_PHASE_START,
- RTC_PHASE_WAIT_START,
-};
-
-enum i2c_phase {
- I2C_PHASE_IDLE,
- I2C_PHASE_ADDR,
- I2C_PHASE_DATA,
- I2C_PHASE_READY,
-};
-
-
-struct process {
- enum rtc_phase rtc_phase;
- uint8_t data[7];
- bool running;
- rtc_time_t time;
- bool time_valid;
- bool new_time_valid;
-
- enum i2c_phase i2c_phase;
- bool i2c_pending;
- bool i2c_write;
- uint8_t i2c_address;
- uint8_t i2c_length;
- bool i2c_first_read_done;
-};
-
-static struct process p;
-
-
-static const uint8_t rtc_regs_bit_mask[7] = {
- 0b01111111,
- 0b01111111,
- 0b00111111,
- 0b00000111,
- 0b00111111,
- 0b00011111,
- 0b11111111
-};
-
-static void sanitize_time (uint8_t *data) {
- for (int i = 0; i < 7; i++) {
- data[i] &= rtc_regs_bit_mask[i];
- }
-}
-
-
-rtc_time_t *rtc_get_time (void) {
- return &p.time;
-}
-
-bool rtc_is_time_valid (void) {
- return p.time_valid;
-}
-
-bool rtc_is_time_running (void) {
- return p.running;
-}
-
-void rtc_set_time (rtc_time_t *time) {
- p.time.second = time->second;
- p.time.minute = time->minute;
- p.time.hour = time->hour;
- p.time.weekday = time->weekday;
- p.time.day = time->day;
- p.time.month = time->month;
- p.time.year = time->year;
- p.new_time_valid = true;
-}
-
-
-void rtc_init (void) {
- p.rtc_phase = RTC_PHASE_READ_START;
- p.running = false;
- p.time_valid = false;
- p.new_time_valid = false;
-
- p.i2c_phase = I2C_PHASE_IDLE;
- p.i2c_pending = false;
-}
-
-
-void process_rtc (void) {
- if (p.i2c_phase == I2C_PHASE_IDLE) {
- switch (p.rtc_phase) {
- case RTC_PHASE_READ_START:
- p.i2c_pending = true;
- p.i2c_write = false;
- p.i2c_address = RTCSEC;
- p.i2c_length = sizeof(p.data);
- p.rtc_phase = RTC_PHASE_READ_READY;
- break;
-
- case RTC_PHASE_READ_READY:
- p.time_valid = (!i2c_failed());
- if (p.new_time_valid) {
- p.rtc_phase = RTC_PHASE_STOP;
- break;
- } else if (p.time_valid) {
- p.running = p.data[RTCSEC] & RTCSEC_ST;
- sanitize_time(p.data);
- p.time.second = p.data[RTCSEC];
- p.time.minute = p.data[RTCMIN];
- p.time.hour = p.data[RTCHOUR];
- p.time.weekday = p.data[RTCWKDAY];
- p.time.day = p.data[RTCDATE];
- p.time.month = p.data[RTCMTH];
- p.time.year = p.data[RTCYEAR];
- }
- p.rtc_phase = RTC_PHASE_READ_START;
- break;
-
- case RTC_PHASE_STOP:
- p.i2c_pending = true;
- p.i2c_write = true;
- p.i2c_length = 2;
- p.i2c_first_read_done = false;
- p.data[0] = RTCSEC;
- p.data[1] = 0x00;
- p.rtc_phase = RTC_PHASE_WAIT_STOP;
- break;
-
- case RTC_PHASE_WAIT_STOP:
- if (p.i2c_first_read_done) {
- if (!(p.data[0] & RTCWKDAY_OSCRUN)) {
- p.rtc_phase = RTC_PHASE_UPDATE;
- break;
- }
- }
- p.i2c_pending = true;
- p.i2c_write = false;
- p.i2c_address = RTCWKDAY;
- p.i2c_length = 1;
- p.i2c_first_read_done = true;
- break;
-
- case RTC_PHASE_UPDATE:
- sanitize_time((uint8_t *)(&p.time));
- p.i2c_pending = true;
- p.i2c_write = true;
- p.i2c_length = 7;
- p.data[0] = RTCMIN;
- p.data[1] = p.time.minute;
- p.data[2] = p.time.hour;
- p.data[3] = p.time.weekday | RTCWKDAY_VBAT;
- p.data[4] = p.time.day;
- p.data[5] = p.time.month;
- p.data[6] = p.time.year;
- p.rtc_phase = RTC_PHASE_START;
- break;
-
- case RTC_PHASE_START:
- p.i2c_pending = true;
- p.i2c_write = true;
- p.i2c_length = 2;
- p.i2c_first_read_done = false;
- p.data[0] = RTCSEC;
- p.data[1] = p.time.second | RTCSEC_ST;
- p.rtc_phase = RTC_PHASE_WAIT_START;
- break;
-
- case RTC_PHASE_WAIT_START:
- if (p.i2c_first_read_done) {
- if (p.data[0] & RTCWKDAY_OSCRUN) {
- p.new_time_valid = false;
- p.rtc_phase = RTC_PHASE_READ_START;
- break;
- }
- }
- p.i2c_pending = true;
- p.i2c_write = false;
- p.i2c_address = RTCWKDAY;
- p.i2c_length = 1;
- p.i2c_first_read_done = true;
- break;
- }
- }
-
- if (!i2c_busy()) {
- switch (p.i2c_phase) {
- case I2C_PHASE_IDLE:
- if (p.i2c_pending) {
- p.i2c_pending = false;
- p.i2c_phase = p.i2c_write ? I2C_PHASE_DATA : I2C_PHASE_ADDR;
- }
- break;
-
- case I2C_PHASE_ADDR:
- i2c_trx(RTC_I2C_ADDR, &p.i2c_address, 1, true, false);
- p.i2c_phase = I2C_PHASE_DATA;
- break;
-
- case I2C_PHASE_DATA:
- i2c_trx(RTC_I2C_ADDR, p.data, p.i2c_length, p.i2c_write, true);
- p.i2c_phase = I2C_PHASE_READY;
- break;
-
- case I2C_PHASE_READY:
- p.i2c_phase = I2C_PHASE_IDLE;
- break;
- }
- }
-}
diff --git a/sw/riscv/src/startup.S b/sw/riscv/src/startup.S
deleted file mode 100644
index c7ccf90..0000000
--- a/sw/riscv/src/startup.S
+++ /dev/null
@@ -1,47 +0,0 @@
-.section .text.reset_handler
-reset_handler:
- .global reset_handler
-
- .option push
- .option norelax
- la gp, __global_pointer$
- .option pop
-
- la sp, __stack_pointer$
-
-init_text:
- la a0, _sitext
- la a1, _stext
- la a2, _etext
- call copy_section
-
-init_data:
- la a0, _sidata
- la a1, _sdata
- la a2, _edata
- call copy_section
-
-init_bss:
- la a0, _sbss
- la a1, _ebss
- bge a0, a1, 2f
-1:
- sw zero, 0(a0)
- addi a0, a0, 4
- blt a0, a1, 1b
-2:
-
-run_in_ram:
- la ra, process_loop
- jalr zero, 0(ra)
-
-copy_section:
- bge a1, a2, 2f
-1:
- lw a3, 0(a0)
- sw a3, 0(a1)
- addi a0, a0, 4
- addi a1, a1, 4
- blt a1, a2, 1b
-2:
- ret
diff --git a/sw/riscv/src/sys.h b/sw/riscv/src/sys.h
deleted file mode 100644
index 5563cb0..0000000
--- a/sw/riscv/src/sys.h
+++ /dev/null
@@ -1,212 +0,0 @@
-#ifndef SYS_H__
-#define SYS_H__
-
-
-#include
-#include
-#include
-#include
-
-
-#define SWAP32(x) ((((x) & 0xFF000000UL) >> 24) | \
- (((x) & 0x00FF0000UL) >> 8) | \
- (((x) & 0x0000FF00UL) << 8) | \
- (((x) & 0x000000FFUL) << 24))
-
-#define ALIGN(value, align) (((value) + ((typeof(value))(align) - 1)) & ~((typeof(value))(align) - 1))
-
-
-typedef volatile uint8_t io8_t;
-typedef volatile uint16_t io16_t;
-typedef volatile uint32_t io32_t;
-
-
-#define DDIPL_OFFSET (0x07800000UL)
-#define SAVE_OFFSET (0x07EE0000UL)
-
-
-#define FLASH_BASE (0x00000000UL)
-#define FLASH_SIZE (0x39800)
-#define FLASH (*((io32_t *) FLASH_BASE))
-
-
-#define RAM_BASE (0x10000000UL)
-#define RAM_SIZE (16 * 1024)
-#define RAM (*((io32_t *) RAM_BASE))
-
-
-typedef volatile struct cfg_regs {
- io32_t SCR;
- io8_t CMD;
- io8_t __padding[3];
- io32_t DATA[2];
- io32_t VERSION;
- io32_t RECONFIGURE;
-} cfg_regs_t;
-
-#define CFG_BASE (0x20000000UL)
-#define CFG ((cfg_regs_t *) CFG_BASE)
-
-#define CFG_SCR_SDRAM_SWITCH (1 << 0)
-#define CFG_SCR_SDRAM_WRITABLE (1 << 1)
-#define CFG_SCR_DD_EN (1 << 2)
-#define CFG_SCR_SRAM_EN (1 << 3)
-#define CFG_SCR_SRAM_BANKED (1 << 4)
-#define CFG_SCR_FLASHRAM_EN (1 << 5)
-#define CFG_SCR_SKIP_BOOTLOADER (1 << 6)
-#define CFG_SCR_WRITES_ON_RESET_EN (1 << 7)
-#define CFG_SCR_FLASH_ERASE_START (1 << 24)
-#define CFG_SCR_FLASH_ERASE_BUSY (1 << 25)
-#define CFG_SCR_FLASH_WP_ENABLE (1 << 26)
-#define CFG_SCR_FLASH_WP_DISABLE (1 << 27)
-#define CFG_SCR_CMD_ERROR (1 << 28)
-#define CFG_SCR_CPU_BUSY (1 << 30)
-#define CFG_SCR_CPU_READY (1 << 31)
-
-
-typedef volatile struct i2c_regs {
- io32_t SCR;
- io32_t DR;
-} i2c_regs_t;
-
-#define I2C_BASE (0x30000000UL)
-#define I2C ((i2c_regs_t *) I2C_BASE)
-
-#define I2C_SCR_START (1 << 0)
-#define I2C_SCR_STOP (1 << 1)
-#define I2C_SCR_MACK (1 << 2)
-#define I2C_SCR_ACK (1 << 3)
-#define I2C_SCR_BUSY (1 << 4)
-
-
-typedef volatile struct usb_regs {
- io32_t SCR;
- io8_t DR;
- io8_t __padding_1[3];
- io32_t ADDR;
- io32_t LEN;
-} usb_regs_t;
-
-#define USB_BASE (0x40000000UL)
-#define USB ((usb_regs_t *) USB_BASE)
-
-#define USB_SCR_RXNE (1 << 0)
-#define USB_SCR_TXE (1 << 1)
-#define USB_SCR_FLUSH_RX (1 << 2)
-#define USB_SCR_FLUSH_TX (1 << 3)
-#define USB_SCR_ENABLE (1 << 4)
-#define USB_SCR_FORCE_TX (1 << 5)
-#define USB_SCR_RESET_PENDING (1 << 6)
-#define USB_SCR_RESET_ACK (1 << 7)
-#define USB_SCR_DMA_BUSY (1 << 8)
-#define USB_SCR_DMA_START (1 << 9)
-#define USB_SCR_DMA_STOP (1 << 10)
-#define USB_SCR_DMA_DIR (1 << 11)
-
-
-typedef volatile struct uart_regs {
- io32_t SCR;
- io8_t DR;
- io8_t __padding[3];
-} uart_regs_t;
-
-#define UART_BASE (0x50000000UL)
-#define UART ((uart_regs_t *) UART_BASE)
-
-#define UART_SCR_RXNE (1 << 0)
-#define UART_SCR_TXE (1 << 1)
-
-
-typedef volatile struct dd_regs {
- io32_t SCR;
- io16_t DATA;
- io8_t CMD;
- io8_t __padding_1;
- io16_t HEAD_TRACK;
- io16_t __padding_2;
- io8_t SECTOR_NUM;
- io8_t SECTOR_SIZE;
- io8_t SECTOR_SIZE_FULL;
- io8_t SECTORS_IN_BLOCK;
- io16_t DRIVE_ID;
- io16_t __padding_3;
- io32_t SEEK_TIMER;
- io32_t __padding_4[58];
- io32_t SECTOR_BUFFER[64];
-} dd_regs_t;
-
-#define DD_BASE (0x60000000UL)
-#define DD ((dd_regs_t *) DD_BASE)
-
-#define DD_SCR_HARD_RESET (1 << 0)
-#define DD_SCR_HARD_RESET_CLEAR (1 << 1)
-#define DD_SCR_CMD_PENDING (1 << 2)
-#define DD_SCR_CMD_READY (1 << 3)
-#define DD_SCR_BM_PENDING (1 << 4)
-#define DD_SCR_BM_READY (1 << 5)
-#define DD_SCR_DISK_INSERTED (1 << 6)
-#define DD_SCR_DISK_CHANGED (1 << 7)
-#define DD_SCR_BM_START (1 << 8)
-#define DD_SCR_BM_START_CLEAR (1 << 9)
-#define DD_SCR_BM_STOP (1 << 10)
-#define DD_SCR_BM_STOP_CLEAR (1 << 11)
-#define DD_SCR_BM_TRANSFER_MODE (1 << 12)
-#define DD_SCR_BM_TRANSFER_BLOCKS (1 << 13)
-#define DD_SCR_BM_TRANSFER_DATA (1 << 14)
-#define DD_SCR_BM_TRANSFER_C2 (1 << 15)
-#define DD_SCR_BM_MICRO_ERROR (1 << 16)
-#define DD_SCR_BM_ACK (1 << 17)
-#define DD_SCR_BM_ACK_CLEAR (1 << 18)
-#define DD_SCR_BM_CLEAR (1 << 19)
-#define DD_SCR_SEEK_TIMER_RESET (1 << 20)
-
-#define DD_TRACK_MASK (0x0FFF)
-#define DD_HEAD_MASK (0x1000)
-#define DD_HEAD_TRACK_MASK (DD_HEAD_MASK | DD_TRACK_MASK)
-#define DD_HEAD_TRACK_INDEX_LOCK (1 << 13)
-
-
-#define SDRAM_BASE (0x70000000UL)
-#define SDRAM (*((io32_t *) SDRAM_BASE))
-#define SDRAM_SIZE (64 * 1024 * 1024)
-
-
-typedef volatile struct flashram_regs {
- io32_t SCR;
- io32_t __padding[31];
- io32_t BUFFER[32];
-} flashram_regs_t;
-
-#define FLASHRAM_BASE (0x80000000UL)
-#define FLASHRAM ((flashram_regs_t *) FLASHRAM_BASE)
-
-#define FLASHRAM_OPERATION_PENDING (1 << 0)
-#define FLASHRAM_OPERATION_DONE (1 << 1)
-#define FLASHRAM_WRITE_OR_ERASE (1 << 2)
-#define FLASHRAM_SECTOR_OR_ALL (1 << 3)
-#define FLASHRAM_PAGE_BIT (8)
-
-
-typedef volatile struct joybus_regs {
- io32_t SCR;
- io32_t DATA[3];
-} joybus_regs_t;
-
-#define JOYBUS_BASE (0x90000000UL)
-#define JOYBUS ((joybus_regs_t *) JOYBUS_BASE)
-
-#define JOYBUS_SCR_RX_READY (1 << 0)
-#define JOYBUS_SCR_RX_STOP_BIT (1 << 1)
-#define JOYBUS_SCR_TX_START (1 << 2)
-#define JOYBUS_SCR_TX_BUSY (1 << 3)
-#define JOYBUS_SCR_RX_RESET (1 << 6)
-#define JOYBUS_SCR_TX_RESET (1 << 7)
-#define JOYBUS_SCR_RX_LENGTH_BIT (8)
-#define JOYBUS_SCR_RX_LENGTH_MASK (0x7F << JOYBUS_SCR_RX_LENGTH_BIT)
-#define JOYBUS_SCR_TX_LENGTH_BIT (16)
-
-
-void reset_handler(void);
-
-
-#endif
diff --git a/sw/riscv/src/uart.c b/sw/riscv/src/uart.c
deleted file mode 100644
index 6cbabd0..0000000
--- a/sw/riscv/src/uart.c
+++ /dev/null
@@ -1,81 +0,0 @@
-#include "uart.h"
-#include "rtc.h"
-
-
-#ifdef DEBUG
-static const char hex_char_map[16] = {
- '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
-};
-#endif
-
-void uart_put (char c) {
-#ifdef DEBUG
- while (!(UART->SCR & UART_SCR_TXE));
- UART->DR = c;
-#endif
-}
-
-void uart_print (const char *text) {
-#ifdef DEBUG
- while (*text != '\0') {
- uart_put(*text++);
- }
-#endif
-}
-
-void uart_print_02hex (uint8_t number) {
-#ifdef DEBUG
- char buffer[3];
- buffer[0] = hex_char_map[(number >> 4) & 0x0F];
- buffer[1] = hex_char_map[number & 0x0F];
- buffer[2] = '\0';
- uart_print(buffer);
-#endif
-}
-
-void uart_print_08hex (uint32_t number) {
-#ifdef DEBUG
- uart_print_02hex((number >> 24) & 0xFF);
- uart_print_02hex((number >> 16) & 0xFF);
- uart_print_02hex((number >> 8) & 0xFF);
- uart_print_02hex((number >> 0) & 0xFF);
-#endif
-}
-
-void uart_init (void) {
-#ifdef DEBUG
- uart_print("App ready from flash!\n");
-#endif
-}
-
-
-void process_uart (void) {
-#ifdef DEBUG
- rtc_time_t *time;
-
- if (UART->SCR & USB_SCR_RXNE) {
- switch (UART->DR) {
- case '/':
- uart_print("Bootloader reset...\n");
- reset_handler();
- break;
-
- case 't':
- time = rtc_get_time();
- uart_print("Current time: ");
- if (rtc_is_time_running()) {
- uart_print("(running) ");
- }
- if (rtc_is_time_valid()) {
- uart_print("(valid) ");
- }
- for (int i = 0; i < 7; i++) {
- uart_print_02hex(((uint8_t *) (time))[i]);
- uart_print(" ");
- }
- uart_print("\n");
- break;
- }
- }
-#endif
-}
diff --git a/sw/riscv/src/uart.h b/sw/riscv/src/uart.h
deleted file mode 100644
index 1727349..0000000
--- a/sw/riscv/src/uart.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef UART_H__
-#define UART_H__
-
-
-#include "sys.h"
-
-
-void uart_put (char c);
-void uart_print (const char *text);
-void uart_print_02hex (uint8_t number);
-void uart_print_08hex (uint32_t number);
-void uart_init (void);
-void process_uart (void);
-
-
-#endif
diff --git a/sw/riscv/src/usb.c b/sw/riscv/src/usb.c
deleted file mode 100644
index 4616304..0000000
--- a/sw/riscv/src/usb.c
+++ /dev/null
@@ -1,310 +0,0 @@
-#include "usb.h"
-#include "cfg.h"
-#include "dd.h"
-
-
-static bool rx_byte (uint8_t *data) {
- if (!(USB->SCR & USB_SCR_RXNE)) {
- return false;
- }
-
- *data = USB->DR;
-
- return true;
-}
-
-static uint8_t rx_word_current_byte = 0;
-static uint32_t rx_word_buffer = 0;
-
-static bool rx_word (uint32_t *data) {
- uint8_t tmp;
-
- while (rx_byte(&tmp)) {
- rx_word_buffer = (rx_word_buffer << 8) | tmp;
- rx_word_current_byte += 1;
- if (rx_word_current_byte == 4) {
- rx_word_current_byte = 0;
- *data = rx_word_buffer;
- rx_word_buffer = 0;
-
- return true;
- }
- }
-
- return false;
-}
-
-static bool tx_byte (uint8_t data) {
- if (!(USB->SCR & USB_SCR_TXE)) {
- return false;
- }
-
- USB->DR = data;
-
- return true;
-}
-
-static uint8_t tx_word_current_byte = 0;
-
-static bool tx_word (uint32_t data) {
- while (tx_byte(data >> ((3 - tx_word_current_byte) * 8))) {
- tx_word_current_byte += 1;
- if (tx_word_current_byte == 4) {
- tx_word_current_byte = 0;
-
- return true;
- }
- }
-
- return false;
-}
-
-
-#define USB_CMD_TOKEN (0x434D4400)
-#define USB_CMP_TOKEN (0x434D5000)
-#define USB_DMA_TOKEN (0x444D4100)
-#define USB_ERR_TOKEN (0x45525200)
-
-
-enum state {
- STATE_IDLE,
- STATE_ARGS,
- STATE_DATA,
- STATE_RESPONSE,
- STATE_EVENT,
-};
-
-struct process {
- enum state state;
- uint32_t counter;
- uint8_t cmd;
- uint32_t args[2];
- bool error;
- bool dma_in_progress;
-
- bool event_pending;
- bool event_callback_pending;
- usb_event_t event;
- uint8_t event_data[16];
- uint32_t event_data_length;
-};
-
-static struct process p;
-
-
-bool usb_put_event (usb_event_t *event, void *data, uint32_t length) {
- if (p.event_pending || p.event_callback_pending) {
- return false;
- }
-
- uint8_t *src = (uint8_t *) (data);
- uint8_t *dst = p.event_data;
-
- p.event_pending = true;
- p.event_callback_pending = false;
- p.event = *event;
- p.event_data_length = length <= sizeof(p.event_data) ? length : sizeof(p.event_data);
- for (int i = 0; i < p.event_data_length; i++) {
- *dst++ = *src++;
- }
-
- return true;
-}
-
-
-static uint8_t rx_cmd_current_byte = 0;
-static uint32_t rx_cmd_buffer = 0;
-
-static bool rx_cmd (uint32_t *data) {
- uint8_t tmp;
-
- while (rx_byte(&tmp)) {
- rx_cmd_current_byte += 1;
- if ((rx_cmd_current_byte != 4) && (tmp != (USB_CMD_TOKEN >> (8 * (4 - rx_cmd_current_byte)) & 0xFF))) {
- rx_cmd_current_byte = 0;
- rx_cmd_buffer = 0;
-
- return false;
- }
- rx_cmd_buffer = (rx_cmd_buffer << 8) | tmp;
- if (rx_cmd_current_byte == 4) {
- rx_cmd_current_byte = 0;
- *data = rx_cmd_buffer;
- rx_cmd_buffer = 0;
-
- return true;
- }
- }
-
- return false;
-}
-
-
-void usb_init (void) {
- USB->SCR = (USB_SCR_DMA_STOP | USB_SCR_ENABLE | USB_SCR_FLUSH_TX | USB_SCR_FLUSH_RX);
-
- p.state = STATE_IDLE;
- p.dma_in_progress = false;
- p.event_pending = false;
- p.event_callback_pending = false;
-
- rx_word_current_byte = 0;
- rx_word_buffer = 0;
- tx_word_current_byte = 0;
- rx_cmd_current_byte = 0;
- rx_cmd_buffer = 0;
-}
-
-
-void process_usb (void) {
- if (USB->SCR & USB_SCR_RESET_PENDING) {
- usb_init();
- USB->SCR |= USB_SCR_RESET_ACK;
- return;
- }
-
- switch (p.state) {
- case STATE_IDLE:
- if (rx_cmd(&p.args[0])) {
- if ((p.args[0] & 0xFFFFFF00) == USB_CMD_TOKEN) {
- p.cmd = p.args[0] & 0xFF;
- p.counter = 0;
- p.error = false;
- p.dma_in_progress = false;
- p.state = STATE_ARGS;
- } else {
- p.cmd = '!';
- p.error = true;
- p.state = STATE_RESPONSE;
- }
- } else if (p.event_pending && (!p.event_callback_pending)) {
- p.state = STATE_EVENT;
- p.counter = 0;
- }
- break;
-
- case STATE_ARGS:
- if (rx_word(&p.args[p.counter])) {
- p.counter += 1;
- if (p.counter == 2) {
- p.counter = 0;
- p.state = STATE_DATA;
- }
- }
- break;
-
- case STATE_DATA:
- switch (p.cmd) {
- case 'V':
- if (tx_word(cfg_get_version())) {
- p.state = STATE_RESPONSE;
- }
- break;
-
- case 'Q':
- if (p.counter == 0) {
- cfg_query(p.args);
- p.counter += 1;
- }
- if (tx_word(p.args[1])) {
- p.state = STATE_RESPONSE;
- }
- break;
-
- case 'C':
- cfg_update(p.args);
- p.state = STATE_RESPONSE;
- break;
-
- case 0xEE:
- if (p.counter == 0) {
- cfg_get_time(p.args);
- p.counter += 1;
- }
- if ((p.counter == 1) && tx_word(p.args[0])) {
- p.counter += 1;
- }
- if ((p.counter == 2) && tx_word(p.args[1])) {
- p.state = STATE_RESPONSE;
- }
- break;
-
- case 0xEF:
- cfg_set_time(p.args);
- p.state = STATE_RESPONSE;
- break;
-
- case 'R':
- case 'W':
- case 'L':
- case 'S':
- if (!(USB->SCR & USB_SCR_DMA_BUSY)) {
- if (!p.dma_in_progress) {
- USB->ADDR = p.args[0];
- USB->LEN = p.args[1];
- if ((p.cmd == 'W') || (p.cmd == 'S')) {
- USB->SCR |= (USB_SCR_DMA_DIR | USB_SCR_DMA_START);
- } else {
- USB->SCR |= USB_SCR_DMA_START;
- }
- p.dma_in_progress = true;
- } else {
- if (p.cmd == 'L' || p.cmd == 'S') {
- if (p.event_callback_pending) {
- if (p.cmd == 'L' && p.event.trigger == CALLBACK_SDRAM_READ) {
- p.event_callback_pending = false;
- p.event.callback();
- }
- if (p.cmd == 'S' && p.event.trigger == CALLBACK_SDRAM_WRITE) {
- p.event_callback_pending = false;
- p.event.callback();
- }
- }
- if (p.cmd == 'L') {
- USB->SCR |= USB_SCR_FORCE_TX;
- }
- p.state = STATE_IDLE;
- } else {
- p.state = STATE_RESPONSE;
- }
- }
- }
- break;
-
- default:
- p.error = true;
- p.state = STATE_RESPONSE;
- break;
- }
- break;
-
- case STATE_RESPONSE:
- if (tx_word((p.error ? USB_ERR_TOKEN : USB_CMP_TOKEN) | p.cmd)) {
- p.state = STATE_IDLE;
- USB->SCR |= USB_SCR_FORCE_TX;
- }
- break;
-
- case STATE_EVENT:
- if ((p.counter == 0) && tx_word(USB_DMA_TOKEN | '@')) {
- p.counter += 1;
- }
- if ((p.counter == 1) && tx_word(((p.event.id & 0xFF) << 24) | p.event_data_length)) {
- p.counter += 1;
- }
- if (p.counter >= 2) {
- while (((p.counter - 2) < p.event_data_length) && tx_byte(p.event_data[p.counter - 2])) {
- p.counter += 1;
- }
- }
- if ((p.counter == (p.event_data_length + 2)) && tx_word(USB_CMP_TOKEN | 'H')) {
- if (p.event.callback != NULL) {
- p.event_callback_pending = true;
- }
- USB->SCR |= USB_SCR_FORCE_TX;
- p.event_pending = false;
- p.state = STATE_IDLE;
- }
- break;
- }
-}
diff --git a/sw/riscv/src/usb.h b/sw/riscv/src/usb.h
deleted file mode 100644
index 5387d9e..0000000
--- a/sw/riscv/src/usb.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef USB_H__
-#define USB_H__
-
-
-#include "sys.h"
-
-
-typedef enum {
- EVENT_ID_FSD_READ = 0xF0,
- EVENT_ID_FSD_WRITE = 0xF1,
- EVENT_ID_FSD_LOAD = 0xF2,
- EVENT_ID_FSD_STORE = 0xF3,
- EVENT_ID_DD_BLOCK = 0xF4,
- EVENT_ID_IS_VIEWER = 0xF5,
-} usb_event_id_t;
-
-typedef enum {
- CALLBACK_NONE = 0,
- CALLBACK_SDRAM_WRITE = 1,
- CALLBACK_SDRAM_READ = 2,
-} usb_event_callback_t;
-
-typedef struct {
- usb_event_id_t id;
- usb_event_callback_t trigger;
- void (*callback)(void);
-} usb_event_t;
-
-
-bool usb_put_event (usb_event_t *event, void *data, uint32_t length);
-void usb_init (void);
-void process_usb (void);
-
-
-#endif